{"id":2229724,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2229724/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/patch/20260428163330.2576313-1-michiel@synopsys.com/","project":{"id":17,"url":"http://patchwork.ozlabs.org/api/1.1/projects/17/?format=json","name":"GNU Compiler Collection","link_name":"gcc","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260428163330.2576313-1-michiel@synopsys.com>","date":"2026-04-28T16:33:30","name":"[v2] RISC-V: Add Synopsys RMX-100 series pipeline description.","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"736c9917b99a668e68f06bcb70dccd2f9b52e633","submitter":{"id":93030,"url":"http://patchwork.ozlabs.org/api/1.1/people/93030/?format=json","name":"Michiel Derhaeg","email":"Michiel.Derhaeg@synopsys.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/gcc/patch/20260428163330.2576313-1-michiel@synopsys.com/mbox/","series":[{"id":501898,"url":"http://patchwork.ozlabs.org/api/1.1/series/501898/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/list/?series=501898","date":"2026-04-28T16:33:30","name":"[v2] RISC-V: Add Synopsys RMX-100 series pipeline description.","version":2,"mbox":"http://patchwork.ozlabs.org/series/501898/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2229724/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2229724/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=synopsys.com header.i=@synopsys.com header.a=rsa-sha256\n header.s=pfptdkimsnps header.b=X3nFtgHz;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=synopsys.com header.i=@synopsys.com header.a=rsa-sha256\n header.s=mail header.b=g53Tjbwi;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; helo=vm01.sourceware.org;\n envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org;\n receiver=patchwork.ozlabs.org)","sourceware.org;\n\tdkim=pass (2048-bit key,\n unprotected) header.d=synopsys.com header.i=@synopsys.com header.a=rsa-sha256\n header.s=pfptdkimsnps header.b=X3nFtgHz;\n\tdkim=pass (2048-bit key,\n unprotected) header.d=synopsys.com header.i=@synopsys.com header.a=rsa-sha256\n header.s=mail header.b=g53Tjbwi","sourceware.org; dmarc=pass (p=quarantine dis=none)\n header.from=synopsys.com","sourceware.org; spf=pass smtp.mailfrom=synopsys.com","server2.sourceware.org;\n arc=none smtp.remote-ip=148.163.156.19"],"Received":["from vm01.sourceware.org (vm01.sourceware.org\n [IPv6:2620:52:6:3111::32])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g4mGg56rDz1xvV\n\tfor ; Wed, 29 Apr 2026 02:34:01 +1000 (AEST)","from vm01.sourceware.org (localhost [127.0.0.1])\n\tby sourceware.org (Postfix) with ESMTP id B30874BA9016\n\tfor ; Tue, 28 Apr 2026 16:33:59 +0000 (GMT)","from mx0a-00230701.pphosted.com (mx0a-00230701.pphosted.com\n [148.163.156.19])\n by sourceware.org (Postfix) with ESMTPS id 161AD4BA799E\n for ; Tue, 28 Apr 2026 16:33:33 +0000 (GMT)","from pps.filterd (m0297266.ppops.net [127.0.0.1])\n by mx0a-00230701.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 63SGCph33495107; Tue, 28 Apr 2026 09:33:32 -0700","from smtprelay-out1.synopsys.com (smtprelay-out1.synopsys.com\n [149.117.87.133])\n by mx0a-00230701.pphosted.com (PPS) with ESMTPS id 4dtmj3mu82-1\n (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NOT);\n Tue, 28 Apr 2026 09:33:31 -0700 (PDT)","from mailhost.synopsys.com (badc-mailhost3.synopsys.com\n [10.192.0.81])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n key-exchange X25519 server-signature RSA-PSS (2048 bits)\n client-signature RSA-PSS (2048 bits))\n (Client CN \"mailhost.synopsys.com\", Issuer \"SNPSica2\" (verified OK))\n by smtprelay-out1.synopsys.com (Postfix) with ESMTPS id 59000401F2;\n Tue, 28 Apr 2026 16:33:31 +0000 (UTC)","from us01arcgnu3.synopsys.com (unknown [10.194.34.166])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest\n SHA256)\n (Client did not present a certificate)\n by mailhost.synopsys.com (Postfix) with ESMTPS id CEE91A0063;\n Tue, 28 Apr 2026 16:33:30 +0000 (UTC)","by us01arcgnu3.synopsys.com (Postfix, from userid 10074339)\n id 9A41A2441DBD0; Tue, 28 Apr 2026 09:33:30 -0700 (PDT)"],"DKIM-Filter":["OpenDKIM Filter v2.11.0 sourceware.org B30874BA9016","OpenDKIM Filter v2.11.0 sourceware.org 161AD4BA799E"],"DMARC-Filter":"OpenDMARC Filter v1.4.2 sourceware.org 161AD4BA799E","ARC-Filter":"OpenARC Filter v1.0.0 sourceware.org 161AD4BA799E","ARC-Seal":"i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1777394013; cv=none;\n b=cU7N2/wNj/A3pVsesJojv9E5zWzBiGvI/x+ctDbwZW27NZyIYVWMl2P39zugSgR0znDClWgIS70Qg+CJHP00pfwrED9hPifgVSCuRaqCgkICXTFscm1WPtF8o+4NfxSjxQXL7CzV2mOFz0DDaPyqP2jD0RuHg94F4lK0PtrF+xU=","ARC-Message-Signature":"i=1; a=rsa-sha256; d=sourceware.org; s=key;\n t=1777394013; c=relaxed/simple;\n bh=V+UtjIMs3iu5mqvoii1CYFG9lkpXQsv7tI1cLGILpjk=;\n h=DKIM-Signature:DKIM-Signature:From:To:Subject:Date:Message-Id:\n MIME-Version;\n b=KfiWNI1H2qbubfqEn9gDYYsIsGAj2FN2A6tOysADORgEVjt+HX4Y7kOLA5oROh/XtN06yZ3VzrkY+DmgcFeihIfsV4Sd2fZ4OZAYb3GUQSYlu6H9OTYQj65KeXfSNmidPmeQAiCk8G0LNSpQQ1QcSM9WnFWJIdndozVLcB2Hl7Q=","ARC-Authentication-Results":"i=1; server2.sourceware.org","DKIM-Signature":["v=1; a=rsa-sha256; c=relaxed/relaxed; d=synopsys.com; h=\n cc:content-transfer-encoding:date:from:message-id:mime-version\n :subject:to; s=pfptdkimsnps; bh=9xR+JW2v9Ig+BJh08SD1wWnunCd9aLd/\n 0bUtwTEcsXA=; b=X3nFtgHzSQ5Er4RjD8LKydbTVNn23l8kxumj2hqkob4kDORA\n j7uQpLEvyyplxNbmsLmPzAoKOhrSQ+eOgP8hWkoNn3tWPVWFdwY9ob/mzD3mh+A2\n ah7BToTlmQVO9o60YyyW0hkebx4xmZiRMH9RtD2rJ9a2K8vJYCf/1RxOZqUKhO0b\n xQLCsdPZ8tfS3NV/DkF7ceYXFQTwp59SIuPwqCSN0B5wvP7fhWfL/00AZpW2S8yy\n 3JjKHKosi6C0Ne0sAAzb59gEL22TlvNJeRi33dz9iJRDaYwoN+mBgZw+1oRrAk4Q\n nnR8GDeWyLkLDmv/BMh+HXjifbXXEJnlqQHEdA==","v=1; a=rsa-sha256; c=relaxed/simple; d=synopsys.com; s=mail;\n t=1777394011; bh=V+UtjIMs3iu5mqvoii1CYFG9lkpXQsv7tI1cLGILpjk=;\n h=From:To:Cc:Subject:Date:From;\n b=g53Tjbwih4SVSVQkYH+KHYcHikQMF6r62K7nuUQbcUXT1jMB/jI2RNrl60Gjg+7UU\n mifPpVYFQIiQ2SX+zaWmfuIJi4TaU206ztteyBqtHhB4wBFa+NJOBUD+BjYyGifnYY\n 8wrXnbw4Gny4Rx6DRb7+wCngKNfCmYhJVSbeyfvALUHqa/Lr7HX/RoNL6qyGcN/yOE\n yvX5aHtG6Zau94elYdpcofrESSppO/Sk8p4uZqcj/0X+x0hudgnDILqmQW23I134XR\n zRPl9a1GlHz7BLco69WSRTRb+5nqFAAforWMz7tk9Ld2JNufAZuvg2tU0x3nkJIW1V\n b/bPpWGWDIDdQ=="],"X-SNPS-Relay":"synopsys.com","From":"Michiel Derhaeg ","To":"jeffrey.law@oss.qualcomm.com","Cc":"gcc-patches@gcc.gnu.org","Subject":"[PATCH v2] RISC-V: Add Synopsys RMX-100 series pipeline description.","Date":"Tue, 28 Apr 2026 09:33:30 -0700","Message-Id":"<20260428163330.2576313-1-michiel@synopsys.com>","X-Mailer":"git-send-email 2.37.1","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Proofpoint-ORIG-GUID":"zm_7pvSZez5CVFE4Cv842302mqBnjTjb","X-Authority-Analysis":"v=2.4 cv=PO8/P/qC c=1 sm=1 tr=0 ts=69f0e15b cx=c_pps\n a=t4gDRyhI9k+KZ5gXRQysFQ==:117 a=t4gDRyhI9k+KZ5gXRQysFQ==:17\n a=A5OVakUREuEA:10 a=qPHU084jO2kA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=tU_645BZ7FZt8VqRJtHG:22 a=Wo6YDfOMAEstGd-0DxeT:22 a=mDV3o1hIAAAA:8\n a=N54-gffFAAAA:8 a=jIQo8A4GAAAA:8 a=l16U_cA9-k3UBWiG3UAA:9","X-Proofpoint-GUID":"zm_7pvSZez5CVFE4Cv842302mqBnjTjb","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNDI4MDE1OSBTYWx0ZWRfX+UmDsRAxuYR/\n vygYVZuXAHKn9VlmeatlNCkdgoKkV0O7yF6m6QhWVEiGka5PCkSU/b3zUCh+g3itAWUARLSp+Xd\n 4XeoVplEllZjNk9IEI5/nUr9dpitHsBGTvcAYM2RL874fGOsfO4A6jG/WuMtnvDvsNjm5HqKdXH\n JYytQA+H3mD/jwRSVNLDoBj5oyfDJV0bkFcTwL3+oj21ns9g3MU3TSTIq8GBYA1AkORCV4CLGY8\n N92YHBu91dgWUU2otnRBHgc5nqWTbWn8QLRLpkQspWFWZAjuIgknxIBXzWB3Ds4hQDIOHlDzqQ/\n Kd9cBxW59npMzAhhkNu3xiDvE8wupV/Z/cuJD77oAxKh5ETPxscJ06+qS/YINjnqw3vk0TI6Vrr\n mvjbFpdThdwkp8+LX9HvoWx+HHPoinoKEVzyFV+X97bfgCeuo7vmOO44RGb9LCpv+LKC/ePTUWU\n HckoEcc4MA8N0wpekug==","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-28_05,2026-04-28_01,2025-10-01_01","X-Proofpoint-Spam-Details":"rule=outbound_active_cloned_notspam\n policy=outbound_active_cloned score=0 priorityscore=1501 impostorscore=0\n bulkscore=0 clxscore=1015 lowpriorityscore=0 spamscore=0 adultscore=0\n malwarescore=0 phishscore=0 suspectscore=0 classifier=typeunknown authscore=0\n authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1\n engine=8.22.0-2604200000 definitions=main-2604280159","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org"},"content":"This patch introduces the pipeline description for the Synopsys RMX-100 series\nprocessor to the RISC-V GCC backend. The RMX-100 has a short, three-stage,\nin-order execution pipeline with configurable multiply unit options.\n\nThe option -mmpy-option was added to control which version of the MPY unit the\ncore has and what the latency of multiply instructions should be similar to\nARCv2 cores (see gcc/config/arc/arc.opt:60).\n\ngcc/ChangeLog:\n\n * config/riscv/riscv-cores.def (RISCV_TUNE): Add arc-v-rmx-100-series.\n * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):\n\tAdd arcv_rmx100.\n (enum arcv_mpy_option_enum): New enum for ARC-V multiply options.\n * config/riscv/riscv-protos.h (arcv_mpy_1c_bypass_p): New declaration.\n (arcv_mpy_2c_bypass_p): New declaration.\n (arcv_mpy_10c_bypass_p): New declaration.\n * config/riscv/riscv.cc (arcv_mpy_1c_bypass_p): New function.\n (arcv_mpy_2c_bypass_p): New function.\n (arcv_mpy_10c_bypass_p): New function.\n * config/riscv/riscv.md: Add arcv_rmx100.\n * config/riscv/riscv.opt: New option for RMX-100 multiply unit\n\tconfiguration.\n * doc/riscv-mtune.texi: Document arc-v-rmx-100-series.\n * config/riscv/arcv-rmx100.md: New file.\n\nCo-authored-by: Artemiy Volkov \nCo-authored-by: Luis Silva \nSigned-off-by: Michiel Derhaeg \n---\nv2:\n - Added reservation for missing insn types\n - use_divmod_expansion is set to true in tune_info\n - Reservation for DIV functional unit is clamped to 7 cycles\n - Don't use nothing*N at the end of reservations\n\n gcc/config/riscv/arcv-rmx100.md | 127 +++++++++++++++++++++++++++++++\n gcc/config/riscv/riscv-cores.def | 1 +\n gcc/config/riscv/riscv-opts.h | 8 ++\n gcc/config/riscv/riscv-protos.h | 4 +\n gcc/config/riscv/riscv.cc | 49 ++++++++++++\n gcc/config/riscv/riscv.md | 4 +-\n gcc/config/riscv/riscv.opt | 17 +++++\n gcc/doc/riscv-mtune.texi | 2 +\n 8 files changed, 211 insertions(+), 1 deletion(-)\n create mode 100644 gcc/config/riscv/arcv-rmx100.md","diff":"diff --git a/gcc/config/riscv/arcv-rmx100.md b/gcc/config/riscv/arcv-rmx100.md\nnew file mode 100644\nindex 00000000000..e573a456db1\n--- /dev/null\n+++ b/gcc/config/riscv/arcv-rmx100.md\n@@ -0,0 +1,127 @@\n+;; DFA scheduling description of the Synopsys RMX-100 cpu\n+;; for GNU C compiler\n+;; Copyright (C) 2026 Free Software Foundation, Inc.\n+\n+;; This file is part of GCC.\n+\n+;; GCC is free software; you can redistribute it and/or modify\n+;; it under the terms of the GNU General Public License as published by\n+;; the Free Software Foundation; either version 3, or (at your option)\n+;; any later version.\n+\n+;; GCC is distributed in the hope that it will be useful,\n+;; but WITHOUT ANY WARRANTY; without even the implied warranty of\n+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n+;; GNU General Public License for more details.\n+\n+;; You should have received a copy of the GNU General Public License\n+;; along with GCC; see the file COPYING3. If not see\n+;; .\n+\n+(define_automaton \"arcv_rmx100\")\n+\n+(define_cpu_unit \"arcv_rmx100_ALU\" \"arcv_rmx100\")\n+(define_cpu_unit \"arcv_rmx100_FPU\" \"arcv_rmx100\")\n+(define_cpu_unit \"arcv_rmx100_MPY\" \"arcv_rmx100\")\n+(define_cpu_unit \"arcv_rmx100_DIV\" \"arcv_rmx100\")\n+(define_cpu_unit \"arcv_rmx100_DMP\" \"arcv_rmx100\")\n+\n+;; Instruction reservation for arithmetic instructions.\n+(define_insn_reservation \"arcv_rmx100_alu_arith\" 1\n+ (and (eq_attr \"tune\" \"arcv_rmx100\")\n+ (eq_attr \"type\" \"unknown, const, arith, shift, slt, multi, auipc, nop,\n+\t\t\tlogical, move, atomic, mvpair, bitmanip, clz, ctz, cpop,\n+\t\t\tzicond, condmove, clmul, min, max, minu, maxu, rotate\"))\n+ \"arcv_rmx100_ALU\")\n+\n+(define_insn_reservation \"arcv_rmx100_jmp_insn\" 1\n+ (and (eq_attr \"tune\" \"arcv_rmx100\")\n+ (eq_attr \"type\" \"branch, jump, call, jalr, ret, trap\"))\n+ \"arcv_rmx100_ALU\")\n+\n+; DIV insn: latency may be overridden by a define_bypass\n+(define_insn_reservation \"arcv_rmx100_div_insn\" 35\n+ (and (eq_attr \"tune\" \"arcv_rmx100\")\n+ (eq_attr \"type\" \"idiv\"))\n+ \"arcv_rmx100_DIV*7\")\n+\n+; MPY insn: latency may be overridden by a define_bypass\n+(define_insn_reservation \"arcv_rmx100_mpy32_insn\" 9\n+ (and (eq_attr \"tune\" \"arcv_rmx100\")\n+ (eq_attr \"type\" \"imul\"))\n+ \"arcv_rmx100_MPY\")\n+\n+(define_insn_reservation \"arcv_rmx100_load_insn\" 3\n+ (and (eq_attr \"tune\" \"arcv_rmx100\")\n+ (eq_attr \"type\" \"load\"))\n+ \"arcv_rmx100_DMP\")\n+\n+(define_insn_reservation \"arcv_rmx100_store_insn\" 1\n+ (and (eq_attr \"tune\" \"arcv_rmx100\")\n+ (eq_attr \"type\" \"store,fpstore\"))\n+ \"arcv_rmx100_DMP\")\n+\n+;; FPU scheduling. This is based on the \"fast\" unit for now.\n+\n+(define_insn_reservation \"arcv_rmx100_fpload_insn\" 3\n+ (and (eq_attr \"tune\" \"arcv_rmx100\")\n+ (eq_attr \"type\" \"fpload\"))\n+ \"arcv_rmx100_DMP\")\n+\n+(define_insn_reservation \"arcv_rmx100_farith_insn\" 2\n+ (and (eq_attr \"tune\" \"arcv_rmx100\")\n+ (eq_attr \"type\" \"fadd,fcmp\"))\n+ \"arcv_rmx100_FPU\")\n+\n+(define_insn_reservation \"arcv_rmx100_xfer\" 1\n+ (and (eq_attr \"tune\" \"arcv_rmx100\")\n+ (eq_attr \"type\" \"fmove,mtc,mfc,fcvt,fcvt_f2i,fcvt_i2f\"))\n+ \"arcv_rmx100_FPU\")\n+\n+(define_insn_reservation \"arcv_rmx100_fmul_insn\" 2\n+ (and (eq_attr \"tune\" \"arcv_rmx100\")\n+ (eq_attr \"type\" \"fmul\"))\n+ \"arcv_rmx100_FPU\")\n+\n+(define_insn_reservation \"arcv_rmx100_fmac_insn\" 2\n+ (and (eq_attr \"tune\" \"arcv_rmx100\")\n+ (eq_attr \"type\" \"fmadd\"))\n+ \"arcv_rmx100_FPU\")\n+\n+(define_insn_reservation \"arcv_rmx100_fdiv_insn\" 10\n+ (and (eq_attr \"tune\" \"arcv_rmx100\")\n+ (eq_attr \"type\" \"fdiv,fsqrt\"))\n+ \"arcv_rmx100_FPU\")\n+\n+(define_insn_reservation \"arcv_rmx100_unknown\" 5\n+ (and (eq_attr \"tune\" \"arcv_rmx100\")\n+ (eq_attr \"type\" \"vfwalu,vfwcvtftoi,vrol,vmidx,vext,vaeskf1,vfredo,\n+ vector,sfb_alu,vlds,viminmax,vfcmp,vimov,vsmul,vnclip,\n+ vldm,vsetvl_pre,vwsll,vfmerge,vmffs,vclmul,vmpop,wrfrm,\n+ vsha2ms,vidiv,vfncvtitof,vaesef,vldr,vlsegdox,vfwmul,\n+ vfmul,vfredu,crypto,vmalu,vimul,vghsh,vialu,viwmul,\n+ vfcvtftoi,vaalu,vislide1up,vfcvtitof,vfwcvtftof,vgather,\n+ vaesz,vbrev,vshift,vsha2ch,vssegtux,vssegtox,vcompress,\n+ vcpop,vstux,vfncvtftof,vfrecp,vssegts,sf_vfnrclip,\n+ vstox,vstr,vlsegdff,vired,vimovvx,vislide1down,vclz,\n+ vfwredu,rdvl,vlde,vaesem,vsm3me,vmiota,vldux,vlsegde,\n+ vssegte,vfwmaccbf16,vfwredo,vctz,vsm4k,vsshift,vsts,\n+ vmsfs,vfmovvf,vfslide1down,viwred,vslidedown,vfncvtftoi,\n+ vsm3c,vnshift,vfalu,vfsqrt,wrvxrm,vfmuladd,vmov,vsetvl,\n+ vfclass,vsha2cl,vicmp,vldff,vfdiv,vste,vaeskf2,\n+ vfncvtbf16,vandn,vbrev8,vgmul,vaesdm,vlsegdux,vfsgnj,\n+ vfmov,rdfrm,vlsegds,vclmulh,vimuladd,viwalu,vfwmuladd,\n+ vimerge,vror,rdvlenb,vfwcvtitof,vaesdf,viwmuladd,vrev8,\n+ vsm4r,vsalu,vfminmax,vicalu,vslideup,vldox,vstm,\n+ vfwcvtbf16,vfmovfv,vfslide1up,vimovxv,sf_vc,sf_vqmacc,\n+ sf_vc_se\"))\n+ \"arcv_rmx100_ALU\")\n+\n+\n+(define_bypass 1 \"arcv_rmx100_mpy32_insn\"\n+ \"arcv_rmx100_*\" \"arcv_mpy_1c_bypass_p\")\n+(define_bypass 2 \"arcv_rmx100_mpy32_insn\"\n+ \"arcv_rmx100_*\" \"arcv_mpy_2c_bypass_p\")\n+\n+(define_bypass 9 \"arcv_rmx100_div_insn\" \"arcv_rmx100_*\" \"arcv_mpy_1c_bypass_p\")\n+(define_bypass 9 \"arcv_rmx100_div_insn\" \"arcv_rmx100_*\" \"arcv_mpy_2c_bypass_p\")\ndiff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def\nindex 79a460f8176..5c8f12a15a9 100644\n--- a/gcc/config/riscv/riscv-cores.def\n+++ b/gcc/config/riscv/riscv-cores.def\n@@ -57,6 +57,7 @@ RISCV_TUNE(\"mips-p8700\", mips_p8700, mips_p8700_tune_info)\n RISCV_TUNE(\"andes-25-series\", andes_25_series, andes_25_tune_info)\n RISCV_TUNE(\"andes-23-series\", andes_23_series, andes_23_tune_info)\n RISCV_TUNE(\"andes-45-series\", andes_45_series, andes_45_tune_info)\n+RISCV_TUNE(\"arc-v-rmx-100-series\", arcv_rmx100, arcv_rmx100_tune_info)\n \n #undef RISCV_TUNE\n \ndiff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h\nindex 1c44bc4e6ec..fdcdba88d6e 100644\n--- a/gcc/config/riscv/riscv-opts.h\n+++ b/gcc/config/riscv/riscv-opts.h\n@@ -65,6 +65,7 @@ enum riscv_microarchitecture_type {\n andes_23_series,\n andes_45_series,\n spacemit_x60,\n+ arcv_rmx100,\n };\n extern enum riscv_microarchitecture_type riscv_microarchitecture;\n \n@@ -92,6 +93,13 @@ enum rvv_max_lmul_enum {\n RVV_CONV_DYNAMIC = 10\n };\n \n+/* ARC-V multiply option. */\n+enum arcv_mpy_option_enum {\n+ ARCV_MPY_OPTION_1C = 1,\n+ ARCV_MPY_OPTION_2C = 2,\n+ ARCV_MPY_OPTION_10C = 8,\n+};\n+\n enum riscv_multilib_select_kind {\n /* Select multilib by builtin way. */\n select_by_builtin,\ndiff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h\nindex dd029c70413..db17cf19110 100644\n--- a/gcc/config/riscv/riscv-protos.h\n+++ b/gcc/config/riscv/riscv-protos.h\n@@ -840,6 +840,10 @@ extern const char *th_output_move (rtx, rtx);\n extern bool th_print_operand_address (FILE *, machine_mode, rtx);\n #endif\n \n+extern bool arcv_mpy_1c_bypass_p (rtx_insn *, rtx_insn *);\n+extern bool arcv_mpy_2c_bypass_p (rtx_insn *, rtx_insn *);\n+extern bool arcv_mpy_10c_bypass_p (rtx_insn *, rtx_insn *);\n+\n extern bool strided_load_broadcast_p (void);\n extern bool riscv_prefer_agnostic_p (void);\n extern bool riscv_use_divmod_expander (void);\ndiff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc\nindex 615750f0744..a1ca80b7605 100644\n--- a/gcc/config/riscv/riscv.cc\n+++ b/gcc/config/riscv/riscv.cc\n@@ -837,6 +837,31 @@ static const struct riscv_tune_param andes_45_tune_info = {\n true,\t\t\t\t\t\t/* prefer-agnostic. */\n };\n \n+/* Costs to use when optimizing for Synopsys RMX-100. */\n+static const struct riscv_tune_param arcv_rmx100_tune_info = {\n+ {COSTS_N_INSNS (2), COSTS_N_INSNS (2)},\t/* fp_add */\n+ {COSTS_N_INSNS (2), COSTS_N_INSNS (2)},\t/* fp_mul */\n+ {COSTS_N_INSNS (17), COSTS_N_INSNS (17)},\t/* fp_div */\n+ {COSTS_N_INSNS (2), COSTS_N_INSNS (2)},\t/* int_mul */\n+ {COSTS_N_INSNS (17), COSTS_N_INSNS (17)},\t/* int_div */\n+ 1,\t\t\t\t\t\t/* issue_rate */\n+ 4,\t\t\t\t\t\t/* branch_cost */\n+ 2,\t\t\t\t\t\t/* memory_cost */\n+ 4,\t\t\t\t\t\t/* fmv_cost */\n+ false,\t\t\t\t\t/* slow_unaligned_access */\n+ false,\t\t\t\t\t/* vector_unaligned_access */\n+ true,\t\t\t\t\t\t/* use_divmod_expansion */\n+ false,\t\t\t\t\t/* overlap_op_by_pieces */\n+ true,\t\t\t\t\t\t/* use_zero_stride_load */\n+ false,\t\t\t\t\t/* speculative_sched_vsetvl */\n+ RISCV_FUSE_NOTHING,\t\t\t\t/* fusible_ops */\n+ NULL,\t\t\t\t\t\t/* vector cost */\n+ NULL,\t\t\t\t\t\t/* function_align */\n+ NULL,\t\t\t\t\t\t/* jump_align */\n+ NULL,\t\t\t\t\t\t/* loop_align */\n+ true,\t\t\t\t\t\t/* prefer-agnostic. */\n+};\n+\n static bool riscv_avoid_shrink_wrapping_separate ();\n static tree riscv_handle_fndecl_attribute (tree *, tree, tree, int, bool *);\n static tree riscv_handle_type_attribute (tree *, tree, tree, int, bool *);\n@@ -10706,6 +10731,30 @@ riscv_store_data_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)\n return store_data_bypass_p (out_insn, in_insn);\n }\n \n+/* Implement one boolean function for each of the values of the\n+ arcv_mpy_option enum, for the needs of arcv-rmx100.md. */\n+\n+bool\n+arcv_mpy_1c_bypass_p (rtx_insn *out_insn ATTRIBUTE_UNUSED,\n+\t\t rtx_insn *in_insn ATTRIBUTE_UNUSED)\n+{\n+ return arcv_mpy_option == ARCV_MPY_OPTION_1C;\n+}\n+\n+bool\n+arcv_mpy_2c_bypass_p (rtx_insn *out_insn ATTRIBUTE_UNUSED,\n+\t\t rtx_insn *in_insn ATTRIBUTE_UNUSED)\n+{\n+ return arcv_mpy_option == ARCV_MPY_OPTION_2C;\n+}\n+\n+bool\n+arcv_mpy_10c_bypass_p (rtx_insn *out_insn ATTRIBUTE_UNUSED,\n+\t\t\trtx_insn *in_insn ATTRIBUTE_UNUSED)\n+{\n+ return arcv_mpy_option == ARCV_MPY_OPTION_10C;\n+}\n+\n /* Implement TARGET_SECONDARY_MEMORY_NEEDED.\n \n When floating-point registers are wider than integer ones, moves between\ndiff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md\nindex 3487ab1954e..a0aaff1f404 100644\n--- a/gcc/config/riscv/riscv.md\n+++ b/gcc/config/riscv/riscv.md\n@@ -679,7 +679,8 @@\n ;; Keep this in sync with enum riscv_microarchitecture.\n (define_attr \"tune\"\n \"generic,sifive_7,sifive_p400,sifive_p600,xiangshan,generic_ooo,mips_p8700,\n- tt_ascalon_d8,andes_25_series,andes_23_series,andes_45_series,spacemit_x60\"\n+ tt_ascalon_d8,andes_25_series,andes_23_series,andes_45_series,spacemit_x60,\n+ arcv_rmx100\"\n (const (symbol_ref \"((enum attr_tune) riscv_microarchitecture)\")))\n \n ;; Describe a user's asm statement.\n@@ -5163,3 +5164,4 @@\n (include \"andes-25-series.md\")\n (include \"andes-45-series.md\")\n (include \"spacemit-x60.md\")\n+(include \"arcv-rmx100.md\")\ndiff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt\nindex 2c26ee99691..c6e099eb47e 100644\n--- a/gcc/config/riscv/riscv.opt\n+++ b/gcc/config/riscv/riscv.opt\n@@ -423,3 +423,20 @@ Specifies whether the fence.tso instruction should be used.\n mautovec-segment\n Target Integer Var(riscv_mautovec_segment) Init(1)\n Enable (default) or disable generation of vector segment load/store instructions.\n+\n+Enum\n+Name(arcv_mpy_option) Type(enum arcv_mpy_option_enum)\n+Valid arguments to -mmpy_option=:\n+\n+EnumValue\n+Enum(arcv_mpy_option) String(1c) Value(ARCV_MPY_OPTION_1C)\n+\n+EnumValue\n+Enum(arcv_mpy_option) String(2c) Value(ARCV_MPY_OPTION_2C)\n+\n+EnumValue\n+Enum(arcv_mpy_option) String(10c) Value(ARCV_MPY_OPTION_10C)\n+\n+mmpy-option=\n+Target RejectNegative Joined Enum(arcv_mpy_option) Var(arcv_mpy_option) Init(ARCV_MPY_OPTION_2C)\n+The type of MPY unit used by the RMX-100 core (to be used in combination with -mtune=arc-v-rmx-100-series) (default: 2c).\ndiff --git a/gcc/doc/riscv-mtune.texi b/gcc/doc/riscv-mtune.texi\nindex 6865bd6fbf7..2a867e55ba1 100644\n--- a/gcc/doc/riscv-mtune.texi\n+++ b/gcc/doc/riscv-mtune.texi\n@@ -64,4 +64,6 @@ particular CPU name. Permissible values for this option are:\n \n @samp{andes-45-series},\n \n+@samp{arc-v-rmx-100-series},\n+\n and all valid options for @option{-mcpu=}.\n","prefixes":["v2"]}