{"id":2229702,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2229702/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/patch/62ef3eed-0fba-4400-bc4a-c7fe40189fe9@oss.qualcomm.com/","project":{"id":17,"url":"http://patchwork.ozlabs.org/api/1.1/projects/17/?format=json","name":"GNU Compiler Collection","link_name":"gcc","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<62ef3eed-0fba-4400-bc4a-c7fe40189fe9@oss.qualcomm.com>","date":"2026-04-28T16:12:13","name":"[V2,to-be-committed,RISC-V,PR,target/124760] Promote SI to DI in some cases to encourage shNadd insns","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"84eb788e9bbac0099fd3dcc2d9f5c9564eebe8cd","submitter":{"id":92310,"url":"http://patchwork.ozlabs.org/api/1.1/people/92310/?format=json","name":"Jeffrey Law","email":"jeffrey.law@oss.qualcomm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/gcc/patch/62ef3eed-0fba-4400-bc4a-c7fe40189fe9@oss.qualcomm.com/mbox/","series":[{"id":501893,"url":"http://patchwork.ozlabs.org/api/1.1/series/501893/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/list/?series=501893","date":"2026-04-28T16:12:13","name":"[V2,to-be-committed,RISC-V,PR,target/124760] Promote SI to DI in some cases to encourage shNadd insns","version":2,"mbox":"http://patchwork.ozlabs.org/series/501893/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2229702/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2229702/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=TzNQCKvG;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=HgAwM4eL;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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boundary=\"------------BvpyJ4ZAdrB0GBBCj1zxEc77\"","Message-ID":"<62ef3eed-0fba-4400-bc4a-c7fe40189fe9@oss.qualcomm.com>","Date":"Tue, 28 Apr 2026 10:12:13 -0600","MIME-Version":"1.0","User-Agent":"Mozilla Thunderbird","Content-Language":"en-US","To":"'GCC Patches' ","From":"Jeffrey Law ","Subject":"[V2][to-be-committed][RISC-V][PR target/124760] Promote SI to DI in\n some cases to encourage shNadd insns","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNDI4MDE1NSBTYWx0ZWRfXzpOeyAqUNrum\n jEIxpvVZX0l/bCUkhHDnHj+wgwDQafxdUagbIMIFeaqS4wKb9Uphp7DOMoyvi6nnCzw85I6waxB\n iV5ZjlUvJHRTHTf8CP6QhouAyL61er+QxSa46GTNvW58oEyfHMuLlGNiZs2iGYz/6j1K8ayllmi\n d3OZM8dzM70nXoy7zJAg8jNCJCFkNhQ+wkZ+vAOP1o+3tcG5e7VeatuNR/L03mOuy0L4NtQMOAk\n qQBa6/zC+yMjMM3W9+uMg3/tCZVeZgyTdVJ6KaxaaXqZH9GusyJDMamcjWbzVbG/u0fdhiLjRtA\n YTT6pKf0YvyTrZP6f91nlOpA2fk0laI6SAF/h3xvqS/JlX52l+qE83uA3IzKB10eRNkHoFcdP+Q\n 8nWjVVymCYuFJ9p9Q2lfe7Il4KxBBwhhb5M9w59ah7vgVfr1iSLW2wCDKgB97V6y0mbnUwli3mm\n xpS8SaHmpLP0kFr2XCw==","X-Authority-Analysis":"v=2.4 cv=TZKmcxQh c=1 sm=1 tr=0 ts=69f0dc61 cx=c_pps\n a=SvEPeNj+VMjHSW//kvnxuw==:117 a=asGLMfRmzhnGNxaIYohjRg==:17\n a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=r77TgQKjGQsHNAKrUKIA:9\n a=3zepaaOLL7rTLR81kakA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10\n a=hHoaQ_RVztWCwp0LMOMA:9 a=7DkWtjWK4BqEV9Rf:21 a=_W_S_7VecoQA:10\n a=-d7-HylfX6lhVPyK7WUA:9 a=B2y7HmGcmWMA:10 a=Kq8ClHjjuc5pcCNDwlU0:22","X-Proofpoint-GUID":"DbLfdk8-RATUlUKhZqyDz9arOHBrHJQ6","X-Proofpoint-ORIG-GUID":"DbLfdk8-RATUlUKhZqyDz9arOHBrHJQ6","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-28_05,2026-04-28_01,2025-10-01_01","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n priorityscore=1501 spamscore=0 adultscore=0 phishscore=0 clxscore=1015\n suspectscore=0 bulkscore=0 malwarescore=0 impostorscore=0 lowpriorityscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604280155","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org"},"content":"No real changes.  Just posting a V2 to see if it'll get picked up by the \npre-commit tester.  Two patches (this being one of them) never started \ntesting yesterday.  No clue why and I haven't heard from Edwin on how to \ndebug the pre-commit tester state.\n\n--\n\n\nSo for this testcase:\n\n\nint foo (int t)\n  {\n    return 3 * t - 1;\n  }\n\nWe currently generate:\n\n\n     slliw    a5,a0,1\n     addw    a0,a5,a0\n     addiw    a0,a0,-1\n     ret\n\n\nIntuitively we can see we're doing a 32->64 sign extension at each step \nand we could drop the intermediate sign extensions.  In fact, not only \ncan we drop the intermediate sign extensions, we can safely \"promote\" \nthe intermediate operations from SI to DI with a final sign extending \nadd.  Conceptually that unlocks combining the first shift+add into a \nshNadd insn resulting in this code:\n\n     sh1add    a0, a0, a0\n     addiw    a0, a0, -1\n     ret\n\nThe patch, but not the testcase, has been in my tree for a while, so \nit's been through bootstrap & regression testing on the BPI and Pioneer \nas well as testing on riscv32-elf and riscv64-elf. Obviously I'll wait \nfor pre-commit CI to do its thing before pushing.\n\nJeff\nPR target/124760\ngcc/\n\t* config/riscv/bitmanip.md (SI->DI promoting shadd pattern): Promote\n\tintermediate SI ops to DI ops when there's a final extending op.\n\ngcc/testsuite\n\n\t* gcc.target/riscv/pr124760.c: New test.","diff":"diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md\nindex 45881994f3ad..4b896b792678 100644\n--- a/gcc/config/riscv/bitmanip.md\n+++ b/gcc/config/riscv/bitmanip.md\n@@ -1368,3 +1368,19 @@ (define_split\n (set (match_dup 0) (zero_extract:X (match_dup 3)\n \t\t\t\t (const_int 1)\n \t\t\t\t (zero_extend:X (match_dup 2))))])\n+\n+(define_split\n+ [(set (match_operand:DI 0 \"register_operand\")\n+\t(sign_extend:DI (plus:SI (plus:SI (ashift:SI (match_operand:SI 1 \"register_operand\")\n+\t\t\t\t\t\t (match_operand 2 \"imm123_operand\"))\n+\t\t\t\t\t (match_operand:SI 3 \"register_operand\"))\n+\t\t\t\t (match_operand:SI 4 \"arith_operand\"))))\n+ (clobber (match_operand:DI 5 \"register_operand\"))]\n+ \"TARGET_64BIT && TARGET_ZBA\"\n+ [(set (match_dup 5) (plus:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))\n+ (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 6) (match_dup 4))))]\n+ {\n+ operands[1] = gen_lowpart (DImode, operands[1]);\n+ operands[3] = gen_lowpart (DImode, operands[3]);\n+ operands[6] = gen_lowpart (SImode, operands[5]);\n+ })\ndiff --git a/gcc/testsuite/gcc.target/riscv/pr124760.c b/gcc/testsuite/gcc.target/riscv/pr124760.c\nnew file mode 100644\nindex 000000000000..0c4768ff0474\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/pr124760.c\n@@ -0,0 +1,14 @@\n+/* { dg-do compile { target rv64 } } */\n+/* { dg-additional-options \"-march=rv64gcb_zicond -mabi=lp64d\" } */\n+/* { dg-skip-if \"\" { *-*-* } { \"-O0\" \"-Og\" \"-Os\" \"-Oz\" } } */\n+\n+\n+int foo (int t)\n+{\n+ return 3 * t - 1;\n+}\n+\n+/* { dg-final { scan-assembler-not \"slliw\\t\" } } */\n+/* { dg-final { scan-assembler-not \"addw\\t\" } } */\n+/* { dg-final { scan-assembler-times \"sh1add\\t\" 1 } } */\n+/* { dg-final { scan-assembler-times \"addiw\\t\" 1 } } */\n","prefixes":["V2","to-be-committed","RISC-V","PR","target/124760"]}