{"id":2229589,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2229589/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/patch/20260428135614.2A39F4B920AC@sourceware.org/","project":{"id":17,"url":"http://patchwork.ozlabs.org/api/1.1/projects/17/?format=json","name":"GNU Compiler Collection","link_name":"gcc","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260428135614.2A39F4B920AC@sourceware.org>","date":"2026-04-28T13:55:45","name":"[x86] Adjust gcc.target/i386/vect-strided-?.c for cost compare","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"6456564812f4db6f1fb02dd1852ef2de1f42e170","submitter":{"id":4338,"url":"http://patchwork.ozlabs.org/api/1.1/people/4338/?format=json","name":"Richard Biener","email":"rguenther@suse.de"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/gcc/patch/20260428135614.2A39F4B920AC@sourceware.org/mbox/","series":[{"id":501860,"url":"http://patchwork.ozlabs.org/api/1.1/series/501860/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/list/?series=501860","date":"2026-04-28T13:55:45","name":"[x86] Adjust gcc.target/i386/vect-strided-?.c for cost compare","version":1,"mbox":"http://patchwork.ozlabs.org/series/501860/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2229589/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2229589/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=suse.de header.i=@suse.de header.a=rsa-sha256\n header.s=susede2_rsa header.b=D16DibeH;\n\tdkim=pass header.d=suse.de header.i=@suse.de header.a=ed25519-sha256\n header.s=susede2_ed25519 header.b=oJxL0HQW;\n\tdkim=pass (1024-bit key) header.d=suse.de header.i=@suse.de\n header.a=rsa-sha256 header.s=susede2_rsa header.b=DF4EfUcJ;\n\tdkim=neutral header.d=suse.de header.i=@suse.de header.a=ed25519-sha256\n header.s=susede2_ed25519 header.b=9n0cCT6w;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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charset=US-ASCII","X-Spamd-Result":"default: False [-1.80 / 50.00]; BAYES_HAM(-3.00)[100.00%];\n MISSING_MID(2.50)[]; NEURAL_HAM_LONG(-1.00)[-1.000];\n NEURAL_HAM_SHORT(-0.20)[-0.999]; MIME_GOOD(-0.10)[text/plain];\n ARC_NA(0.00)[]; FROM_HAS_DN(0.00)[];\n FUZZY_RATELIMITED(0.00)[rspamd.com]; MISSING_XM_UA(0.00)[];\n RCVD_COUNT_ZERO(0.00)[0]; RCPT_COUNT_TWO(0.00)[2];\n DKIM_SIGNED(0.00)[suse.de:s=susede2_rsa,suse.de:s=susede2_ed25519];\n FROM_EQ_ENVFROM(0.00)[]; MIME_TRACE(0.00)[0:+];\n TO_DN_NONE(0.00)[]; TO_MATCH_ENVRCPT_ALL(0.00)[];\n SUBJECT_HAS_QUESTION(0.00)[]","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org","Message-Id":"<20260428135614.2A39F4B920AC@sourceware.org>"},"content":"With cost comparison and MMX-with-SSE vector width available we\nprefer to use V2SImode over V4SImode with shuffles, rightfully\nso I think. The following adds variants with explicit cost\ncompare enabled and disabled and adjusts the cost comparison\nvariant accordingly.\n\nTested on x86_64 with {,-m32,-mx32}.\n\nOK?\n\nThanks,\nRichard.\n\n\t* gcc.target/i386/vect-strided-1.c: Disable vector cost\n\tcomparison.\n\t* gcc.target/i386/vect-strided-2.c: Likewise.\n\t* gcc.target/i386/vect-strided-3.c: Likewise.\n\t* gcc.target/i386/vect-strided-4.c: Likewise.\n\t* gcc.target/i386/vect-strided-1b.c: Copy of\n\tgcc.target/i386/vect-strided-1.c, enable vector cost comparison\n\tand adjust expected code generation.\n\t* gcc.target/i386/vect-strided-2b.c: Likewise.\n\t* gcc.target/i386/vect-strided-3b.c: Likewise.\n\t* gcc.target/i386/vect-strided-4b.c: Likewise.\n---\n .../gcc.target/i386/vect-strided-1.c | 2 +-\n .../gcc.target/i386/vect-strided-1b.c | 23 +++++++++++++++++++\n .../gcc.target/i386/vect-strided-2.c | 2 +-\n .../gcc.target/i386/vect-strided-2b.c | 17 ++++++++++++++\n .../gcc.target/i386/vect-strided-3.c | 2 +-\n .../gcc.target/i386/vect-strided-3b.c | 20 ++++++++++++++++\n .../gcc.target/i386/vect-strided-4.c | 2 +-\n .../gcc.target/i386/vect-strided-4b.c | 19 +++++++++++++++\n 8 files changed, 83 insertions(+), 4 deletions(-)\n create mode 100644 gcc/testsuite/gcc.target/i386/vect-strided-1b.c\n create mode 100644 gcc/testsuite/gcc.target/i386/vect-strided-2b.c\n create mode 100644 gcc/testsuite/gcc.target/i386/vect-strided-3b.c\n create mode 100644 gcc/testsuite/gcc.target/i386/vect-strided-4b.c","diff":"diff --git a/gcc/testsuite/gcc.target/i386/vect-strided-1.c b/gcc/testsuite/gcc.target/i386/vect-strided-1.c\nindex db4a06711f1..8e232540bd4 100644\n--- a/gcc/testsuite/gcc.target/i386/vect-strided-1.c\n+++ b/gcc/testsuite/gcc.target/i386/vect-strided-1.c\n@@ -1,5 +1,5 @@\n /* { dg-do compile } */\n-/* { dg-options \"-O2 -msse2 -mno-avx\" } */\n+/* { dg-options \"-O2 -msse2 -mno-avx --param ix86-vect-compare-costs=0\" } */\n \n void foo (int * __restrict a, int *b, int s)\n {\ndiff --git a/gcc/testsuite/gcc.target/i386/vect-strided-1b.c b/gcc/testsuite/gcc.target/i386/vect-strided-1b.c\nnew file mode 100644\nindex 00000000000..6f173eaea5c\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/i386/vect-strided-1b.c\n@@ -0,0 +1,23 @@\n+/* { dg-do compile { target { ! ia32 } } } */\n+/* { dg-options \"-O2 -msse2 -mno-avx --param ix86-vect-compare-costs=1\" } */\n+\n+void foo (int * __restrict a, int *b, int s)\n+{\n+ for (int i = 0; i < 1024; ++i)\n+ {\n+ a[8*i+0] = b[s*i+0];\n+ a[8*i+1] = b[s*i+1];\n+ a[8*i+2] = b[s*i+2];\n+ a[8*i+3] = b[s*i+3];\n+ a[8*i+4] = b[s*i+4];\n+ a[8*i+5] = b[s*i+5];\n+ a[8*i+6] = b[s*i+4];\n+ a[8*i+7] = b[s*i+5];\n+ }\n+}\n+\n+/* Three two-element loads, four two-element stores. No wider loads\n+ or permutes. */\n+/* { dg-final { scan-assembler-times \"movq\" 7 } } */\n+/* { dg-final { scan-assembler-times \"movhps\" 0 } } */\n+/* { dg-final { scan-assembler-times \"movups\" 0 } } */\ndiff --git a/gcc/testsuite/gcc.target/i386/vect-strided-2.c b/gcc/testsuite/gcc.target/i386/vect-strided-2.c\nindex 6fd64e28cf0..67aa3917c4e 100644\n--- a/gcc/testsuite/gcc.target/i386/vect-strided-2.c\n+++ b/gcc/testsuite/gcc.target/i386/vect-strided-2.c\n@@ -1,5 +1,5 @@\n /* { dg-do compile } */\n-/* { dg-options \"-O2 -msse2 -mno-avx\" } */\n+/* { dg-options \"-O2 -msse2 -mno-avx --param ix86-vect-compare-costs=0\" } */\n \n void foo (int * __restrict a, int *b, int s)\n {\ndiff --git a/gcc/testsuite/gcc.target/i386/vect-strided-2b.c b/gcc/testsuite/gcc.target/i386/vect-strided-2b.c\nnew file mode 100644\nindex 00000000000..9eabfbb082b\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/i386/vect-strided-2b.c\n@@ -0,0 +1,17 @@\n+/* { dg-do compile { target { ! ia32 } } } */\n+/* { dg-options \"-O2 -msse2 -mno-avx --param ix86-vect-compare-costs=1\" } */\n+\n+void foo (int * __restrict a, int *b, int s)\n+{\n+ for (int i = 0; i < 1024; ++i)\n+ {\n+ a[4*i+0] = b[s*i+0];\n+ a[4*i+1] = b[s*i+1];\n+ a[4*i+2] = b[s*i+0];\n+ a[4*i+3] = b[s*i+1];\n+ }\n+}\n+\n+/* One two-element load, two two-element stores. */\n+/* { dg-final { scan-assembler-times \"movq\" 3 } } */\n+/* { dg-final { scan-assembler-times \"movups\" 0 } } */\ndiff --git a/gcc/testsuite/gcc.target/i386/vect-strided-3.c b/gcc/testsuite/gcc.target/i386/vect-strided-3.c\nindex f9c54a6f715..d08d5836a7a 100644\n--- a/gcc/testsuite/gcc.target/i386/vect-strided-3.c\n+++ b/gcc/testsuite/gcc.target/i386/vect-strided-3.c\n@@ -1,5 +1,5 @@\n /* { dg-do compile } */\n-/* { dg-options \"-O2 -msse2 -mno-sse4 -fno-tree-slp-vectorize\" } */\n+/* { dg-options \"-O2 -msse2 -mno-sse4 -fno-tree-slp-vectorize --param ix86-vect-compare-costs=0\" } */\n \n void foo (int * __restrict a, int *b, int s)\n {\ndiff --git a/gcc/testsuite/gcc.target/i386/vect-strided-3b.c b/gcc/testsuite/gcc.target/i386/vect-strided-3b.c\nnew file mode 100644\nindex 00000000000..829fb0ccd39\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/i386/vect-strided-3b.c\n@@ -0,0 +1,20 @@\n+/* { dg-do compile { target { ! ia32 } } } */\n+/* { dg-options \"-O2 -msse2 -mno-sse4 -fno-tree-slp-vectorize --param ix86-vect-compare-costs=1\" } */\n+\n+void foo (int * __restrict a, int *b, int s)\n+{\n+ if (s >= 6)\n+ for (int i = 0; i < 1024; ++i)\n+ {\n+\ta[s*i+0] = b[4*i+0];\n+\ta[s*i+1] = b[4*i+1];\n+\ta[s*i+2] = b[4*i+2];\n+\ta[s*i+3] = b[4*i+3];\n+\ta[s*i+4] = b[4*i+0];\n+\ta[s*i+5] = b[4*i+1];\n+ }\n+}\n+\n+/* The vectorizer generates 3 uint64 stores and two uint64 loads. */\n+/* { dg-final { scan-assembler-times \"movq\" 5 } } */\n+/* { dg-final { scan-assembler-times \"movhps\" 0 } } */\ndiff --git a/gcc/testsuite/gcc.target/i386/vect-strided-4.c b/gcc/testsuite/gcc.target/i386/vect-strided-4.c\nindex 3fb9f07886e..37f6e72c0a9 100644\n--- a/gcc/testsuite/gcc.target/i386/vect-strided-4.c\n+++ b/gcc/testsuite/gcc.target/i386/vect-strided-4.c\n@@ -1,5 +1,5 @@\n /* { dg-do compile } */\n-/* { dg-options \"-O2 -msse4.2 -mno-avx -fno-tree-slp-vectorize\" } */\n+/* { dg-options \"-O2 -msse4.2 -mno-avx -fno-tree-slp-vectorize --param ix86-vect-compare-costs=0\" } */\n \n void foo (int * __restrict a, int * __restrict b, int *c, int s)\n {\ndiff --git a/gcc/testsuite/gcc.target/i386/vect-strided-4b.c b/gcc/testsuite/gcc.target/i386/vect-strided-4b.c\nnew file mode 100644\nindex 00000000000..3183a5c5385\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/i386/vect-strided-4b.c\n@@ -0,0 +1,19 @@\n+/* { dg-do compile { target { ! ia32 } } } */\n+/* { dg-options \"-O2 -msse4.2 -mno-avx -fno-tree-slp-vectorize --param ix86-vect-compare-costs=1\" } */\n+\n+void foo (int * __restrict a, int * __restrict b, int *c, int s)\n+{\n+ if (s >= 2)\n+ for (int i = 0; i < 1024; ++i)\n+ {\n+\ta[s*i+0] = c[4*i+0];\n+\ta[s*i+1] = c[4*i+1];\n+\tb[s*i+0] = c[4*i+2];\n+\tb[s*i+1] = c[4*i+3];\n+ }\n+}\n+\n+/* Vectorization factor two, two two-element stores using movq\n+ and two two-element stores to b via movq. One reg-reg copy with movq. */\n+/* { dg-final { scan-assembler-times \"movq\\[^\\r\\n\\]+\\\\\\(\" 4 } } */\n+/* { dg-final { scan-assembler-times \"pextrq\" 0 } } */\n","prefixes":["x86"]}