{"id":2229557,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2229557/?format=json","web_url":"http://patchwork.ozlabs.org/project/kvm-riscv/patch/20260428131359.34872-5-fangyu.yu@linux.alibaba.com/","project":{"id":70,"url":"http://patchwork.ozlabs.org/api/1.1/projects/70/?format=json","name":"Linux KVM RISC-V","link_name":"kvm-riscv","list_id":"kvm-riscv.lists.infradead.org","list_email":"kvm-riscv@lists.infradead.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260428131359.34872-5-fangyu.yu@linux.alibaba.com>","date":"2026-04-28T13:13:52","name":"[RFC,04/11] iommu/riscv: support GSCID and GVMA invalidation command","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"f0e3f86a96c145a71bd38f857436f89f5ddaeb18","submitter":{"id":91416,"url":"http://patchwork.ozlabs.org/api/1.1/people/91416/?format=json","name":null,"email":"fangyu.yu@linux.alibaba.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/kvm-riscv/patch/20260428131359.34872-5-fangyu.yu@linux.alibaba.com/mbox/","series":[{"id":501850,"url":"http://patchwork.ozlabs.org/api/1.1/series/501850/?format=json","web_url":"http://patchwork.ozlabs.org/project/kvm-riscv/list/?series=501850","date":"2026-04-28T13:13:48","name":"iommu/riscv: Add hardware dirty tracking for second-stage domains","version":1,"mbox":"http://patchwork.ozlabs.org/series/501850/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2229557/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2229557/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=lists.infradead.org header.i=@lists.infradead.org\n header.a=rsa-sha256 header.s=bombadil.20210309 header.b=f2TO6jPb;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n unprotected) header.d=linux.alibaba.com header.i=@linux.alibaba.com\n header.a=rsa-sha256 header.s=default header.b=at4kJr/g;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=none (no SPF record) smtp.mailfrom=lists.infradead.org\n (client-ip=2607:7c80:54:3::133; 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The original\n message has been attached to this so you can view it or label\n similar future email. If you have any questions, see\n the administrator of that system for details.\n Content preview: From: Zong Li This patch adds a ID\n Allocator\n for GSCID and a wrap for setting up GSCID in IOTLB invalidation command.\n Set up iohgatp to enable second stage table and flush stage-2 table if the\n GSCID is set.\n Content analysis details: (-17.6 points, 5.0 required)\n pts rule name description\n ---- ----------------------\n --------------------------------------------------\n -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no\n trust\n [115.124.30.111 listed in list.dnswl.org]\n -7.5 USER_IN_DEF_SPF_WL From: address is in the default SPF welcome-list\n 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record\n -0.0 SPF_PASS SPF: sender matches SPF record\n -7.5 USER_IN_DEF_DKIM_WL From: address is in the default DKIM welcome-list\n -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from\n envelope-from domain\n 0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n not necessarily valid\n -0.1 DKIM_VALID Message has at least one valid DKIM or DK\n signature\n -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n author's\n domain\n -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n [score: 0.0000]\n -0.5 ENV_AND_HDR_SPF_MATCH Env and Hdr From used in default SPF WL Match\n 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay\n lines","X-BeenThere":"kvm-riscv@lists.infradead.org","X-Mailman-Version":"2.1.34","Precedence":"list","List-Id":"","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"kvm-riscv\" ","Errors-To":"kvm-riscv-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org"},"content":"From: Zong Li \n\nThis patch adds a ID Allocator for GSCID and a wrap for setting up\nGSCID in IOTLB invalidation command.\n\nSet up iohgatp to enable second stage table and flush stage-2 table if\nthe GSCID is set.\n\nThe GSCID of domain should be freed when release domain. GSCID will be\nallocated for parent domain in nested IOMMU process.\n\nSigned-off-by: Zong Li \nSigned-off-by: Fangyu Yu \n---\n drivers/iommu/riscv/iommu-bits.h | 7 +++++++\n drivers/iommu/riscv/iommu.c | 32 ++++++++++++++++++++++++++------\n 2 files changed, 33 insertions(+), 6 deletions(-)","diff":"diff --git a/drivers/iommu/riscv/iommu-bits.h b/drivers/iommu/riscv/iommu-bits.h\nindex 29a0040b1c32..7c440926fa23 100644\n--- a/drivers/iommu/riscv/iommu-bits.h\n+++ b/drivers/iommu/riscv/iommu-bits.h\n@@ -716,6 +716,13 @@ static inline void riscv_iommu_cmd_inval_vma(struct riscv_iommu_command *cmd)\n \tcmd->dword1 = 0;\n }\n \n+static inline void riscv_iommu_cmd_inval_gvma(struct riscv_iommu_command *cmd)\n+{\n+\tcmd->dword0 = FIELD_PREP(RISCV_IOMMU_CMD_OPCODE, RISCV_IOMMU_CMD_IOTINVAL_OPCODE) |\n+\t\t FIELD_PREP(RISCV_IOMMU_CMD_FUNC, RISCV_IOMMU_CMD_IOTINVAL_FUNC_GVMA);\n+\tcmd->dword1 = 0;\n+}\n+\n static inline void riscv_iommu_cmd_inval_set_addr(struct riscv_iommu_command *cmd,\n \t\t\t\t\t\t u64 addr)\n {\ndiff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c\nindex 369c98b7e1e5..5dadf6d09139 100644\n--- a/drivers/iommu/riscv/iommu.c\n+++ b/drivers/iommu/riscv/iommu.c\n@@ -48,6 +48,10 @@\n static DEFINE_IDA(riscv_iommu_pscids);\n #define RISCV_IOMMU_MAX_PSCID\t\t(BIT(20) - 1)\n \n+/* IOMMU GSCID allocation namespace. */\n+static DEFINE_IDA(riscv_iommu_gscids);\n+#define RISCV_IOMMU_MAX_GSCID\t\t(BIT(16) - 1)\n+\n /* Device resource-managed allocations */\n struct riscv_iommu_devres {\n \tvoid *addr;\n@@ -819,6 +823,7 @@ struct riscv_iommu_domain {\n \tstruct list_head bonds;\n \tspinlock_t lock;\t\t/* protect bonds list updates. */\n \tint pscid;\n+\tint gscid;\n };\n PT_IOMMU_CHECK_DOMAIN(struct riscv_iommu_domain, riscvpt.iommu, domain);\n \n@@ -967,15 +972,20 @@ static void riscv_iommu_iotlb_inval(struct riscv_iommu_domain *domain,\n \n \t\t/*\n \t\t * IOTLB invalidation request can be safely omitted if already sent\n-\t\t * to the IOMMU for the same PSCID, and with domain->bonds list\n+\t\t * to the IOMMU for the same PSCID/GSCID, and with domain->bonds list\n \t\t * arranged based on the device's IOMMU, it's sufficient to check\n \t\t * last device the invalidation was sent to.\n \t\t */\n \t\tif (iommu == prev)\n \t\t\tcontinue;\n \n-\t\triscv_iommu_cmd_inval_vma(&cmd);\n-\t\triscv_iommu_cmd_inval_set_pscid(&cmd, domain->pscid);\n+\t\tif (domain->gscid) {\n+\t\t\triscv_iommu_cmd_inval_gvma(&cmd);\n+\t\t\triscv_iommu_cmd_inval_set_gscid(&cmd, domain->gscid);\n+\t\t} else {\n+\t\t\triscv_iommu_cmd_inval_vma(&cmd);\n+\t\t\triscv_iommu_cmd_inval_set_pscid(&cmd, domain->pscid);\n+\t\t}\n \t\tif (end - start < RISCV_IOMMU_IOTLB_INVAL_LIMIT - 1) {\n \t\t\tunsigned long iova = start;\n \n@@ -1120,6 +1130,7 @@ static void riscv_iommu_iodir_update(struct riscv_iommu_device *iommu,\n \n \t\tWRITE_ONCE(dc->fsc, new_dc->fsc);\n \t\tWRITE_ONCE(dc->ta, new_dc->ta & RISCV_IOMMU_PC_TA_PSCID);\n+\t\tWRITE_ONCE(dc->iohgatp, new_dc->iohgatp);\n \t\t/* Update device context, write TC.V as the last step. */\n \t\tdma_wmb();\n \t\tWRITE_ONCE(dc->tc, tc);\n@@ -1175,8 +1186,10 @@ static void riscv_iommu_free_paging_domain(struct iommu_domain *iommu_domain)\n \n \tWARN_ON(!list_empty(&domain->bonds));\n \n-\tif ((int)domain->pscid > 0)\n+\tif (domain->pscid > 0)\n \t\tida_free(&riscv_iommu_pscids, domain->pscid);\n+\tif (domain->gscid > 0)\n+\t\tida_free(&riscv_iommu_gscids, domain->gscid);\n \n \tpt_iommu_deinit(&domain->riscvpt.iommu);\n \tkfree(domain);\n@@ -1212,8 +1225,15 @@ static int riscv_iommu_attach_paging_domain(struct iommu_domain *iommu_domain,\n \tif (!riscv_iommu_pt_supported(iommu, pt_info.fsc_iosatp_mode))\n \t\treturn -ENODEV;\n \n-\tdc.fsc = FIELD_PREP(RISCV_IOMMU_PC_FSC_MODE, pt_info.fsc_iosatp_mode) |\n-\t FIELD_PREP(RISCV_IOMMU_PC_FSC_PPN, pt_info.ppn);\n+\tif (domain->gscid) {\n+\t\tdc.iohgatp = FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_MODE, pt_info.iohgatp_mode) |\n+\t\t\t FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_GSCID, domain->gscid) |\n+\t\t\t FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_PPN, pt_info.ppn);\n+\t} else {\n+\t\tdc.fsc = FIELD_PREP(RISCV_IOMMU_PC_FSC_MODE, pt_info.fsc_iosatp_mode) |\n+\t\t FIELD_PREP(RISCV_IOMMU_PC_FSC_PPN, pt_info.ppn);\n+\t}\n+\n \tdc.ta = FIELD_PREP(RISCV_IOMMU_PC_TA_PSCID, domain->pscid) |\n \t RISCV_IOMMU_PC_TA_V;\n \n","prefixes":["RFC","04/11"]}