{"id":2229554,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2229554/?format=json","web_url":"http://patchwork.ozlabs.org/project/kvm-riscv/patch/20260428131359.34872-2-fangyu.yu@linux.alibaba.com/","project":{"id":70,"url":"http://patchwork.ozlabs.org/api/1.1/projects/70/?format=json","name":"Linux KVM RISC-V","link_name":"kvm-riscv","list_id":"kvm-riscv.lists.infradead.org","list_email":"kvm-riscv@lists.infradead.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260428131359.34872-2-fangyu.yu@linux.alibaba.com>","date":"2026-04-28T13:13:49","name":"[RFC,01/11] iommupt: Add RISC-V Second-stage (iohgatp) page table support","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"f3c799523078f7af42ff9f0e52259799cc77d53a","submitter":{"id":91416,"url":"http://patchwork.ozlabs.org/api/1.1/people/91416/?format=json","name":null,"email":"fangyu.yu@linux.alibaba.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/kvm-riscv/patch/20260428131359.34872-2-fangyu.yu@linux.alibaba.com/mbox/","series":[{"id":501850,"url":"http://patchwork.ozlabs.org/api/1.1/series/501850/?format=json","web_url":"http://patchwork.ozlabs.org/project/kvm-riscv/list/?series=501850","date":"2026-04-28T13:13:48","name":"iommu/riscv: Add hardware dirty tracking for second-stage domains","version":1,"mbox":"http://patchwork.ozlabs.org/series/501850/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2229554/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2229554/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=lists.infradead.org header.i=@lists.infradead.org\n header.a=rsa-sha256 header.s=bombadil.20210309 header.b=RvYsktkZ;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n unprotected) header.d=linux.alibaba.com header.i=@linux.alibaba.com\n header.a=rsa-sha256 header.s=default header.b=GEu9WpZO;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=none (no SPF record) smtp.mailfrom=lists.infradead.org\n (client-ip=2607:7c80:54:3::133; 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The original\n message has been attached to this so you can view it or label\n similar future email. If you have any questions, see\n the administrator of that system for details.\n Content preview: From: Fangyu Yu Add support\n for Sv39x4/Sv48x4/Sv57x4 Second-stage page tables used by the RISC-V IOMMU\n iohgatp register. The x4 root page table is 16 KiB instead of the usual 4\n KiB, covering 2 extra GPA bits (hw_max_ [...]\n Content analysis details: (-17.6 points, 5.0 required)\n pts rule name description\n ---- ----------------------\n --------------------------------------------------\n -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no\n trust\n [115.124.30.97 listed in list.dnswl.org]\n -7.5 USER_IN_DEF_SPF_WL From: address is in the default SPF welcome-list\n 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record\n -0.0 SPF_PASS SPF: sender matches SPF record\n -7.5 USER_IN_DEF_DKIM_WL From: address is in the default DKIM welcome-list\n -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from\n envelope-from domain\n 0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n not necessarily valid\n -0.1 DKIM_VALID Message has at least one valid DKIM or DK\n signature\n -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n author's\n domain\n -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n [score: 0.0000]\n 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay\n lines\n -0.5 ENV_AND_HDR_SPF_MATCH Env and Hdr From used in default SPF WL Match","X-BeenThere":"kvm-riscv@lists.infradead.org","X-Mailman-Version":"2.1.34","Precedence":"list","List-Id":"","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"kvm-riscv\" ","Errors-To":"kvm-riscv-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org"},"content":"From: Fangyu Yu \n\nAdd support for Sv39x4/Sv48x4/Sv57x4 Second-stage page tables used by\nthe RISC-V IOMMU iohgatp register. The x4 root page table is 16 KiB\ninstead of the usual 4 KiB, covering 2 extra GPA bits (hw_max_vasz_lg2\n= 41/50/59).\n\nSigned-off-by: Fangyu Yu \n---\n drivers/iommu/generic_pt/fmt/riscv.h | 64 +++++++++++++++++++++++++---\n include/linux/generic_pt/common.h | 5 +++\n include/linux/generic_pt/iommu.h | 17 +++++++-\n 3 files changed, 80 insertions(+), 6 deletions(-)","diff":"diff --git a/drivers/iommu/generic_pt/fmt/riscv.h b/drivers/iommu/generic_pt/fmt/riscv.h\nindex a7fef6266a36..4fe645e60375 100644\n--- a/drivers/iommu/generic_pt/fmt/riscv.h\n+++ b/drivers/iommu/generic_pt/fmt/riscv.h\n@@ -37,7 +37,16 @@ enum {\n \tPT_MAX_OUTPUT_ADDRESS_LG2 = 34,\n \tPT_MAX_TOP_LEVEL = 1,\n #else\n-\tPT_MAX_VA_ADDRESS_LG2 = 57,\n+\t/*\n+\t * PT_MAX_VA_ADDRESS_LG2 is the upper bound accepted by the generic\n+\t * pt_iommu_init() range check. It must cover both first-stage and\n+\t * second-stage (G-stage) modes:\n+\t *\n+\t * First-stage (fsc/iosatp): Sv39=39, Sv48=48, Sv57=57\n+\t * Second-stage (iohgatp): Sv39x4=41, Sv48x4=50, Sv57x4=59\n+\t *\n+\t */\n+\tPT_MAX_VA_ADDRESS_LG2 = 59,\n \tPT_MAX_OUTPUT_ADDRESS_LG2 = 56,\n \tPT_MAX_TOP_LEVEL = 4,\n #endif\n@@ -124,6 +133,14 @@ riscvpt_entry_num_contig_lg2(const struct pt_state *pts)\n \n static inline unsigned int riscvpt_num_items_lg2(const struct pt_state *pts)\n {\n+\t/*\n+\t * Second-stage (iohgatp) root page tables have 4x the usual number of\n+\t * entries (2048 = 2^11 instead of 512 = 2^9) to cover the 2 extra GPA\n+\t * bits in Sv39x4/Sv48x4/Sv57x4. Only the root (top) level is\n+\t * enlarged; all other levels remain at the standard 9-bit index width.\n+\t */\n+\tif (to_riscvpt(pts)->second_stage && pts->level == pts->range->top_level)\n+\t\treturn PT_TABLEMEM_LG2SZ - ilog2(sizeof(u64)) + 2;\n \treturn PT_TABLEMEM_LG2SZ - ilog2(sizeof(u64));\n }\n #define pt_num_items_lg2 riscvpt_num_items_lg2\n@@ -254,6 +271,7 @@ riscvpt_iommu_fmt_init(struct pt_iommu_riscv_64 *iommu_table,\n \tstruct pt_riscv *table = &iommu_table->riscv_64pt;\n \n \tswitch (cfg->common.hw_max_vasz_lg2) {\n+\t/* First-stage (fsc/iosatp): Sv39 / Sv48 / Sv57 */\n \tcase 39:\n \t\tpt_top_set_level(&table->common, 2);\n \t\tbreak;\n@@ -263,6 +281,22 @@ riscvpt_iommu_fmt_init(struct pt_iommu_riscv_64 *iommu_table,\n \tcase 57:\n \t\tpt_top_set_level(&table->common, 4);\n \t\tbreak;\n+\t/*\n+\t * Second-stage (iohgatp): Sv39x4 / Sv48x4 / Sv57x4.\n+\t * The top level is the same as for the first-stage counterpart.\n+\t */\n+\tcase 41:\n+\t\tpt_top_set_level(&table->common, 2);\n+\t\ttable->second_stage = true;\n+\t\tbreak;\n+\tcase 50:\n+\t\tpt_top_set_level(&table->common, 3);\n+\t\ttable->second_stage = true;\n+\t\tbreak;\n+\tcase 59:\n+\t\tpt_top_set_level(&table->common, 4);\n+\t\ttable->second_stage = true;\n+\t\tbreak;\n \tdefault:\n \t\treturn -EINVAL;\n \t}\n@@ -283,10 +317,17 @@ riscvpt_iommu_fmt_hw_info(struct pt_iommu_riscv_64 *table,\n \tPT_WARN_ON(top_phys & ~PT_TOP_PHYS_MASK);\n \n \t/*\n-\t * See Table 3. Encodings of iosatp.MODE field\" for DC.tx.SXL = 0:\n-\t * 8 = Sv39 = top level 2\n-\t * 9 = Sv38 = top level 3\n-\t * 10 = Sv57 = top level 4\n+\t * Both first-stage (fsc/iosatp) and second-stage (iohgatp) share the\n+\t * same MODE numeric values for a given top level:\n+\t * top_level 2 -> MODE 8 (Sv39 / Sv39x4)\n+\t * top_level 3 -> MODE 9 (Sv48 / Sv48x4)\n+\t * top_level 4 -> MODE 10 (Sv57 / Sv57x4)\n+\t *\n+\t * The union members fsc_iosatp_mode and iohgatp_mode occupy the same\n+\t * byte; the caller selects the appropriate name based on domain type.\n+\t *\n+\t * See \"Table 3. Encodings of iosatp.MODE field\" (DC.tc.SXL = 0) and\n+\t * \"Table 2. Encoding of iohgatp.MODE field\" in the RISC-V IOMMU spec.\n \t */\n \tinfo->fsc_iosatp_mode = top_range->top_level + 6;\n }\n@@ -294,6 +335,7 @@ riscvpt_iommu_fmt_hw_info(struct pt_iommu_riscv_64 *table,\n \n #if defined(GENERIC_PT_KUNIT)\n static const struct pt_iommu_riscv_64_cfg riscv_64_kunit_fmt_cfgs[] = {\n+\t/* First-stage (fsc/iosatp): Sv39 / Sv48 / Sv57 */\n \t[0] = { .common.features = BIT(PT_FEAT_RISCV_SVNAPOT_64K),\n \t\t.common.hw_max_oasz_lg2 = 56,\n \t\t.common.hw_max_vasz_lg2 = 39 },\n@@ -303,6 +345,18 @@ static const struct pt_iommu_riscv_64_cfg riscv_64_kunit_fmt_cfgs[] = {\n \t[2] = { .common.features = BIT(PT_FEAT_RISCV_SVNAPOT_64K),\n \t\t.common.hw_max_oasz_lg2 = 56,\n \t\t.common.hw_max_vasz_lg2 = 57 },\n+\t/*\n+\t * Second-stage (iohgatp): Sv39x4 / Sv48x4 / Sv57x4.\n+\t */\n+\t[3] = { .common.features = BIT(PT_FEAT_RISCV_SVNAPOT_64K),\n+\t\t.common.hw_max_oasz_lg2 = 56,\n+\t\t.common.hw_max_vasz_lg2 = 41 },\n+\t[4] = { .common.features = 0,\n+\t\t.common.hw_max_oasz_lg2 = 56,\n+\t\t.common.hw_max_vasz_lg2 = 50 },\n+\t[5] = { .common.features = BIT(PT_FEAT_RISCV_SVNAPOT_64K),\n+\t\t.common.hw_max_oasz_lg2 = 56,\n+\t\t.common.hw_max_vasz_lg2 = 59 },\n };\n #define kunit_fmt_cfgs riscv_64_kunit_fmt_cfgs\n enum {\ndiff --git a/include/linux/generic_pt/common.h b/include/linux/generic_pt/common.h\nindex fc5d0b5edadc..e82dff33ece8 100644\n--- a/include/linux/generic_pt/common.h\n+++ b/include/linux/generic_pt/common.h\n@@ -181,6 +181,11 @@ struct pt_riscv_32 {\n \n struct pt_riscv_64 {\n \tstruct pt_common common;\n+\t/*\n+\t * True when this table is used for second-stage / iohgatp\n+\t * address translation.\n+\t */\n+\tbool second_stage;\n };\n \n enum {\ndiff --git a/include/linux/generic_pt/iommu.h b/include/linux/generic_pt/iommu.h\nindex dd0edd02a48a..f27d229ff318 100644\n--- a/include/linux/generic_pt/iommu.h\n+++ b/include/linux/generic_pt/iommu.h\n@@ -328,7 +328,22 @@ struct pt_iommu_riscv_64_cfg {\n \n struct pt_iommu_riscv_64_hw_info {\n \tu64 ppn;\n-\tu8 fsc_iosatp_mode;\n+\tunion {\n+\t\t/*\n+\t\t * First-stage (fsc/iosatp) MODE encoding:\n+\t\t * 8 = Sv39, 9 = Sv48, 10 = Sv57\n+\t\t * Used to program DC.fsc.iosatp.MODE.\n+\t\t */\n+\t\tu8 fsc_iosatp_mode;\n+\t\t/*\n+\t\t * Second-stage (iohgatp) MODE encoding:\n+\t\t * 8 = Sv39x4, 9 = Sv48x4, 10 = Sv57x4\n+\t\t * Used to program DC.iohgatp.MODE.\n+\t\t * The numeric values are identical to fsc_iosatp_mode;\n+\t\t * the caller selects the interpretation based on domain type.\n+\t\t */\n+\t\tu8 iohgatp_mode;\n+\t};\n };\n \n IOMMU_FORMAT(riscv_64, riscv_64pt);\n","prefixes":["RFC","01/11"]}