{"id":2229513,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2229513/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/patch/01082f57-24bb-4846-be23-a2e357cbc9b5@linux.ibm.com/","project":{"id":17,"url":"http://patchwork.ozlabs.org/api/1.1/projects/17/?format=json","name":"GNU Compiler Collection","link_name":"gcc","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<01082f57-24bb-4846-be23-a2e357cbc9b5@linux.ibm.com>","date":"2026-04-28T11:04:23","name":"rs6000: Update mma_assemble_acc for DMF","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"a42c08d9018d869852fd81c9e0b43f293a22bb42","submitter":{"id":88474,"url":"http://patchwork.ozlabs.org/api/1.1/people/88474/?format=json","name":"Surya Kumari Jangala","email":"jskumari@linux.ibm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/gcc/patch/01082f57-24bb-4846-be23-a2e357cbc9b5@linux.ibm.com/mbox/","series":[{"id":501826,"url":"http://patchwork.ozlabs.org/api/1.1/series/501826/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/list/?series=501826","date":"2026-04-28T11:04:23","name":"rs6000: Update mma_assemble_acc for DMF","version":1,"mbox":"http://patchwork.ozlabs.org/series/501826/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2229513/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2229513/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256\n header.s=pp1 header.b=FzOKGJ0p;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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charset=UTF-8","Content-Transfer-Encoding":"7bit","X-TM-AS-GCONF":"00","X-Proofpoint-GUID":"3WBNIY364BT7HlrYXv9Mis6GqQWplins","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNDI4MDA5NyBTYWx0ZWRfX7vZNB6akFRCd\n IrYr4BxJKz/h06+Io9fdxgrmVmNeXNkcdLbvnMBvvd87f1HlIIBLvnZPw3Ce0WxON1+v0sQlI5K\n v0SYLtQS/xdRZxjVkELwMc22jp228AFSF+lJtMCOa0hLsHvCuDNkSvUQPgSV0d4UkVIE4TK3JMQ\n 71Kk+UrF1F0+G/cgNyPdKinCKHPcjjrGoRS7v9zf+grr0YEx2uswUvp3KKKVbe66Z/uzV55fYxy\n EPGuYlUinJRoM7KoH76hFrfERQxRgaFzgSb13L/aY3UQAC39eLsdSg+KXS8ti6Kr8NEdtrTf3xJ\n 1Jog+nBLTI0Oyb5ydT45vc1B4c7kGMvZmSfHNOk7kHslBq0mHaTBrTo48lQp5HfIfzMCzN0UJTC\n CMe+ZNLSFobgmXSUOcOSo63mjvRcPZdJQ/ee232K2fs5fRK+6q3kWAjEZNYZt7v1Td7D+LNuB/7\n 9OMrMqyyNZKaB1P43lA==","X-Authority-Analysis":"v=2.4 cv=Kc7idwYD c=1 sm=1 tr=0 ts=69f0943e cx=c_pps\n a=bLidbwmWQ0KltjZqbj+ezA==:117 a=bLidbwmWQ0KltjZqbj+ezA==:17\n a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=RnoormkPH1_aCDwRdu11:22 a=uAbxVGIbfxUO_5tXvNgY:22 a=mDV3o1hIAAAA:8\n a=VnNF1IyMAAAA:8 a=aIgOinGhM5ZEc-C-JXUA:9 a=QEXdDO2ut3YA:10","X-Proofpoint-ORIG-GUID":"3WBNIY364BT7HlrYXv9Mis6GqQWplins","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-28_02,2026-04-21_02,2025-10-01_01","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n clxscore=1015 phishscore=0 bulkscore=0 adultscore=0 spamscore=0\n malwarescore=0 impostorscore=0 priorityscore=1501 lowpriorityscore=0\n suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc=\n route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000\n definitions=main-2604280097","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org"},"content":"This patch depends on the following patches:\n1. -mcpu=future: https://gcc.gnu.org/pipermail/gcc-patches/2025-December/703739.html\n2. Support for Dense Math Registers: https://gcc.gnu.org/pipermail/gcc-patches/2026-April/713352.html\n\nThis patch adds a new dm_insert512 instruction pattern for moving data\nfrom VSX registers to Dense Math Registers via two insert 512-bit\ninstructions. Also mma_assemble_acc expand is updated to use DMF\nspecific code path when TARGET_DENSE_MATH is enabled.\nNote that the Dense Math Facility may or may not be supported in a\nfuture processor.\n\n2026-04-28 Peter Bergner \n\ngcc:\n\t* config/rs6000/mma.md (dm_insert512): New define_insn.\n\t(mma_assemble_acc): Update to support Dense Math Facility with\n\tconditional code path for TARGET_DENSE_MATH.\n---\n gcc/config/rs6000/mma.md | 33 ++++++++++++++++++++++++++++-----\n 1 file changed, 28 insertions(+), 5 deletions(-)","diff":"diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md\nindex 5253e2c34a8..e4e613c55bf 100644\n--- a/gcc/config/rs6000/mma.md\n+++ b/gcc/config/rs6000/mma.md\n@@ -427,6 +427,18 @@ (define_expand \"vsx_disassemble_pair\"\n DONE;\n })\n \n+;; Move from VSX registers to DMR registers via two insert 512 bit\n+;; instructions.\n+(define_insn \"dm_insert512\"\n+ [(set (match_operand:XO 0 \"dense_math_operand\" \"=wD\")\n+ (unspec:XO [(match_operand:OO 1 \"vsx_register_operand\" \"wa\")\n+\t\t (match_operand:OO 2 \"vsx_register_operand\" \"wa\")\n+\t\t (match_operand 3 \"const_0_to_1_operand\")]\n+\t\t UNSPEC_DM_INSERT512_UPPER))]\n+ \"TARGET_DENSE_MATH\"\n+ \"dmxxinstdmr512 %0,%x1,%x2,%3\"\n+ [(set_attr \"type\" \"mma\")])\n+\n (define_expand \"mma_assemble_acc\"\n [(match_operand:XO 0 \"fpr_reg_operand\")\n (match_operand:V16QI 1 \"mma_assemble_input_operand\")\n@@ -435,11 +447,22 @@ (define_expand \"mma_assemble_acc\"\n (match_operand:V16QI 4 \"mma_assemble_input_operand\")]\n \"TARGET_MMA\"\n {\n- rtx src = gen_rtx_UNSPEC_VOLATILE (XOmode,\n-\t\t\t \t gen_rtvec (4, operands[1], operands[2],\n-\t\t\t\t \t\toperands[3], operands[4]),\n-\t\t\t \t UNSPECV_MMA_ASSEMBLE);\n- emit_move_insn (operands[0], src);\n+ if (TARGET_DENSE_MATH)\n+ {\n+ rtx vp0 = gen_reg_rtx (OOmode);\n+ rtx vp1 = gen_reg_rtx (OOmode);\n+ emit_insn (gen_vsx_assemble_pair (vp0, operands[1], operands[2]));\n+ emit_insn (gen_vsx_assemble_pair (vp1, operands[3], operands[4]));\n+ emit_insn (gen_dm_insert512 (operands[0], vp0, vp1, const0_rtx));\n+ }\n+ else\n+ {\n+ rtx src = gen_rtx_UNSPEC_VOLATILE (XOmode,\n+\t\t\t \t \t gen_rtvec (4, operands[1], operands[2],\n+\t\t\t\t \t\t operands[3], operands[4]),\n+\t\t\t \t \t UNSPECV_MMA_ASSEMBLE);\n+ emit_move_insn (operands[0], src);\n+ }\n DONE;\n })\n \n","prefixes":[]}