{"id":2229357,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2229357/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20260428070017.16807-3-chen.huei.lok@altera.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.1/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260428070017.16807-3-chen.huei.lok@altera.com>","date":"2026-04-28T07:00:11","name":"[v2,2/8] arm: dts: socfpga: n5x: enable DT register settings and update GMAC nodes","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"a3a504a515e957805534ae3043b2c40cb9a3bcd6","submitter":{"id":92584,"url":"http://patchwork.ozlabs.org/api/1.1/people/92584/?format=json","name":"Chen Huei Lok","email":"chen.huei.lok@altera.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20260428070017.16807-3-chen.huei.lok@altera.com/mbox/","series":[{"id":501777,"url":"http://patchwork.ozlabs.org/api/1.1/series/501777/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=501777","date":"2026-04-28T07:00:09","name":"socfpga: n5x: Update Boot Support for N5X","version":2,"mbox":"http://patchwork.ozlabs.org/series/501777/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2229357/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2229357/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=altera.com header.i=@altera.com header.a=rsa-sha256\n header.s=selector2 header.b=tF2m119t;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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The QSPI controller clock is obtained\nvia cm_get_qspi_controller_clk_hz(), so the device tree clock\nreference is unnecessary.\n\nAdditionally, include socfpga_soc64_u-boot.dtsi and rename the\nsoc node to soc@0 in socfpga_n5x-u-boot.dtsi to align with\nthe common SoCFPGA DT layout.\n\nSigned-off-by: Tien Fong Chee \nSigned-off-by: Alif Zakuan Yuslaimi \nSigned-off-by: Chen Huei Lok \n---\n arch/arm/dts/socfpga_n5x-u-boot.dtsi | 38 +++++++++++++++++++++-\n arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi | 5 +++\n 2 files changed, 42 insertions(+), 1 deletion(-)","diff":"diff --git a/arch/arm/dts/socfpga_n5x-u-boot.dtsi b/arch/arm/dts/socfpga_n5x-u-boot.dtsi\nindex e27a64651e1..dbfd2abfd59 100644\n--- a/arch/arm/dts/socfpga_n5x-u-boot.dtsi\n+++ b/arch/arm/dts/socfpga_n5x-u-boot.dtsi\n@@ -5,6 +5,7 @@\n * Copyright (C) 2020-2021 Intel Corporation \n */\n \n+#include \"socfpga_soc64_u-boot.dtsi\"\n #include \"socfpga_soc64_fit-u-boot.dtsi\"\n #include \n \n@@ -15,7 +16,7 @@\n \t\tbootph-all;\n \t};\n \n-\tsoc {\n+\tsoc@0 {\n \t\tbootph-all;\n \n \t\tccu: cache-controller@f7000000 {\n@@ -46,17 +47,29 @@\n };\n \n &gmac0 {\n+\tcompatible = \"altr,socfpga-stmmac\", \"snps,dwmac-3.74a\", \"snps,dwmac\";\n+\treset-names = \"stmmaceth\", \"stmmaceth-ocp\";\n \tclocks = <&clkmgr N5X_EMAC0_CLK>;\n+\tclock-names = \"stmmaceth\";\n+\tstatus = \"disabled\";\n };\n \n &gmac1 {\n+\tcompatible = \"altr,socfpga-stmmac\", \"snps,dwmac-3.74a\", \"snps,dwmac\";\n+\treset-names = \"stmmaceth\", \"stmmaceth-ocp\";\n \taltr,sysmgr-syscon = <&sysmgr 0x48 0>;\n \tclocks = <&clkmgr N5X_EMAC1_CLK>;\n+\tclock-names = \"stmmaceth\";\n+\tstatus = \"disabled\";\n };\n \n &gmac2 {\n+\tcompatible = \"altr,socfpga-stmmac\", \"snps,dwmac-3.74a\", \"snps,dwmac\";\n+\treset-names = \"stmmaceth\", \"stmmaceth-ocp\";\n \taltr,sysmgr-syscon = <&sysmgr 0x4c 0>;\n \tclocks = <&clkmgr N5X_EMAC2_CLK>;\n+\tclock-names = \"stmmaceth\";\n+\tstatus = \"disabled\";\n };\n \n &i2c0 {\n@@ -132,6 +145,29 @@\n \tclocks = <&clkmgr N5X_L4_MAIN_CLK>;\n };\n \n+&socfpga_l3interconnect_firewall {\n+\tocram-firewall@f7100200 {\n+\t\treg = <0xf7100200 0x00000014>;\n+\t\tintel,offset-settings =\n+\t\t\t/* Disable ocram security at CCU for non secure access */\n+\t\t\t<0x00000004 0x8000ffff 0xe007ffff>,\n+\t\t\t<0x00000008 0x8000ffff 0xe007ffff>,\n+\t\t\t<0x0000000c 0x8000ffff 0xe007ffff>,\n+\t\t\t<0x00000010 0x8000ffff 0xe007ffff>;\n+\t\tbootph-all;\n+\t};\n+\n+\tmpfe-firewall@f8020000 {\n+\t\treg = <0xf8020000 0x0000001c>;\n+\t\tintel,offset-settings =\n+\t\t\t/* Disable MPFE firewall for SMMU */\n+\t\t\t<0x00000000 0x00010101 0x00010101>,\n+\t\t\t/* Disable MPFE firewall for HMC adapter */\n+\t\t\t<0x00000004 0x00000001 0x00010101>;\n+\t\tbootph-all;\n+\t};\n+};\n+\n &sysmgr {\n \tcompatible = \"altr,sys-mgr\", \"syscon\";\n \tbootph-all;\ndiff --git a/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi\nindex 840537c9d0b..1f7e31bcae3 100644\n--- a/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi\n+++ b/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi\n@@ -44,6 +44,10 @@\n \tbootph-all;\n };\n \n+&gmac0 {\n+\tstatus = \"okay\";\n+};\n+\n &i2c1 {\n \tstatus = \"okay\";\n };\n@@ -55,6 +59,7 @@\n };\n \n &qspi {\n+\t/delete-property/ clocks;\n \tstatus = \"okay\";\n };\n \n","prefixes":["v2","2/8"]}