{"id":2229337,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2229337/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/patch/20260428072746.3641227-3-pan2.li@intel.com/","project":{"id":17,"url":"http://patchwork.ozlabs.org/api/1.1/projects/17/?format=json","name":"GNU Compiler Collection","link_name":"gcc","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260428072746.3641227-3-pan2.li@intel.com>","date":"2026-04-28T07:26:27","name":"[v1,2/2] RISC-V: Add test for vec_duplicate + vmsgtu.vv combine with GR2VR cost 0, 1 and 15","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"c97fe06e98b70f64ea766b0d0f2539b6acef5b37","submitter":{"id":86320,"url":"http://patchwork.ozlabs.org/api/1.1/people/86320/?format=json","name":"Li, Pan2","email":"pan2.li@intel.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/gcc/patch/20260428072746.3641227-3-pan2.li@intel.com/mbox/","series":[{"id":501773,"url":"http://patchwork.ozlabs.org/api/1.1/series/501773/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/list/?series=501773","date":"2026-04-28T07:26:25","name":"RISC-V: Combine vec_duplicate + vmsgtu.vv to vmsgtu.vx on GR2VR cost","version":1,"mbox":"http://patchwork.ozlabs.org/series/501773/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2229337/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2229337/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=glxTauBZ;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; helo=vm01.sourceware.org;\n envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org;\n receiver=patchwork.ozlabs.org)","sourceware.org;\n\tdkim=pass (2048-bit key,\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=glxTauBZ","sourceware.org;\n dmarc=pass (p=none dis=none) header.from=intel.com","sourceware.org; spf=pass smtp.mailfrom=intel.com","server2.sourceware.org;\n arc=none smtp.remote-ip=198.175.65.13"],"Received":["from vm01.sourceware.org (vm01.sourceware.org\n [IPv6:2620:52:6:3111::32])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g4XG51WFqz1yHv\n\tfor ; Tue, 28 Apr 2026 17:32:45 +1000 (AEST)","from vm01.sourceware.org (localhost [127.0.0.1])\n\tby sourceware.org (Postfix) with ESMTP id 670F54BA7999\n\tfor ; Tue, 28 Apr 2026 07:32:43 +0000 (GMT)","from mgamail.intel.com (mgamail.intel.com [198.175.65.13])\n by sourceware.org (Postfix) with ESMTPS id CEE6A4B99F53\n for ; Tue, 28 Apr 2026 07:32:03 +0000 (GMT)","from orviesa008.jf.intel.com ([10.64.159.148])\n by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 28 Apr 2026 00:31:50 -0700","from panli.sh.intel.com ([10.239.159.63])\n by orviesa008.jf.intel.com with ESMTP; 28 Apr 2026 00:31:47 -0700"],"DKIM-Filter":["OpenDKIM Filter v2.11.0 sourceware.org 670F54BA7999","OpenDKIM Filter v2.11.0 sourceware.org CEE6A4B99F53"],"DMARC-Filter":"OpenDMARC Filter v1.4.2 sourceware.org CEE6A4B99F53","ARC-Filter":"OpenARC Filter v1.0.0 sourceware.org CEE6A4B99F53","ARC-Seal":"i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1777361524; cv=none;\n b=afq6ryqRcbBWOZ6ZPmES1F1uGVo6SfrrCGNzqj8ge/XK5LlpfgI4t5CJW5V/7PnTah0AXmulfM2izx6a8YlPnjMMYrJ0jE2gE1ZzploIDAOcus8EmredmEsXiPeGUC5s2bNtoEwRp6vf10zYokQPqGnBjPfdRvqGzk4LVR2cU28=","ARC-Message-Signature":"i=1; a=rsa-sha256; d=sourceware.org; s=key;\n t=1777361524; c=relaxed/simple;\n bh=j8BeX/j8EN8s/T3WEuZ5fZFt+J2XWVxflm5xhFgLkuc=;\n h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version;\n b=hacZnFKtPO9+gHKV0gAtDQnMwd1v5faLNnb8IdcPiFYw4+0X7SPWf3a2VD25OkGx6IN/YEFZ9vDYUlDvAZJnl+h1e4AbLz2mFPQ2kSIf+PBC+bLkWUEwhlC9wUYO0ku8P7XGzOjXTnfctVUwzXFkYtNR1iXt0GixosrTCd7xNcA=","ARC-Authentication-Results":"i=1; server2.sourceware.org","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1777361524; x=1808897524;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=j8BeX/j8EN8s/T3WEuZ5fZFt+J2XWVxflm5xhFgLkuc=;\n b=glxTauBZW2HjY5cwIAPBNs08p276S/wsiQS6N33jEponcBLiiolW/Ppb\n bVjkiFZISzhQBjDkwIh/zuwxPnJJsr8zABBsn6mcazmLkzc2HoebjF1Kt\n qBRN2KuHPEiqEI1+Qew0MmxocG9g2Jq3bOAb4xOK319xXYaDpcpawLFqV\n mKRugBZcf4L6Nh93h95l2GlEGBEVxJnS/fE+tDrdHS5H/81gp+MdehLhi\n 7QwBnHeFjnniWqC0X5yre+7bHXo7g7HOLeNThY5wD8UnNyfAEgmTnf28N\n m/+2ngnl913vTewmuEiC9sRGIDwho4C+ez4b3kPboEqYZtcyvrzn63a1e A==;","X-CSE-ConnectionGUID":["NF2VfT24S1u+nG8xguP7FA==","nYd4l08lREyxfgj6QPGZtA=="],"X-CSE-MsgGUID":["sXWFO0aTR/yI9i/Ci1VVpQ==","J3ce1ctPRne2gf+Zw1Yk8w=="],"X-IronPort-AV":["E=McAfee;i=\"6800,10657,11769\"; a=\"89350079\"","E=Sophos;i=\"6.23,203,1770624000\"; d=\"scan'208\";a=\"89350079\"","E=Sophos;i=\"6.23,203,1770624000\"; d=\"scan'208\";a=\"233746064\""],"X-ExtLoop1":"1","From":"pan2.li@intel.com","To":"gcc-patches@gcc.gnu.org","Cc":"juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com,\n rdapp.gcc@gmail.com, ken.chen@intel.com, hongtao.liu@intel.com,\n Pan Li ","Subject":"[PATCH v1 2/2] RISC-V: Add test for vec_duplicate + vmsgtu.vv combine\n with GR2VR cost 0, 1 and 15","Date":"Tue, 28 Apr 2026 15:26:27 +0800","Message-ID":"<20260428072746.3641227-3-pan2.li@intel.com>","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"<20260428072746.3641227-1-pan2.li@intel.com>","References":"<20260428072746.3641227-1-pan2.li@intel.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org"},"content":"From: Pan Li \n\nAdd asm dump check and run test for vec_duplicate + vmsgtu.vv\ncombine to vmsgtu.vx, with the GR2VR cost is 0, 2 and 15.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Add asm check\n\tfor vmsgtu.vx.\n\t* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h: Add test\n\thelper macro.\n\t* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h: Add test\n\tdata for run test.\n\t* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgtu-run-1-u16.c: New test.\n\t* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgtu-run-1-u32.c: New test.\n\t* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgtu-run-1-u64.c: New test.\n\t* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgtu-run-1-u8.c: New test.\n\nSigned-off-by: Pan Li \n---\n .../riscv/rvv/autovec/vx_vf/vx-1-u16.c | 1 +\n .../riscv/rvv/autovec/vx_vf/vx-1-u32.c | 1 +\n .../riscv/rvv/autovec/vx_vf/vx-1-u64.c | 1 +\n .../riscv/rvv/autovec/vx_vf/vx-1-u8.c | 1 +\n .../riscv/rvv/autovec/vx_vf/vx-2-u16.c | 1 +\n .../riscv/rvv/autovec/vx_vf/vx-2-u32.c | 1 +\n .../riscv/rvv/autovec/vx_vf/vx-2-u64.c | 1 +\n .../riscv/rvv/autovec/vx_vf/vx-2-u8.c | 1 +\n .../riscv/rvv/autovec/vx_vf/vx-3-u16.c | 1 +\n .../riscv/rvv/autovec/vx_vf/vx-3-u32.c | 1 +\n .../riscv/rvv/autovec/vx_vf/vx-3-u64.c | 1 +\n .../riscv/rvv/autovec/vx_vf/vx-3-u8.c | 1 +\n .../riscv/rvv/autovec/vx_vf/vx_binary.h | 1 +\n .../riscv/rvv/autovec/vx_vf/vx_binary_data.h | 136 ++++++++++++++++++\n .../rvv/autovec/vx_vf/vx_vmsgtu-run-1-u16.c | 15 ++\n .../rvv/autovec/vx_vf/vx_vmsgtu-run-1-u32.c | 15 ++\n .../rvv/autovec/vx_vf/vx_vmsgtu-run-1-u64.c | 15 ++\n .../rvv/autovec/vx_vf/vx_vmsgtu-run-1-u8.c | 15 ++\n 18 files changed, 209 insertions(+)\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgtu-run-1-u16.c\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgtu-run-1-u32.c\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgtu-run-1-u64.c\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgtu-run-1-u8.c","diff":"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c\nindex 7e3ad1f70fc..2cae55389b3 100644\n--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c\n@@ -39,3 +39,4 @@ TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)\n /* { dg-final { scan-assembler-times {vmseq.vx} 1 } } */\n /* { dg-final { scan-assembler-times {vmsne.vx} 1 } } */\n /* { dg-final { scan-assembler-times {vmsltu.vx} 1 } } */\n+/* { dg-final { scan-assembler-times {vmsgtu.vx} 1 } } */\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c\nindex 36d8a6434ca..946126e1fb9 100644\n--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c\n@@ -40,3 +40,4 @@ TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)\n /* { dg-final { scan-assembler-times {vmsne.vx} 1 } } */\n /* { dg-final { scan-assembler-times {vmsltu.vx} 1 } } */\n /* { dg-final { scan-assembler-times {vmsleu.vx} 1 } } */\n+/* { dg-final { scan-assembler-times {vmsgtu.vx} 1 } } */\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c\nindex aab16016dd4..63f1fae266f 100644\n--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c\n@@ -43,3 +43,4 @@ TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)\n /* { dg-final { scan-assembler-times {vmsne.vx} 1 } } */\n /* { dg-final { scan-assembler-times {vmsltu.vx} 1 } } */\n /* { dg-final { scan-assembler-times {vmsleu.vx} 1 } } */\n+/* { dg-final { scan-assembler-times {vmsgtu.vx} 1 } } */\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c\nindex dcea470dc5f..add5a7255cc 100644\n--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c\n@@ -30,3 +30,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T)\n /* { dg-final { scan-assembler-times {vmsne.vx} 1 } } */\n /* { dg-final { scan-assembler-times {vmsltu.vx} 1 } } */\n /* { dg-final { scan-assembler-times {vmsleu.vx} 1 } } */\n+/* { dg-final { scan-assembler-times {vmsgtu.vx} 1 } } */\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c\nindex a3162b1626a..735b9c094d7 100644\n--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c\n@@ -40,3 +40,4 @@ TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)\n /* { dg-final { scan-assembler-not {vmsne.vx} } } */\n /* { dg-final { scan-assembler-not {vmsltu.vx} } } */\n /* { dg-final { scan-assembler-not {vmsleu.vx} } } */\n+/* { dg-final { scan-assembler-not {vmsgtu.vx} } } */\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c\nindex e90cdf652af..576d7c18845 100644\n--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c\n@@ -40,3 +40,4 @@ TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)\n /* { dg-final { scan-assembler-not {vmsne.vx} } } */\n /* { dg-final { scan-assembler-not {vmsltu.vx} } } */\n /* { dg-final { scan-assembler-not {vmsleu.vx} } } */\n+/* { dg-final { scan-assembler-not {vmsgtu.vx} } } */\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c\nindex 79a2b3fb743..ce14846b987 100644\n--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c\n@@ -40,3 +40,4 @@ TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)\n /* { dg-final { scan-assembler-not {vmsne.vx} } } */\n /* { dg-final { scan-assembler-not {vmsltu.vx} } } */\n /* { dg-final { scan-assembler-not {vmsleu.vx} } } */\n+/* { dg-final { scan-assembler-not {vmsgtu.vx} } } */\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c\nindex 989e1013890..8b5718feb4d 100644\n--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c\n@@ -30,3 +30,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T)\n /* { dg-final { scan-assembler-not {vmsne.vx} } } */\n /* { dg-final { scan-assembler-not {vmsltu.vx} } } */\n /* { dg-final { scan-assembler-not {vmsleu.vx} } } */\n+/* { dg-final { scan-assembler-not {vmsgtu.vx} } } */\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c\nindex ae2216a75fe..e2d04a5df78 100644\n--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c\n@@ -40,3 +40,4 @@ TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)\n /* { dg-final { scan-assembler-not {vmsne.vx} } } */\n /* { dg-final { scan-assembler-not {vmsltu.vx} } } */\n /* { dg-final { scan-assembler-not {vmsleu.vx} } } */\n+/* { dg-final { scan-assembler-not {vmsgtu.vx} } } */\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c\nindex 348f33e9a79..46f5a05b1b2 100644\n--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c\n@@ -40,3 +40,4 @@ TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)\n /* { dg-final { scan-assembler-not {vmsne.vx} } } */\n /* { dg-final { scan-assembler-not {vmsltu.vx} } } */\n /* { dg-final { scan-assembler-not {vmsleu.vx} } } */\n+/* { dg-final { scan-assembler-not {vmsgtu.vx} } } */\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c\nindex 85f9085ca62..0d73725f491 100644\n--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c\n@@ -40,3 +40,4 @@ TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)\n /* { dg-final { scan-assembler-not {vmsne.vx} } } */\n /* { dg-final { scan-assembler-not {vmsltu.vx} } } */\n /* { dg-final { scan-assembler-not {vmsleu.vx} } } */\n+/* { dg-final { scan-assembler-not {vmsgtu.vx} } } */\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c\nindex 82e5389f7d3..a98cc802c55 100644\n--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c\n@@ -30,3 +30,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T)\n /* { dg-final { scan-assembler-not {vmsne.vx} } } */\n /* { dg-final { scan-assembler-not {vmsltu.vx} } } */\n /* { dg-final { scan-assembler-not {vmsleu.vx} } } */\n+/* { dg-final { scan-assembler-not {vmsgtu.vx} } } */\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h\nindex 149787ae476..ff6b7f6542d 100644\n--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h\n@@ -428,6 +428,7 @@ DEF_AVG_CEIL(int32_t, int64_t)\n DEF_VX_BINARY_CASE_0_WRAP(T, !=, ne) \\\n DEF_VX_BINARY_CASE_0_WRAP(T, <, ltu) \\\n DEF_VX_BINARY_CASE_0_WRAP(T, <=, leu) \\\n+ DEF_VX_BINARY_CASE_0_WRAP(T, >, gtu) \\\n DEF_VX_BINARY_CASE_2_WRAP(T, MAX_FUNC_0_WARP(T), max) \\\n DEF_VX_BINARY_CASE_2_WRAP(T, MAX_FUNC_1_WARP(T), max) \\\n DEF_VX_BINARY_CASE_2_WRAP(T, MIN_FUNC_0_WARP(T), min) \\\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h\nindex 8e66c22a235..952c8b49ecd 100644\n--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h\n@@ -6974,4 +6974,140 @@ int64_t TEST_BINARY_DATA(int64_t, le)[][3][N] =\n },\n };\n \n+uint8_t TEST_BINARY_DATA(uint8_t, gtu)[][3][N] =\n+{\n+ {\n+ { 127 },\n+ {\n+ 0, 0, 0, 0,\n+ 1, 1, 1, 1,\n+ 127, 127, 127, 127,\n+ 128, 128, 128, 128,\n+ },\n+ {\n+ 0, 0, 0, 0,\n+ 0, 0, 0, 0,\n+ 0, 0, 0, 0,\n+ 1, 1, 1, 1,\n+ },\n+ },\n+ {\n+ { 255 },\n+ {\n+ 0, 0, 0, 0,\n+ 1, 1, 1, 1,\n+ 2, 2, 2, 2,\n+ 255, 255, 255, 255,\n+ },\n+ {\n+ 0, 0, 0, 0,\n+ 0, 0, 0, 0,\n+ 0, 0, 0, 0,\n+ 0, 0, 0, 0,\n+ },\n+ },\n+};\n+\n+uint16_t TEST_BINARY_DATA(uint16_t, gtu)[][3][N] =\n+{\n+ {\n+ { 32767 },\n+ {\n+ 0, 0, 0, 0,\n+ 1, 1, 1, 1,\n+ 32767, 32767, 32767, 32767,\n+ 32768, 32768, 32768, 32768,\n+ },\n+ {\n+ 0, 0, 0, 0,\n+ 0, 0, 0, 0,\n+ 0, 0, 0, 0,\n+ 1, 1, 1, 1,\n+ },\n+ },\n+ {\n+ { 65535 },\n+ {\n+ 0, 0, 0, 0,\n+ 1, 1, 1, 1,\n+ 2, 2, 2, 2,\n+ 65535, 65535, 65535, 65535,\n+ },\n+ {\n+ 0, 0, 0, 0,\n+ 0, 0, 0, 0,\n+ 0, 0, 0, 0,\n+ 0, 0, 0, 0,\n+ },\n+ },\n+};\n+\n+uint32_t TEST_BINARY_DATA(uint32_t, gtu)[][3][N] =\n+{\n+ {\n+ { 2147483647 },\n+ {\n+ 0, 0, 0, 0,\n+ 1, 1, 1, 1,\n+ 2147483647, 2147483647, 2147483647, 2147483647,\n+ 2147483648, 2147483648, 2147483648, 2147483648,\n+ },\n+ {\n+ 0, 0, 0, 0,\n+ 0, 0, 0, 0,\n+ 0, 0, 0, 0,\n+ 1, 1, 1, 1,\n+ },\n+ },\n+ {\n+ { 4294967295 },\n+ {\n+ 0, 0, 0, 0,\n+ 1, 1, 1, 1,\n+ 2, 2, 2, 2,\n+ 4294967295, 4294967295, 4294967295, 4294967295,\n+ },\n+ {\n+ 0, 0, 0, 0,\n+ 0, 0, 0, 0,\n+ 0, 0, 0, 0,\n+ 0, 0, 0, 0,\n+ },\n+ },\n+};\n+\n+uint64_t TEST_BINARY_DATA(uint64_t, gtu)[][3][N] =\n+{\n+ {\n+ { 9223372036854775807ull },\n+ {\n+ 0, 0, 0, 0,\n+ 1, 1, 1, 1,\n+ 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull,\n+ 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull,\n+ },\n+ {\n+ 0, 0, 0, 0,\n+ 0, 0, 0, 0,\n+ 0, 0, 0, 0,\n+ 1, 1, 1, 1,\n+ },\n+ },\n+ {\n+ { 18446744073709551615ull },\n+ {\n+ 0, 0, 0, 0,\n+ 1, 1, 1, 1,\n+ 2, 2, 2, 2,\n+ 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull,\n+ },\n+ {\n+ 0, 0, 0, 0,\n+ 0, 0, 0, 0,\n+ 0, 0, 0, 0,\n+ 0, 0, 0, 0,\n+ },\n+ },\n+};\n+\n #endif\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgtu-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgtu-run-1-u16.c\nnew file mode 100644\nindex 00000000000..8fcc3041050\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgtu-run-1-u16.c\n@@ -0,0 +1,15 @@\n+/* { dg-do run { target { riscv_v } } } */\n+/* { dg-additional-options \"-std=c99 --param=gpr2vr-cost=0\" } */\n+\n+#include \"vx_binary.h\"\n+#include \"vx_binary_data.h\"\n+\n+#define T uint16_t\n+#define NAME gtu\n+\n+DEF_VX_BINARY_CASE_0_WRAP(T, >, NAME)\n+\n+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)\n+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)\n+\n+#include \"vx_binary_run.h\"\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgtu-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgtu-run-1-u32.c\nnew file mode 100644\nindex 00000000000..ed269c8f50c\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgtu-run-1-u32.c\n@@ -0,0 +1,15 @@\n+/* { dg-do run { target { riscv_v } } } */\n+/* { dg-additional-options \"-std=c99 --param=gpr2vr-cost=0\" } */\n+\n+#include \"vx_binary.h\"\n+#include \"vx_binary_data.h\"\n+\n+#define T uint32_t\n+#define NAME gtu\n+\n+DEF_VX_BINARY_CASE_0_WRAP(T, >, NAME)\n+\n+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)\n+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)\n+\n+#include \"vx_binary_run.h\"\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgtu-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgtu-run-1-u64.c\nnew file mode 100644\nindex 00000000000..11752b43f6b\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgtu-run-1-u64.c\n@@ -0,0 +1,15 @@\n+/* { dg-do run { target { riscv_v } } } */\n+/* { dg-additional-options \"-std=c99 --param=gpr2vr-cost=0\" } */\n+\n+#include \"vx_binary.h\"\n+#include \"vx_binary_data.h\"\n+\n+#define T uint64_t\n+#define NAME gtu\n+\n+DEF_VX_BINARY_CASE_0_WRAP(T, >, NAME)\n+\n+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)\n+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)\n+\n+#include \"vx_binary_run.h\"\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgtu-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgtu-run-1-u8.c\nnew file mode 100644\nindex 00000000000..78c5835c94f\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgtu-run-1-u8.c\n@@ -0,0 +1,15 @@\n+/* { dg-do run { target { riscv_v } } } */\n+/* { dg-additional-options \"-std=c99 --param=gpr2vr-cost=0\" } */\n+\n+#include \"vx_binary.h\"\n+#include \"vx_binary_data.h\"\n+\n+#define T uint8_t\n+#define NAME gtu\n+\n+DEF_VX_BINARY_CASE_0_WRAP(T, >, NAME)\n+\n+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)\n+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)\n+\n+#include \"vx_binary_run.h\"\n","prefixes":["v1","2/2"]}