{"id":2229334,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2229334/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/patch/20260428072746.3641227-2-pan2.li@intel.com/","project":{"id":17,"url":"http://patchwork.ozlabs.org/api/1.1/projects/17/?format=json","name":"GNU Compiler Collection","link_name":"gcc","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260428072746.3641227-2-pan2.li@intel.com>","date":"2026-04-28T07:26:26","name":"[v1,1/2] RISC-V: Combine vec_duplicate + vmsgtu.vv to vmsgtu.vx on GR2VR cost","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"c7b56e3b229883e7a9607592fbf60b5679e95438","submitter":{"id":86320,"url":"http://patchwork.ozlabs.org/api/1.1/people/86320/?format=json","name":"Li, Pan2","email":"pan2.li@intel.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/gcc/patch/20260428072746.3641227-2-pan2.li@intel.com/mbox/","series":[{"id":501773,"url":"http://patchwork.ozlabs.org/api/1.1/series/501773/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/list/?series=501773","date":"2026-04-28T07:26:25","name":"RISC-V: Combine vec_duplicate + vmsgtu.vv to vmsgtu.vx on GR2VR cost","version":1,"mbox":"http://patchwork.ozlabs.org/series/501773/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2229334/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2229334/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=MKZNPyCe;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; 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d=\"scan'208\";a=\"233746055\""],"X-ExtLoop1":"1","From":"pan2.li@intel.com","To":"gcc-patches@gcc.gnu.org","Cc":"juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com,\n rdapp.gcc@gmail.com, ken.chen@intel.com, hongtao.liu@intel.com,\n Pan Li ","Subject":"[PATCH v1 1/2] RISC-V: Combine vec_duplicate + vmsgtu.vv to vmsgtu.vx\n on GR2VR cost","Date":"Tue, 28 Apr 2026 15:26:26 +0800","Message-ID":"<20260428072746.3641227-2-pan2.li@intel.com>","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"<20260428072746.3641227-1-pan2.li@intel.com>","References":"<20260428072746.3641227-1-pan2.li@intel.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org"},"content":"From: Pan Li \n\nThis patch would like to combine the vec_duplicate + vmsgtu.vv to the\nvmsgtu.vx. From example as below code. The related pattern will depend\non the cost of vec_duplicate from GR2VR. Then the late-combine will\ntake action if the cost of GR2VR is zero, and reject the combination\nif the GR2VR cost is greater than zero.\n\nAssume we have asm code like below, GR2VR cost is 0.\n\nBefore this patch:\n 11 beq a3,zero,.L8\n 12 vsetvli a5,zero,e32,m1,ta,ma\n 13 vmv.v.x v2,a2\n ...\n 16 .L3:\n 17 vsetvli a5,a3,e32,m1,ta,ma\n ...\n 22 vmsgtu.vv v1,v2,v3\n ...\n 25 bne a3,zero,.L3\n\nAfter this patch:\n 11 beq a3,zero,.L8\n ...\n 14 .L3:\n 15 vsetvli a5,a3,e32,m1,ta,ma\n ...\n 20 vmsgtu.vx v1,a2,v3\n ...\n 23 bne a3,zero,.L3\n\ngcc/ChangeLog:\n\n\t* config/riscv/predicates.md: Add ltu to swappable\n\tcmp operator.\n\t* config/riscv/riscv-v.cc (get_swapped_cmp_rtx_code): Handle\n\tthe swapped rtx code as well.\n\nSigned-off-by: Pan Li \n---\n gcc/config/riscv/predicates.md | 2 +-\n gcc/config/riscv/riscv-v.cc | 2 ++\n 2 files changed, 3 insertions(+), 1 deletion(-)","diff":"diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md\nindex 8022c84b114..4116674601c 100644\n--- a/gcc/config/riscv/predicates.md\n+++ b/gcc/config/riscv/predicates.md\n@@ -612,7 +612,7 @@ (define_predicate \"comparison_except_ge_operator\"\n (match_code \"eq,ne,le,leu,gt,gtu,lt,ltu\"))\n \n (define_predicate \"comparison_swappable_operator\"\n- (match_code \"gtu,gt,geu,ge\"))\n+ (match_code \"gtu,gt,geu,ge,ltu\"))\n \n (define_predicate \"ge_operator\"\n (match_code \"ge,geu\"))\ndiff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc\nindex cfea5dd693e..3c7e749cb60 100644\n--- a/gcc/config/riscv/riscv-v.cc\n+++ b/gcc/config/riscv/riscv-v.cc\n@@ -6073,6 +6073,8 @@ get_swapped_cmp_rtx_code (rtx_code code)\n return LEU;\n case GE:\n return LE;\n+ case LTU:\n+ return GTU;\n default:\n gcc_unreachable ();\n }\n","prefixes":["v1","1/2"]}