{"id":2229301,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2229301/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20260428034822.23756-10-alif.zakuan.yuslaimi@altera.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.1/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260428034822.23756-10-alif.zakuan.yuslaimi@altera.com>","date":"2026-04-28T03:48:22","name":"[v2,9/9] spl: s10: Enhance watchdog support in SPL for Stratix 10","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"c6d1462d3967fd3ed805da6421ebbf0e44f277c5","submitter":{"id":90458,"url":"http://patchwork.ozlabs.org/api/1.1/people/90458/?format=json","name":"YUSLAIMI, ALIF ZAKUAN","email":"alif.zakuan.yuslaimi@altera.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20260428034822.23756-10-alif.zakuan.yuslaimi@altera.com/mbox/","series":[{"id":501758,"url":"http://patchwork.ozlabs.org/api/1.1/series/501758/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=501758","date":"2026-04-28T03:48:13","name":"SoCFPGA: Update Boot Support for Stratix10 in U-Boot","version":2,"mbox":"http://patchwork.ozlabs.org/series/501758/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2229301/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2229301/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=altera.com header.i=@altera.com header.a=rsa-sha256\n header.s=selector2 header.b=RxOczy6E;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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This requires clocks and reset to be valid for\nthe L4 watchdog block, and so it must run after the clock manager\n(uclass_get_device(UCLASS_CLK)) succeeds.\n\nEnabling watchdog immediately after clock init keeps watchdog coverage as\nearly as possible.\n\nSigned-off-by: Alif Zakuan Yuslaimi \n---\n arch/arm/mach-socfpga/spl_s10.c | 16 ++++++++--------\n 1 file changed, 8 insertions(+), 8 deletions(-)","diff":"diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c\nindex ace029557f3..588dca4fcd3 100644\n--- a/arch/arm/mach-socfpga/spl_s10.c\n+++ b/arch/arm/mach-socfpga/spl_s10.c\n@@ -18,7 +18,7 @@\n #include \n #include \n #include \n-#include \n+#include \n #include \n \n u32 reset_flag(void)\n@@ -54,13 +54,6 @@ void board_init_f(ulong dummy)\n \twritel(SYSMGR_WDDBG_PAUSE_ALL_CPU,\n \t socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG);\n \n-#ifdef CONFIG_HW_WATCHDOG\n-\t/* Enable watchdog before initializing the HW */\n-\tsocfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);\n-\tsocfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);\n-\thw_watchdog_init();\n-#endif\n-\n \t/* ensure all processors are not released prior Linux boot */\n \twriteq(0, CPU_RELEASE_ADDR);\n \n@@ -80,6 +73,13 @@ void board_init_f(ulong dummy)\n \t\thang();\n \t}\n \n+\t/*\n+\t * Enable watchdog as early as possible before initializing other\n+\t * component.\n+\t */\n+\tif (CONFIG_IS_ENABLED(WDT))\n+\t\tinitr_watchdog();\n+\n #ifdef CONFIG_DEBUG_UART\n \tsocfpga_per_reset(SOCFPGA_RESET(UART0), 0);\n \tdebug_uart_init();\n","prefixes":["v2","9/9"]}