{"id":2229298,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2229298/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20260428034822.23756-7-alif.zakuan.yuslaimi@altera.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.1/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260428034822.23756-7-alif.zakuan.yuslaimi@altera.com>","date":"2026-04-28T03:48:19","name":"[v2,6/9] ddr: altera: soc64: Add secure region support for ATF flow","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"e773361b8441d13e93e48afb646c3126f645227f","submitter":{"id":90458,"url":"http://patchwork.ozlabs.org/api/1.1/people/90458/?format=json","name":"YUSLAIMI, ALIF ZAKUAN","email":"alif.zakuan.yuslaimi@altera.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20260428034822.23756-7-alif.zakuan.yuslaimi@altera.com/mbox/","series":[{"id":501758,"url":"http://patchwork.ozlabs.org/api/1.1/series/501758/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=501758","date":"2026-04-28T03:48:13","name":"SoCFPGA: Update Boot Support for Stratix10 in U-Boot","version":2,"mbox":"http://patchwork.ozlabs.org/series/501758/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2229298/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2229298/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=altera.com header.i=@altera.com header.a=rsa-sha256\n header.s=selector2 header.b=tmfTFPzq;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; 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The ARM Trusted Firmware (ATF)\nimage is located in this first 1 MiB memory region. So, this can prevent\nsoftware executing at non-secure state EL0-EL2 and non-secure masters\naccess to secure region.\n\nAdd common function for firewall setup and reuse for all SoC64 devices.\n\nSigned-off-by: Alif Zakuan Yuslaimi \n---\n drivers/ddr/altera/sdram_s10.c | 16 ++--------------\n 1 file changed, 2 insertions(+), 14 deletions(-)","diff":"diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c\nindex 1497a8e4aab..aed53ae58eb 100644\n--- a/drivers/ddr/altera/sdram_s10.c\n+++ b/drivers/ddr/altera/sdram_s10.c\n@@ -78,20 +78,6 @@ int sdram_mmr_init_full(struct udevice *dev)\n \tphys_size_t hw_size;\n \tstruct bd_info bd = {0};\n \n-\t/* this enables nonsecure access to DDR */\n-\t/* mpuregion0addr_limit */\n-\tFW_MPU_DDR_SCR_WRITEL(0xFFFF0000, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT);\n-\tFW_MPU_DDR_SCR_WRITEL(0x1F, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT);\n-\n-\t/* nonmpuregion0addr_limit */\n-\tFW_MPU_DDR_SCR_WRITEL(0xFFFF0000,\n-\t\t\t FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT);\n-\tFW_MPU_DDR_SCR_WRITEL(0x1F, FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT);\n-\n-\t/* Enable mpuregion0enable and nonmpuregion0enable */\n-\tFW_MPU_DDR_SCR_WRITEL(MPUREGION0_ENABLE | NONMPUREGION0_ENABLE,\n-\t\t\t FW_MPU_DDR_SCR_EN_SET);\n-\n \t/* Ensure HMC clock is running */\n \tif (poll_hmc_clock_status()) {\n \t\tputs(\"DDR: Error as HMC clock not running\\n\");\n@@ -284,6 +270,8 @@ int sdram_mmr_init_full(struct udevice *dev)\n \n \tsdram_size_check(&bd);\n \n+\tsdram_set_firewall(&bd);\n+\n \tpriv->info.base = bd.bi_dram[0].start;\n \tpriv->info.size = gd->ram_size;\n \n","prefixes":["v2","6/9"]}