{"id":2229290,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2229290/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20260428033230.7777-4-alif.zakuan.yuslaimi@altera.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.1/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260428033230.7777-4-alif.zakuan.yuslaimi@altera.com>","date":"2026-04-28T03:32:30","name":"[v2,3/3] ddr: socfpga: Add ECC DRAM scrubbing support for Gen5/Arria10","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"0b51adc0ec2941fce49c58752fbb88fb25d93001","submitter":{"id":90458,"url":"http://patchwork.ozlabs.org/api/1.1/people/90458/?format=json","name":"YUSLAIMI, ALIF ZAKUAN","email":"alif.zakuan.yuslaimi@altera.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20260428033230.7777-4-alif.zakuan.yuslaimi@altera.com/mbox/","series":[{"id":501756,"url":"http://patchwork.ozlabs.org/api/1.1/series/501756/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=501756","date":"2026-04-28T03:32:27","name":"SoCFPGA: Update DDR Support for Gen5/Arria10 in U-Boot","version":2,"mbox":"http://patchwork.ozlabs.org/series/501756/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2229290/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2229290/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=altera.com header.i=@altera.com header.a=rsa-sha256\n header.s=selector2 header.b=htJn5S7n;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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Make the CPU overwrite the DRAM with zeroes in such a\ncase.\n\nThis implementation turns the caches on temporarily, then overwrites the\nwhole RAM with zeroes, flushes the caches and turns them off again.\nThis provides satisfactory performance.\n\nMove common code sdram_init_ecc_bits() to new common file sdram_soc32.c.\nPreparation for Gen5 uses the same memory initialization function as\nArria10.\n\nNew Kconfig is introduced to enable this implementation only on the default\nArria10 and CycloneV boards as this will increase the SPL size which\nwill exceed some Gen5 devices' SPL size limit.\n\nSigned-off-by: Tien Fong Chee \nSigned-off-by: Alif Zakuan Yuslaimi \n---\n arch/arm/mach-socfpga/Kconfig | 13 ++++-\n arch/arm/mach-socfpga/spl_a10.c | 4 ++\n arch/arm/mach-socfpga/spl_gen5.c | 17 ++++++\n drivers/ddr/altera/Makefile | 4 +-\n drivers/ddr/altera/sdram_arria10.c | 34 +++++-------\n drivers/ddr/altera/sdram_gen5.c | 41 ++++++++++++--\n drivers/ddr/altera/sdram_soc32.c | 85 ++++++++++++++++++++++++++++++\n drivers/ddr/altera/sdram_soc32.h | 15 ++++++\n 8 files changed, 187 insertions(+), 26 deletions(-)\n create mode 100644 drivers/ddr/altera/sdram_soc32.c\n create mode 100644 drivers/ddr/altera/sdram_soc32.h","diff":"diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig\nindex 830585a72cc..dd71691b724 100644\n--- a/arch/arm/mach-socfpga/Kconfig\n+++ b/arch/arm/mach-socfpga/Kconfig\n@@ -6,6 +6,13 @@ config ERR_PTR_OFFSET\n config NR_DRAM_BANKS\n \tdefault 1\n \n+config SOCFPGA_ECC_SUPPORT\n+\tbool \"Enable ECC support for DRAM\"\n+\thelp\n+\t Adds CPU-based ECC support for DRAM at boot. This will initialize\n+\t all DRAM ECC metadata to zero, preventing false ECC errors and\n+\t improving reliability.\n+\n config SOCFPGA_DRAM_SIZE_CHECK\n \tbool \"Enable DRAM size checking for safety\"\n \thelp\n@@ -105,6 +112,7 @@ config ARCH_SOCFPGA_ARRIA10\n \tselect ETH_DESIGNWARE_SOCFPGA\n \timply FPGA_SOCFPGA\n \timply SPL_USE_TINY_PRINTF\n+\tselect SOCFPGA_ECC_SUPPORT\n \n config SOCFPGA_ARRIA10_ALWAYS_REPROGRAM\n \tbool \"Always reprogram Arria 10 FPGA\"\n@@ -117,6 +125,9 @@ config SOCFPGA_ARRIA10_ALWAYS_REPROGRAM\n config ARCH_SOCFPGA_CYCLONE5\n \tbool\n \tselect ARCH_SOCFPGA_GEN5\n+\tselect SOCFPGA_ECC_SUPPORT if \\\n+\t !TARGET_SOCFPGA_TERASIC_SOCKIT && !TARGET_SOCFPGA_EBV_SOCRATES \\\n+\t && !TARGET_SOCFPGA_SOFTING_VINING_FPGA\n \tselect SOCFPGA_DRAM_SIZE_CHECK if !TARGET_SOCFPGA_TERASIC_SOCKIT \\\n \t && !TARGET_SOCFPGA_EBV_SOCRATES && \\\n \t !TARGET_SOCFPGA_SOFTING_VINING_FPGA\n@@ -124,7 +135,7 @@ config ARCH_SOCFPGA_CYCLONE5\n config ARCH_SOCFPGA_GEN5\n \tbool\n \tselect SPL_ALTERA_SDRAM\n-\tselect SPL_CACHE if SPL\n+\tselect SPL_CACHE if SPL && SOCFPGA_ECC_SUPPORT\n \timply FPGA_SOCFPGA\n \timply SPL_SIZE_LIMIT_SUBTRACT_GD\n \timply SPL_SIZE_LIMIT_SUBTRACT_MALLOC\ndiff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c\nindex c20376f7f8e..4d0696bbaf6 100644\n--- a/arch/arm/mach-socfpga/spl_a10.c\n+++ b/arch/arm/mach-socfpga/spl_a10.c\n@@ -25,6 +25,7 @@\n #include \n #include \n #include \n+#include \n #include \n #include \n #include \n@@ -265,6 +266,9 @@ void board_init_f(ulong dummy)\n \t/* Configure the clock based on handoff */\n \tcm_basic_init(gd->fdt_blob);\n \n+\tif (CONFIG_IS_ENABLED(WDT))\n+\t\tinitr_watchdog();\n+\n #ifdef CONFIG_HW_WATCHDOG\n \t/* release osc1 watchdog timer 0 from reset */\n \tsocfpga_reset_deassert_osc1wd0();\ndiff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c\nindex 08b756db2ca..530863b1564 100644\n--- a/arch/arm/mach-socfpga/spl_gen5.c\n+++ b/arch/arm/mach-socfpga/spl_gen5.c\n@@ -6,6 +6,7 @@\n #include \n #include \n #include \n+#include \n #include \n #include \n #include \n@@ -21,9 +22,17 @@\n #include \n #include \n #include \n+#include \n #include \n #include \n \n+DECLARE_GLOBAL_DATA_PTR;\n+\n+#if IS_ENABLED(CONFIG_SOCFPGA_ECC_SUPPORT) || \\\n+\tIS_ENABLED(CONFIG_SOCFPGA_DRAM_SIZE_CHECK)\n+static struct bd_info bdata __attribute__ ((section(\".data\")));\n+#endif\n+\n u32 spl_boot_device(void)\n {\n \tconst u32 bsel = readl(socfpga_get_sysmgr_addr() +\n@@ -106,6 +115,9 @@ void board_init_f(ulong dummy)\n \tif (cm_basic_init(cm_default_cfg))\n \t\thang();\n \n+\tif (CONFIG_IS_ENABLED(WDT))\n+\t\tinitr_watchdog();\n+\n \t/* Enable bootrom to configure IOs. */\n \tsysmgr_config_warmrstcfgio(1);\n \n@@ -143,6 +155,11 @@ void board_init_f(ulong dummy)\n \t/* enable console uart printing */\n \tpreloader_console_init();\n \n+#if IS_ENABLED(CONFIG_SOCFPGA_ECC_SUPPORT) || \\\n+\tIS_ENABLED(CONFIG_SOCFPGA_DRAM_SIZE_CHECK)\n+\tgd->bd = &bdata;\n+#endif\n+\n \tret = uclass_get_device(UCLASS_RAM, 0, &dev);\n \tif (ret) {\n \t\tdebug(\"DRAM init failed: %d\\n\", ret);\ndiff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile\nindex 8259ab04a7e..ece6a131897 100644\n--- a/drivers/ddr/altera/Makefile\n+++ b/drivers/ddr/altera/Makefile\n@@ -7,8 +7,8 @@\n # Copyright (C) 2014-2025 Altera Corporation \n \n ifdef CONFIG_$(PHASE_)ALTERA_SDRAM\n-obj-$(CONFIG_ARCH_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o\n-obj-$(CONFIG_ARCH_SOCFPGA_ARRIA10) += sdram_arria10.o\n+obj-$(CONFIG_ARCH_SOCFPGA_GEN5) += sdram_soc32.o sdram_gen5.o sequencer.o\n+obj-$(CONFIG_ARCH_SOCFPGA_ARRIA10) += sdram_soc32.o sdram_arria10.o\n obj-$(CONFIG_ARCH_SOCFPGA_STRATIX10) += sdram_soc64.o sdram_s10.o\n obj-$(CONFIG_ARCH_SOCFPGA_AGILEX) += sdram_soc64.o sdram_agilex.o\n obj-$(CONFIG_ARCH_SOCFPGA_N5X) += sdram_soc64.o sdram_n5x.o\ndiff --git a/drivers/ddr/altera/sdram_arria10.c b/drivers/ddr/altera/sdram_arria10.c\nindex c281f711fdf..09d3526603e 100644\n--- a/drivers/ddr/altera/sdram_arria10.c\n+++ b/drivers/ddr/altera/sdram_arria10.c\n@@ -22,9 +22,13 @@\n #include \n #include \n #include \n+#include \n+#include \"sdram_soc32.h\"\n \n DECLARE_GLOBAL_DATA_PTR;\n \n+#define PGTABLE_OFF\t0x4000\n+\n static void sdram_mmr_init(void);\n static u64 sdram_size_calc(void);\n \n@@ -193,24 +197,6 @@ static int sdram_is_ecc_enabled(void)\n \t\t ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK);\n }\n \n-/* Initialize SDRAM ECC bits to avoid false DBE */\n-static void sdram_init_ecc_bits(u32 size)\n-{\n-\ticache_enable();\n-\n-\tmemset(0, 0, 0x8000);\n-\tgd->arch.tlb_addr = 0x4000;\n-\tgd->arch.tlb_size = PGTABLE_SIZE;\n-\n-\tdcache_enable();\n-\n-\tprintf(\"DDRCAL: Scrubbing ECC RAM (%i MiB).\\n\", size >> 20);\n-\tmemset((void *)0x8000, 0, size - 0x8000);\n-\tflush_dcache_all();\n-\tprintf(\"DDRCAL: Scrubbing ECC RAM done.\\n\");\n-\tdcache_disable();\n-}\n-\n /* Function to startup the SDRAM*/\n static int sdram_startup(void)\n {\n@@ -735,8 +721,16 @@ int ddr_calibration_sequence(void)\n \tif (of_sdram_firewall_setup(gd->fdt_blob))\n \t\tputs(\"FW: Error Configuring Firewall\\n\");\n \n-\tif (sdram_is_ecc_enabled())\n-\t\tsdram_init_ecc_bits(gd->ram_size);\n+\tif (sdram_is_ecc_enabled()) {\n+#if IS_ENABLED(CONFIG_SOCFPGA_ECC_SUPPORT)\n+\t\tsdram_init_ecc_bits();\n+\t}\n+#else\n+\t\tputs(\"DDR: Enable CONFIG_SOCFPGA_ECC_SUPPORT when SDRAM \");\n+\t\tputs(\"ECC is enabled.\\n\");\n+\t\thang();\n+\t}\n+#endif\n \n \tsdram_size_check();\n \ndiff --git a/drivers/ddr/altera/sdram_gen5.c b/drivers/ddr/altera/sdram_gen5.c\nindex 1c3c70ea8ae..76effb264e2 100644\n--- a/drivers/ddr/altera/sdram_gen5.c\n+++ b/drivers/ddr/altera/sdram_gen5.c\n@@ -2,6 +2,7 @@\n /*\n * Copyright Altera Corporation (C) 2014-2015\n */\n+#include \n #include \n #include \n #include \n@@ -19,8 +20,11 @@\n #include \n #include \n #include \n-\n+#include \n #include \"sequencer.h\"\n+#include \"sdram_soc32.h\"\n+\n+#define PGTABLE_OFF\t0x4000\n \n #ifdef CONFIG_XPL_BUILD\n \n@@ -566,6 +570,19 @@ static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl)\n \treturn temp;\n }\n \n+#if IS_ENABLED(CONFIG_SOCFPGA_ECC_SUPPORT)\n+static int sdram_is_ecc_enabled(struct socfpga_sdr_ctrl *sdr_ctrl)\n+{\n+\treturn !!(readl(&sdr_ctrl->ctrl_cfg) &\n+\t\t SDR_CTRLGRP_CTRLCFG_ECCEN_MASK);\n+}\n+#else\n+static int sdram_is_ecc_enabled(struct socfpga_sdr_ctrl *sdr_ctrl)\n+{\n+ return 0;\n+}\n+#endif\n+\n static int altera_gen5_sdram_of_to_plat(struct udevice *dev)\n {\n \tstruct altera_gen5_sdram_plat *plat = dev_get_plat(dev);\n@@ -608,10 +625,13 @@ static int altera_gen5_sdram_probe(struct udevice *dev)\n \tsdram_size = sdram_calculate_size(sdr_ctrl);\n \tdebug(\"SDRAM: %ld MiB\\n\", sdram_size >> 20);\n \n-#if IS_ENABLED(CONFIG_SOCFPGA_DRAM_SIZE_CHECK)\n+#if IS_ENABLED(CONFIG_SOCFPGA_DRAM_SIZE_CHECK) || \\\n+ IS_ENABLED(CONFIG_SOCFPGA_ECC_SUPPORT)\n \t/* setup the dram info within bd */\n \tdram_init_banksize();\n+#endif\n \n+#if IS_ENABLED(CONFIG_SOCFPGA_DRAM_SIZE_CHECK)\n \tif (sdram_size != gd->bd->bi_dram[0].size) {\n \t\tprintf(\"DDR: Warning: DRAM size from device tree (%lu MiB)\\n\",\n \t\t (ulong)(gd->bd->bi_dram[0].size >> 20));\n@@ -626,8 +646,23 @@ static int altera_gen5_sdram_probe(struct udevice *dev)\n \t}\n #endif\n \n+\tif (sdram_is_ecc_enabled(sdr_ctrl)) {\n+#if IS_ENABLED(CONFIG_SOCFPGA_ECC_SUPPORT)\n+\t\t/* Must set USEECCASDATA to 0 if ECC is enabled */\n+\t\tclrbits_le32(&sdr_ctrl->static_cfg,\n+\t\t\t SDR_CTRLGRP_STATICCFG_USEECCASDATA_MASK);\n+\t\tsdram_init_ecc_bits();\n+#else\n+\t\tputs(\"DDR: Enable CONFIG_SOCFPGA_ECC_SUPPORT when SDRAM \");\n+\t\tputs(\"ECC is enabled.\\n\");\n+\t\tputs(\"DDR: Without scrub, false ECC errors may occur.\\n\");\n+\t\thang();\n+#endif\n+}\n+\n \t/* Sanity check ensure correct SDRAM size specified */\n-#if IS_ENABLED(CONFIG_SOCFPGA_DRAM_SIZE_CHECK)\n+#if IS_ENABLED(CONFIG_SOCFPGA_DRAM_SIZE_CHECK) || \\\n+ IS_ENABLED(CONFIG_SOCFPGA_ECC_SUPPORT)\n \tif (get_ram_size(0, gd->bd->bi_dram[0].size) !=\n \t gd->bd->bi_dram[0].size) {\n #else\ndiff --git a/drivers/ddr/altera/sdram_soc32.c b/drivers/ddr/altera/sdram_soc32.c\nnew file mode 100644\nindex 00000000000..7556d4933f4\n--- /dev/null\n+++ b/drivers/ddr/altera/sdram_soc32.c\n@@ -0,0 +1,85 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Copyright (C) 2026 Altera Corporation \n+ */\n+\n+#include \"sdram_soc32.h\"\n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#if !defined(CONFIG_HW_WATCHDOG)\n+#include \n+#endif\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+#define PGTABLE_OFF\t0x4000\n+#define PGTABLE_RESERVE (PGTABLE_OFF + PGTABLE_SIZE)\n+\n+#if IS_ENABLED(CONFIG_SOCFPGA_ECC_SUPPORT)\n+static void socfpga_prepare_watchdog_for_long_op(void)\n+{\n+#if !IS_ENABLED(CONFIG_WATCHDOG)\n+\t/*\n+\t * No DM watchdog support enabled. Previous boot stage may have left\n+\t * L4WD0 running, so stop it once before long DDR scrub operation.\n+\t */\n+\tsocfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);\n+\tsocfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);\n+#endif\n+}\n+\n+/* Initialize SDRAM ECC bits to avoid false DBE */\n+void sdram_init_ecc_bits(void)\n+{\n+\tu32 start;\n+\tphys_addr_t start_addr;\n+\tphys_size_t size, size_init;\n+\n+\tstart = get_timer(0);\n+\n+\tstart_addr = gd->bd->bi_dram[0].start;\n+\tsize = gd->bd->bi_dram[0].size;\n+\n+\tprintf(\"DDRCAL: Scrubbing ECC RAM (%lu MiB).\\n\",\n+\t (ulong)(size >> 20));\n+\n+\tif (size <= PGTABLE_RESERVE) {\n+\t\tprintf(\"DDRCAL: Error: DRAM size %#llx smaller than scrub reserve %#x\\n\",\n+\t\t (unsigned long long)size, PGTABLE_RESERVE);\n+\t\thang();\n+\t}\n+\n+\tmemset((void *)start_addr, 0, PGTABLE_RESERVE);\n+\tgd->arch.tlb_addr = start_addr + PGTABLE_OFF;\n+\tgd->arch.tlb_size = PGTABLE_SIZE;\n+\tstart_addr += PGTABLE_RESERVE;\n+\tsize -= PGTABLE_RESERVE;\n+\n+\tdcache_enable();\n+\n+\tsocfpga_prepare_watchdog_for_long_op();\n+\n+\twhile (size > 0) {\n+\t\tsize_init = min_t(phys_size_t, (phys_size_t)SZ_1G, size);\n+\t\tmemset((void *)start_addr, 0, size_init);\n+\t\tsize -= size_init;\n+\t\tstart_addr += size_init;\n+\n+#if IS_ENABLED(CONFIG_WATCHDOG)\n+\t\t/* Service DM watchdog cyclic callbacks */\n+\t\tschedule();\n+#endif\n+\t}\n+\n+\tdcache_disable();\n+\n+\tprintf(\"DDRCAL: SDRAM-ECC initialized success with %u ms\\n\",\n+\t (u32)get_timer(start));\n+}\n+#endif\ndiff --git a/drivers/ddr/altera/sdram_soc32.h b/drivers/ddr/altera/sdram_soc32.h\nnew file mode 100644\nindex 00000000000..2cfc583b5f5\n--- /dev/null\n+++ b/drivers/ddr/altera/sdram_soc32.h\n@@ -0,0 +1,15 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2026 Altera Corporation \n+ */\n+\n+#ifndef\t_SDRAM_SOC32_H_\n+#define\t_SDRAM_SOC32_H_\n+\n+#if IS_ENABLED(CONFIG_SOCFPGA_ECC_SUPPORT)\n+void sdram_init_ecc_bits(void);\n+#else\n+static inline void sdram_init_ecc_bits(void) { }\n+#endif\n+\n+#endif /* _SDRAM_SOC32_H_ */\n","prefixes":["v2","3/3"]}