{"id":2229289,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2229289/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20260428033230.7777-3-alif.zakuan.yuslaimi@altera.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.1/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260428033230.7777-3-alif.zakuan.yuslaimi@altera.com>","date":"2026-04-28T03:32:29","name":"[v2,2/3] ddr: altera: gen5: Add DRAM size checking","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"6e2510cfc8449e325b76376fb9bb0e664a76e89f","submitter":{"id":90458,"url":"http://patchwork.ozlabs.org/api/1.1/people/90458/?format=json","name":"YUSLAIMI, ALIF ZAKUAN","email":"alif.zakuan.yuslaimi@altera.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20260428033230.7777-3-alif.zakuan.yuslaimi@altera.com/mbox/","series":[{"id":501756,"url":"http://patchwork.ozlabs.org/api/1.1/series/501756/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=501756","date":"2026-04-28T03:32:27","name":"SoCFPGA: Update DDR Support for Gen5/Arria10 in U-Boot","version":2,"mbox":"http://patchwork.ozlabs.org/series/501756/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2229289/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2229289/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=altera.com header.i=@altera.com header.a=rsa-sha256\n header.s=selector2 header.b=T+9IIuN+;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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So, it has consistency with\nother device families.\n\nNew Kconfig is introduced to enable this implementation only on the default\nCycloneV board as this will increase the SPL size which will exceed some\nGen5 devices' SPL size limit.\n\nSigned-off-by: Alif Zakuan Yuslaimi \n---\n arch/arm/mach-socfpga/Kconfig | 9 +++++++++\n drivers/ddr/altera/sdram_gen5.c | 27 +++++++++++++++++++++++++++\n 2 files changed, 36 insertions(+)","diff":"diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig\nindex e2fdd6bb30f..830585a72cc 100644\n--- a/arch/arm/mach-socfpga/Kconfig\n+++ b/arch/arm/mach-socfpga/Kconfig\n@@ -6,6 +6,12 @@ config ERR_PTR_OFFSET\n config NR_DRAM_BANKS\n \tdefault 1\n \n+config SOCFPGA_DRAM_SIZE_CHECK\n+\tbool \"Enable DRAM size checking for safety\"\n+\thelp\n+\t Compares device tree DRAM size with actual hardware. Hangs on\n+\t oversized claim.\n+\n config SOCFPGA_SECURE_VAB_AUTH\n \tbool \"Enable boot image authentication with Secure Device Manager\"\n \tdepends on ARCH_SOCFPGA_AGILEX || ARCH_SOCFPGA_N5X || \\\n@@ -111,6 +117,9 @@ config SOCFPGA_ARRIA10_ALWAYS_REPROGRAM\n config ARCH_SOCFPGA_CYCLONE5\n \tbool\n \tselect ARCH_SOCFPGA_GEN5\n+\tselect SOCFPGA_DRAM_SIZE_CHECK if !TARGET_SOCFPGA_TERASIC_SOCKIT \\\n+\t && !TARGET_SOCFPGA_EBV_SOCRATES && \\\n+\t !TARGET_SOCFPGA_SOFTING_VINING_FPGA\n \n config ARCH_SOCFPGA_GEN5\n \tbool\ndiff --git a/drivers/ddr/altera/sdram_gen5.c b/drivers/ddr/altera/sdram_gen5.c\nindex 3c79bb11802..1c3c70ea8ae 100644\n--- a/drivers/ddr/altera/sdram_gen5.c\n+++ b/drivers/ddr/altera/sdram_gen5.c\n@@ -5,6 +5,7 @@\n #include \n #include \n #include \n+#include \n #include \n #include \n #include \n@@ -15,6 +16,7 @@\n #include \n #include \n #include \n+#include \n #include \n #include \n \n@@ -22,6 +24,8 @@\n \n #ifdef CONFIG_XPL_BUILD\n \n+DECLARE_GLOBAL_DATA_PTR;\n+\n struct altera_gen5_sdram_priv {\n \tstruct ram_info info;\n };\n@@ -604,8 +608,31 @@ static int altera_gen5_sdram_probe(struct udevice *dev)\n \tsdram_size = sdram_calculate_size(sdr_ctrl);\n \tdebug(\"SDRAM: %ld MiB\\n\", sdram_size >> 20);\n \n+#if IS_ENABLED(CONFIG_SOCFPGA_DRAM_SIZE_CHECK)\n+\t/* setup the dram info within bd */\n+\tdram_init_banksize();\n+\n+\tif (sdram_size != gd->bd->bi_dram[0].size) {\n+\t\tprintf(\"DDR: Warning: DRAM size from device tree (%lu MiB)\\n\",\n+\t\t (ulong)(gd->bd->bi_dram[0].size >> 20));\n+\t\tprintf(\" mismatch with hardware (%lu MiB).\\n\",\n+\t\t (ulong)(sdram_size >> 20));\n+\t}\n+\n+\tif (gd->bd->bi_dram[0].size > sdram_size) {\n+\t\tprintf(\"DDR: Error: DRAM size from device tree is greater\\n\");\n+\t\tprintf(\" than hardware size.\\n\");\n+\t\thang();\n+\t}\n+#endif\n+\n \t/* Sanity check ensure correct SDRAM size specified */\n+#if IS_ENABLED(CONFIG_SOCFPGA_DRAM_SIZE_CHECK)\n+\tif (get_ram_size(0, gd->bd->bi_dram[0].size) !=\n+\t gd->bd->bi_dram[0].size) {\n+#else\n \tif (get_ram_size(0, sdram_size) != sdram_size) {\n+#endif\n \t\tputs(\"SDRAM size check failed!\\n\");\n \t\tgoto failed;\n \t}\n","prefixes":["v2","2/3"]}