{"id":2229282,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2229282/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/0c4ee6a31621d15f789586ea5f9e1f5443e622fb.1777345877.git.weijie.gao@mediatek.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.1/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<0c4ee6a31621d15f789586ea5f9e1f5443e622fb.1777345877.git.weijie.gao@mediatek.com>","date":"2026-04-28T03:31:59","name":"[2/6] mtd: spi-nor-ids: Add support for ESMT/EON EN25QX128A/EN25QH256/EN25QX256A","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"0303cfc382d6ee5e5d8c8429ea9c9a89e4a82d95","submitter":{"id":75269,"url":"http://patchwork.ozlabs.org/api/1.1/people/75269/?format=json","name":"Weijie Gao","email":"weijie.gao@mediatek.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/0c4ee6a31621d15f789586ea5f9e1f5443e622fb.1777345877.git.weijie.gao@mediatek.com/mbox/","series":[{"id":501755,"url":"http://patchwork.ozlabs.org/api/1.1/series/501755/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=501755","date":"2026-04-28T03:28:46","name":"Fix and add some spi-nor flash parts","version":1,"mbox":"http://patchwork.ozlabs.org/series/501755/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2229282/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2229282/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=mediatek.com header.i=@mediatek.com header.a=rsa-sha256\n header.s=dk header.b=OHkrbL2+;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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Tue, 28 Apr 2026 05:32:11 +0200 (CEST)","from mailgw02.mediatek.com (unknown [210.61.82.184])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 99AA184119\n for ; Tue, 28 Apr 2026 05:32:07 +0200 (CEST)","from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by\n mailgw02.mediatek.com (envelope-from )\n (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256)\n with ESMTP id 732367278; Tue, 28 Apr 2026 11:32:01 +0800","from mtkmbs13n2.mediatek.inc (172.21.101.108) by\n mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.2.2562.29; Tue, 28 Apr 2026 11:32:00 +0800","from mcddlt001.gcn.mediatek.inc (10.19.240.15) by\n mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id\n 15.2.2562.29 via Frontend Transport; Tue, 28 Apr 2026 11:31:59 +0800"],"X-Spam-Checker-Version":"SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-1.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED,\n RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL,RDNS_NONE,SPF_HELO_PASS,SPF_PASS,\n UNPARSEABLE_RELAY autolearn=no autolearn_force=no version=3.4.2","X-UUID":["d1749d1642b211f19a16598d5ca7f8ec-20260428","d1749d1642b211f19a16598d5ca7f8ec-20260428"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n d=mediatek.com;\n s=dk;\n h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From;\n bh=JCz8APH/EDx4F6rN9lLh3wP05/S9EDEqwa2Bmao5WFY=;\n b=OHkrbL2+DLgNWJY2HibKF7Cf1QavbjoK5UzWhoxN4vRlHrMIdDJNz9XQZH35nuKKgAXIBs+aXy4CalYUVyNf0aZ6fkeqsBQc8wzvozF7SDdipHLYMzBaKAfsp2I0qN7L6Ya9atF3HUBFG+aLxqnYfosV9KsoauxY05vK1fyExZs=;","X-CID-P-RULE":"Release_Ham","X-CID-O-INFO":"VERSION:1.3.12, REQID:18a8bed7-f9ce-46ff-a802-d96e6630b8b3,\n IP:0,\n U\n RL:0,TC:0,Content:-25,EDM:-25,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACT\n ION:release,TS:-50","X-CID-META":"VersionHash:e7bac3a, CLOUDID:7502c744-8360-4d24-8500-9b9380fa4b0d,\n B\n ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102|836|865|888|898,TC:-5,Cont\n ent:0|15|50,EDM:2,IP:nil,URL:99|1,File:130,RT:0,Bulk:nil,QS:nil,BEC:-1,COL\n :0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0","X-CID-BVR":"2,SSN|SDN","X-CID-BAS":"2,SSN|SDN,0,_","X-CID-FACTOR":"TF_CID_SPAM_ULS,TF_CID_SPAM_SNR","X-CID-RHF":"D41D8CD98F00B204E9800998ECF8427E","From":"Weijie Gao ","To":"","CC":"GSS_MTK_Uboot_upstream , Tom Rini\n , Vignesh R , Takahiro Kuwano\n , Marek Vasut\n , Tudor Ambarus ,\n Jeffrey Yu , Christoph Reiter ,\n Venkatesh Yadav Abbarapu , Miquel Raynal\n , Shiji Yang , Bernhard\n Messerklinger , Vaishnav Achath\n , Prasad Kummari , Weijie Gao\n ","Subject":"[PATCH 2/6] mtd: spi-nor-ids: Add support for ESMT/EON\n EN25QX128A/EN25QH256/EN25QX256A","Date":"Tue, 28 Apr 2026 11:31:59 +0800","Message-ID":"\n <0c4ee6a31621d15f789586ea5f9e1f5443e622fb.1777345877.git.weijie.gao@mediatek.com>","X-Mailer":"git-send-email 2.17.0","In-Reply-To":"","References":"","MIME-Version":"1.0","Content-Type":"text/plain","X-MTK":"N","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.39","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"},"content":"Datasheets can be found here:\nhttps://www.esmt.com.tw/upload/pdf/ESMT/datasheets/EN25QX128A(2V).pdf\nhttps://www.esmt.com.tw/upload/pdf/ESMT/datasheets/EN25QH256A(2R).pdf\n\nSigned-off-by: Weijie Gao \n---\n drivers/mtd/spi/spi-nor-core.c | 1 +\n drivers/mtd/spi/spi-nor-ids.c | 5 +++++\n include/linux/mtd/spi-nor.h | 1 +\n 3 files changed, 7 insertions(+)","diff":"diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c\nindex 937d79af64e..e4f78e740ba 100644\n--- a/drivers/mtd/spi/spi-nor-core.c\n+++ b/drivers/mtd/spi/spi-nor-core.c\n@@ -758,6 +758,7 @@ static int set_4byte(struct spi_nor *nor, const struct flash_info *info,\n \tcase SNOR_MFR_ISSI:\n \tcase SNOR_MFR_MACRONIX:\n \tcase SNOR_MFR_WINBOND:\n+\tcase SNOR_MFR_EON:\n \t\tif (need_wren)\n \t\t\twrite_enable(nor);\n \ndiff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c\nindex 7d96adab4fd..fcc546fb5ae 100644\n--- a/drivers/mtd/spi/spi-nor-ids.c\n+++ b/drivers/mtd/spi/spi-nor-ids.c\n@@ -95,6 +95,11 @@ const struct flash_info spi_nor_ids[] = {\n \t{ INFO(\"en25q64\", 0x1c3017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },\n \t{ INFO(\"en25q128b\", 0x1c3018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },\n \t{ INFO(\"en25qh128\", 0x1c7018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },\n+\t{ INFO(\"en25qx128a\", 0x1c7118, 0, 64 * 1024, 256,\n+\t SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },\n+\t{ INFO(\"en25qh256\", 0x1c7019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },\n+\t{ INFO(\"en25qx256a\", 0x1c7119, 0, 64 * 1024, 512,\n+\t SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },\n \t{ INFO(\"en25s64\", 0x1c3817, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },\n #endif\n #ifdef CONFIG_SPI_FRAM_FUJITSU\ndiff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h\nindex 4eef4ab0488..02fa72fb401 100644\n--- a/include/linux/mtd/spi-nor.h\n+++ b/include/linux/mtd/spi-nor.h\n@@ -33,6 +33,7 @@\n #define SNOR_MFR_SST\t\tCFI_MFR_SST\n #define SNOR_MFR_WINBOND\t0xef /* Also used by some Spansion */\n #define SNOR_MFR_CYPRESS\t0x34\n+#define SNOR_MFR_EON\t\tCFI_MFR_EON\n \n /*\n * Note on opcode nomenclature: some opcodes have a format like\n","prefixes":["2/6"]}