{"id":2229194,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2229194/?format=json","web_url":"http://patchwork.ozlabs.org/project/rtc-linux/patch/20260427214127.406067-2-ynorov@nvidia.com/","project":{"id":9,"url":"http://patchwork.ozlabs.org/api/1.1/projects/9/?format=json","name":"Linux RTC development","link_name":"rtc-linux","list_id":"linux-rtc.vger.kernel.org","list_email":"linux-rtc@vger.kernel.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260427214127.406067-2-ynorov@nvidia.com>","date":"2026-04-27T21:41:18","name":"[v2,1/9] bitfield: add FIELD_GET_SIGNED()","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"2bdfe98d05486f1def27cd568a45d656e4d748f6","submitter":{"id":92516,"url":"http://patchwork.ozlabs.org/api/1.1/people/92516/?format=json","name":"Yury Norov","email":"ynorov@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/rtc-linux/patch/20260427214127.406067-2-ynorov@nvidia.com/mbox/","series":[{"id":501729,"url":"http://patchwork.ozlabs.org/api/1.1/series/501729/?format=json","web_url":"http://patchwork.ozlabs.org/project/rtc-linux/list/?series=501729","date":"2026-04-27T21:41:17","name":"bitfield: add FIELD_GET_SIGNED()","version":2,"mbox":"http://patchwork.ozlabs.org/series/501729/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2229194/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2229194/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-rtc@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=ey1tjxvj;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; 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arc=none"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=PF86IjnLk7u6qiOLwmi5ggjeNCS4nXYc5WQ5CMAQ2Jk=;\n b=ey1tjxvjHWQiS+vTWg0tf1e643NLldxgoDUZNxjP71/sC0tBrq5s/g6VxZft2qTaGD2LU2Wv3JSLunrSyCp/l1wqD/fPsnp/0EzTtInf0WQmdxBh9+9HgIj8eBV63jFDQ7LS+LlSMuH3GPx8xr/vOxEKMUzHaSoCYDN5QdptCWtkWkj7PLMYVhFzn7THAIfgrbhzPq2pCF8DTa3A6G/9ADNGNRaSzbbqpK4dzMzFmc85PAARvh79A0815KNhGFWvYmfFaXGRyBjwey0Fcs1SUfwSv3BFNWk+6c7Zpn1BUf0X3y5ur+Rh4Wbwjvw3XLQq2JZFlmHCWN4erStZrQthTw==","From":"Yury Norov ","To":"Thomas Gleixner , Ingo Molnar ,\n Borislav Petkov , Dave Hansen ,\n \"H. Peter Anvin\" , Andy Lutomirski ,\n Peter Zijlstra , Jonathan Cameron ,\n David Lechner ,\n Johannes Berg ,\n David Laight ,\n =?utf-8?q?Nuno_S=C3=A1?= ,\n Andy Shevchenko , Ping-Ke Shih ,\n Richard Cochran ,\n Andrew Lunn , \"David S. Miller\" ,\n Eric Dumazet , Jakub Kicinski ,\n Paolo Abeni ,\n Alexandre Belloni ,\n Yury Norov ,\n Rasmus Villemoes ,\n Hans de Goede , Linus Walleij ,\n Sakari Ailus ,\n Salah Triki , Achim Gratz ,\n Ben Collins , x86@kernel.org,\n linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org,\n linux-wireless@vger.kernel.org, netdev@vger.kernel.org,\n linux-rtc@vger.kernel.org","Cc":"Yury Norov ","Subject":"[PATCH v2 1/9] bitfield: add FIELD_GET_SIGNED()","Date":"Mon, 27 Apr 2026 17:41:18 -0400","Message-ID":"<20260427214127.406067-2-ynorov@nvidia.com>","X-Mailer":"git-send-email 2.51.0","In-Reply-To":"<20260427214127.406067-1-ynorov@nvidia.com>","References":"<20260427214127.406067-1-ynorov@nvidia.com>","Content-Transfer-Encoding":"8bit","Content-Type":"text/plain","X-ClientProxiedBy":"BN9PR03CA0117.namprd03.prod.outlook.com\n (2603:10b6:408:fd::32) To DS7PR12MB8290.namprd12.prod.outlook.com\n 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mVALzdwk70NZrxvyQWrvj45+MRNCVUc7DjMjFjnQtyKu6n4qIGQz32j/gIe7woVt++3j8FRiUt98ivtAQOHA7wAiKTjl1rPSZi0rfn4cdqqBxI+/6jDeRGlDUZ5Od7Hp9MCVJt4FCzRpzJnM5gFuq2I/guMMkOV9GguFHdJbhZNUPQMFrH+liNS9mGGsm2qTCJEgz0tjG/eq+/cjhp29c/819ULS7V7ikYUW4N5j4aMe68ho4U5ALmebSwTvPvhtOglubRI2xXDEUHDdZHPkuy3IOSasRPS5KflQfAgq2/CKZ4BUWfhCxCz0DMBaLCpooUgwv+BoNDIjaZxhgCr8UoSIGQe9zPF7A8DL5pj6wj2zadgbsHDiPHjZrrKcKS3XuJNtZz6SrmXwYWfUL6QDSW4BlYTY0rOD2zB5GFvP7HqJ9tHv3elIiVmfv4Nq92qWZf1UwCGt4NMf7M05h9NhaqePlf8a+e0hTnlB864bICpSc7Qn0OalgmErrvAKQU14e7qo99V3kfEjWl+5nk8EZAMU7kzhi5rJ/Sg6L59zDEfljhdo9NXJX+GLVW9jgufLQTu+/XCa/hGQD1T+y2ZeaFUZrMfn7mRUYVOl5t0FgWY+FRhwMP74MjJgngmKiEL5kyoU4HnJdsMuEgocR6DjGT3UoodmoHRmBSft+1CBmMI5oMsGnPqq5oj10dPZpmVlsVux/8lffFFh/sPa4h8XFf4dEbEKs6d9x45vnRLk8EMxsO9LOfI15Udg3kjTg73wr5YSTWnCRyQaF45IpacpJa6DDWM6qen+ygfccCiBIOJ06Kxe5HWogSumltTk22ZxtkzzCSPsrsbaehzkeyneZ+d9juJY6mK6EB3zhagLoW62kbfgh+tY2MiHOA/nyrof2jO7CxH/6KxdtwkwGWFbgmblPMvAGQnUnMQl8XWzdcH6jXTo1E1NYfr5JVP3Xn0LJy8b0DX+cYGOmp0YmCiTt+QwvDVUS69g40+lBtkc5wvdJN4XiKIRQ73OGulasm3Xt/skMSx6jskG3s6/9W+gRQLP9Iz6xHU1uvpyCMhRZDttgJcCPurlYfdnZG+yT1MTwPgI2FbYDlyB3T4iGYQdINV4kylUXFkz9hqCJg11ouVBAhP4cjQinYxEi5C+fxBDZUbzBGoy6r9mp69Dkjo8HEkZXKZVt90w8YntAEtcvoBeVkST5Zl0Awv6zkdXBeyASc4Pu9bFqaV7LUnpg22bhxVLzoI3VyyzmQtS1obkJQ4e1sHiTFfVgUVKTQEhGmYdooHj/x6zDXru6W7Q42ETcb0+CtD9Xcy/Ys010Nh0/V2fnRptOuHN2LLfhdoaFEnNo1eOB9Hsw6UyolZFp2/WtSYdNgoAh9ZY+kU8V34GiQn5gGa9EcRTlnSGDuXVSPqtvJ1qak7Olp5OrUwu1LBzNjexyNDyttucwDrRznGFs/EWBc95XRMI6E0KY2kQRbYqMsdXTUeanX/+tcPYkw79Xj2RF+HW2yonfL0CTerNeBNTu/jL7dWLbRBq0lxU5Sr4hsNhjGXnyUapjxNlZSXq/C9zZwatzTLzNGSKSEAIkPSBFoECpNDkt+oJo3lod5LaprMncJxaV1OEYv2SyYIba6AD7stCj8Fume9JfMHeFNtHbjOadw/4WatiuGwp4i8lRDmreW3O/gJdz1uf3NEdf4CJL9S/T0wcHQbJ8bYk+6IMOvDdIQVqYdA13qhiCsCN9UObY/eSNISgs7mX8+LfCyEL11ROUzLKVxv24yKM/jS6FuMbVVwjrbhsjzZ1m7Gu","X-OriginatorOrg":"Nvidia.com","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n b6dc1d92-cfdd-483a-2fd0-08dea4a5c736","X-MS-Exchange-CrossTenant-AuthSource":"DS7PR12MB8290.namprd12.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Internal","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"27 Apr 2026 21:41:45.9215\n (UTC)","X-MS-Exchange-CrossTenant-FromEntityHeader":"Hosted","X-MS-Exchange-CrossTenant-Id":"43083d15-7273-40c1-b7db-39efd9ccc17a","X-MS-Exchange-CrossTenant-MailboxType":"HOSTED","X-MS-Exchange-CrossTenant-UserPrincipalName":"\n HtginAblZ4qsYaPt8R0D+8pQWviedceo0YGFcI7ONgObNlmdsofNqYU5zj8QU+2MT11J89x8hZedpxwtrv8IDQ==","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"LV9PR12MB9829"},"content":"The bitfields are designed in assumption that fields contain unsigned\ninteger values, thus extracting the values from the field implies\nzero-extending.\n\nSome drivers need to sign-extend their fields, and currently do it like:\n\n\tdc_re += sign_extend32(FIELD_GET(0xfff000, tmp), 11);\n\tdc_im += sign_extend32(FIELD_GET(0xfff, tmp), 11);\n\nIt's error-prone because it relies on user to provide the correct\nindex of the most significant bit and proper 32 vs 64 function flavor.\n\nThus, introduce a FIELD_GET_SIGNED(). With the new API, the above\nsnippet turns into the more convenient:\n\n\tdc_re += FIELD_GET_SIGNED(0xfff000, tmp);\n\tdc_im += FIELD_GET_SIGNED(0xfff, tmp);\n\nIt compiles (on x86_64) into just a couple instructions: shl and sar.\nWhen the mask includes MSB, the '<< __builtin_clzll(mask)' part becomes\na NOP, and the compiler only emits a single sar:\n\n long long foo(long long reg)\n {\n 10: f3 0f 1e fa endbr64\n return FIELD_GET_SIGNED(GENMASK_ULL(63, 60), reg);\n 14: 48 89 f8 mov %rdi,%rax\n 17: 48 c1 f8 3c sar $0x3c,%rax\n }\n\n32-bit code generation is equally well. On arm32:\n\n long long foo(long long reg)\n {\n return FIELD_GET_SIGNED(0x00f00000ULL, reg);\n }\n\ngenerates:\n\n foo(long long):\n lsls r1, r0, #8\n asrs r0, r1, #28\n asrs r1, r1, #31\n bx lr\n\nSigned-off-by: Yury Norov \n---\n include/linux/bitfield.h | 16 ++++++++++++++++\n 1 file changed, 16 insertions(+)","diff":"diff --git a/include/linux/bitfield.h b/include/linux/bitfield.h\nindex 54aeeef1f0ec..cd44013281c7 100644\n--- a/include/linux/bitfield.h\n+++ b/include/linux/bitfield.h\n@@ -178,6 +178,22 @@\n \t\t__FIELD_GET(_mask, _reg, \"FIELD_GET: \");\t\t\\\n \t})\n \n+/**\n+ * FIELD_GET_SIGNED() - extract a signed bitfield element\n+ * @mask: shifted mask defining the field's length and position\n+ * @reg: value of entire bitfield\n+ *\n+ * Returns the sign-extended field specified by @_mask from the\n+ * bitfield passed in as @_reg by masking and shifting it down.\n+ */\n+#define FIELD_GET_SIGNED(mask, reg)\t\t\t\t\t\\\n+\t({\t\t\t\t\t\t\t\t\\\n+\t\t__BF_FIELD_CHECK(mask, reg, 0U, \"FIELD_GET_SIGNED: \");\t\\\n+\t\t ((__signed_scalar_typeof(mask))\t\t\t\\\n+\t\t (((long long)(reg) << __builtin_clzll(mask)) >>\t\\\n+\t\t (__builtin_clzll(mask) + __builtin_ctzll(mask))));\t\\\n+\t})\n+\n /**\n * FIELD_MODIFY() - modify a bitfield element\n * @_mask: shifted mask defining the field's length and position\n","prefixes":["v2","1/9"]}