{"id":2228957,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2228957/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/patch/2a921c9d-c312-4ccd-afca-d97813432403@oss.qualcomm.com/","project":{"id":17,"url":"http://patchwork.ozlabs.org/api/1.1/projects/17/?format=json","name":"GNU Compiler Collection","link_name":"gcc","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<2a921c9d-c312-4ccd-afca-d97813432403@oss.qualcomm.com>","date":"2026-04-27T14:52:58","name":"[to-be-committed,V3,PR,target/121268] ","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"f2142626a7c19e6a183de314489526e33d670acd","submitter":{"id":92310,"url":"http://patchwork.ozlabs.org/api/1.1/people/92310/?format=json","name":"Jeffrey Law","email":"jeffrey.law@oss.qualcomm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/gcc/patch/2a921c9d-c312-4ccd-afca-d97813432403@oss.qualcomm.com/mbox/","series":[{"id":501666,"url":"http://patchwork.ozlabs.org/api/1.1/series/501666/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/list/?series=501666","date":"2026-04-27T14:52:58","name":"[to-be-committed,V3,PR,target/121268] ","version":3,"mbox":"http://patchwork.ozlabs.org/series/501666/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2228957/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2228957/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=aUalK9UP;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=eTPPj0Zo;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; 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boundary=\"------------b9T0MgajfPqaQ6oJDdTnv9fx\"","Message-ID":"<2a921c9d-c312-4ccd-afca-d97813432403@oss.qualcomm.com>","Date":"Mon, 27 Apr 2026 08:52:58 -0600","MIME-Version":"1.0","User-Agent":"Mozilla Thunderbird","Content-Language":"en-US","To":"'GCC Patches' ","From":"Jeffrey Law ","Subject":"[to-be-committed][V3][PR target/121268]","X-Proofpoint-ORIG-GUID":"zNpzMvzCxnwmqJHMoPMaiLmHnrdFewgR","X-Authority-Analysis":"v=2.4 cv=Xba5Co55 c=1 sm=1 tr=0 ts=69ef784e cx=c_pps\n a=kVLUcbK0zfr7ocalXnG1qA==:117 a=asGLMfRmzhnGNxaIYohjRg==:17\n a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=r77TgQKjGQsHNAKrUKIA:9\n a=NeGlvrA1Pa8BGdrBpgsA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10\n a=lJZwUOCYSaWFdIi53IMA:9 a=yVOC4zewY2VDDqEJ:21 a=_W_S_7VecoQA:10\n a=lHyQXsNW_jjFoZG7ryoA:9 a=B2y7HmGcmWMA:10 a=vr4QvYf-bLy2KjpDp97w:22","X-Proofpoint-GUID":"zNpzMvzCxnwmqJHMoPMaiLmHnrdFewgR","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNDI3MDE1NyBTYWx0ZWRfX89jRRKVyeBPT\n UQFuJfXhffFz+OtjLUO2O4GKWUKkr/ggxIbUT0Gl/qi9Ia9fzwlSqrcixGmwuVAXbP5+8AhmJ6M\n uzvXkDjETqb3W6B2nc05HeOozMYXf4xN7S4+QSYuOq244AYz5wTknLQ8LpRzVPGKE9xn0QOcaC1\n 78THksQtjSumluIYTTxWCDx3VT/TV4TWgJQdX61tw+APzOKpoqrrG2sl7DnnV8Nl+ErTzxSTglB\n VjHNJLO+IceSe/8y3PazzwSpyKtgoulKLOHILEvN5ksAlUrPFWlB7jMu2y1p1lgy8/r9b6jo8KY\n w5uwJUN/I8DMMN8Q4mmbOPDufRfV85QXH8xeVA1FzAHLJLQJWjHHxDcDSeWEI9QTDKFSYa0ZKS2\n UTURO/QJCB50iK279tKSESIV/poomdSdv13igHektEkJuMFSYXhKR9PZQNejw450bSTktj0+IkY\n YNEnbHU0aos6cCxOgeA==","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-27_04,2026-04-21_02,2025-10-01_01","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n priorityscore=1501 bulkscore=0 suspectscore=0 phishscore=0 adultscore=0\n impostorscore=0 lowpriorityscore=0 spamscore=0 clxscore=1015 malwarescore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604270157","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org"},"content":"One more time!  Same pattern, just context adjustment in the patch.\n\n--\n\n\nSo if we have something like (and (not X) (not Y)) where X or Y is a \nsimple register and the other is possibly more complex, but \nimplementable with a single instruction, we want to split at the the \ncomplex expression. Let's say it's Y above.  We want to generate\n\n(set (temp) (not Y))\n(set (dest) (and (not (X) (temp))\n\nThe most interesting cases for Y exploit the ~x = -x + 1 identity or (x \n& -x) - 1 = (x - 1) & ~x\n\nIf we take two functions from the PR:\n\nunsigned int f1(unsigned int x)\n{\n return ~(x | -x);\n}\n\nunsigned int f3(unsigned int x)\n{\n return (x & -x) - 1;\n}\n\nCurrently generates this on rv64:\n\n\nf1:\n         negw    a5,a0\n         or      a0,a5,a0\n         not     a0,a0\n         ret\n\nf3:\n         negw    a5,a0\n         and     a0,a5,a0\n         addiw   a0,a0,-1\n         ret\n\n\nAfter this patch we generate:\n\nf1:\n         addiw   a5,a0,-1\n         andn    a0,a5,a0\n         ret\n\nf3:\n         addiw   a5,a0,-1\n         andn    a0,a5,a0\n         ret\n\nI considered doing these in simplify-rtx.  My biggest worry is \nover-fitting to the way the RISC-V port expresses the \"w\" form \ninstructions.  So I stuck with a target specific solution.\n\n\nIt's just a few 3->2 splitters.   The bulk of the patch has been in my \ntester for a while, but the last pattern is new after I did some \nexperimentation on rv32 to make sure it's generating sensible code too.  \nThe runs in my tester have all been without regressions. Obviously I'll \nbe waiting on the pre-commit CI system to render a verdict.","diff":"diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md\nindex 45881994f3a..1ca9f82b363 100644\n--- a/gcc/config/riscv/bitmanip.md\n+++ b/gcc/config/riscv/bitmanip.md\n@@ -927,7 +927,7 @@ (define_insn \"*bext\"\n \n ;; We do not define SHIFT_COUNT_TRUNCATED, so we have to have variants\n ;; that mask/extend the count if we want to eliminate those ops\n-;; \n+;;\n ;; We could (in theory) use GPR for the various modes, but I haven't\n ;; seen those cases appear in practice. Without a testcase I've\n ;; elected to keep the modes X which is easy to reason about.\n@@ -1368,3 +1368,61 @@ (define_split\n (set (match_dup 0) (zero_extract:X (match_dup 3)\n \t\t\t\t (const_int 1)\n \t\t\t\t (zero_extend:X (match_dup 2))))])\n+\n+;; If we have (and (not X) (not Y)), and we can implement one of those NOT\n+;; expressions as a single insn, then do so as that will allow using andn.\n+;; In this case we exploit ~(-x) == x - 1. Two versions as we can reverse\n+;; the operands of the AND.\n+(define_split\n+ [(set (match_operand:DI 0 \"register_operand\")\n+\t(and:DI\n+\t (not:DI\n+\t (sign_extend:DI (neg:SI (match_operand:SI 1 \"register_operand\"))))\n+\t (not:DI (match_operand:DI 2 \"register_operand\"))))\n+ (clobber (match_operand:DI 3 \"register_operand\"))]\n+ \"TARGET_64BIT && TARGET_ZBB\"\n+ [(set (match_dup 3) (sign_extend:DI (plus:SI (match_dup 1) (const_int -1))))\n+ (set (match_dup 0) (and:DI (not:DI (match_dup 2)) (match_dup 3)))])\n+\n+(define_split\n+ [(set (match_operand:DI 0 \"register_operand\")\n+\t(and:DI\n+\t (not:DI (match_operand:DI 1 \"register_operand\"))\n+\t (not:DI\n+\t (sign_extend:DI (neg:SI (match_operand:SI 2 \"register_operand\"))))))\n+ (clobber (match_operand:DI 3 \"register_operand\"))]\n+ \"TARGET_64BIT && TARGET_ZBB\"\n+ [(set (match_dup 3) (sign_extend:DI (plus:SI (match_dup 2) (const_int -1))))\n+ (set (match_dup 0) (and:DI (not:DI (match_dup 1)) (match_dup 3)))])\n+\n+;; Another variant, this time exploiting (x & -x) - 1 == (x - 1) & ~x\n+(define_split\n+ [(set (match_operand:DI 0 \"register_operand\")\n+\t(sign_extend:DI\n+\t (plus:SI\n+\t (subreg:SI (and:DI\n+\t\t (subreg:DI (neg:SI\n+\t\t\t\t (match_operand:SI 1 \"register_operand\")) 0)\n+\t\t (match_operand:DI 2 \"register_operand\")) 0)\n+\t (const_int -1))))\n+ (clobber (match_operand:DI 3 \"register_operand\"))]\n+ \"(TARGET_64BIT\n+ && TARGET_ZBB\n+ && (REG_P (operands[2]) && SUBREG_P (operands[1])\n+\t ? REGNO (operands[2]) == REGNO (SUBREG_REG (operands[1]))\n+\t : REG_P (operands[1]) && SUBREG_P (operands[2])\n+\t ? (REGNO (SUBREG_REG (operands[2])) == REGNO (operands[1])) : 0))\"\n+ [(set (match_dup 3) (sign_extend:DI (plus:SI (match_dup 1) (const_int -1))))\n+ (set (match_dup 0) (and:DI (not:DI (match_dup 2)) (match_dup 3)))])\n+\n+;; Another exploiting (x & -x) -1 == (x - 1) & ~x\n+(define_split\n+ [(set (match_operand:X 0 \"register_operand\")\n+\t(plus:X (and:X (neg:X (match_operand:X 1 \"register_operand\"))\n+\t\t (match_dup 1))\n+\t\t(const_int -1)))\n+ (clobber (match_operand:X 2 \"register_operand\"))]\n+ \"TARGET_ZBB\"\n+ [(set (match_dup 2) (plus:X (match_dup 1) (const_int -1)))\n+ (set (match_dup 0) (and:X (not:X (match_dup 1)) (match_dup 2)))])\n+\ndiff --git a/gcc/testsuite/gcc.target/riscv/pr121268.c b/gcc/testsuite/gcc.target/riscv/pr121268.c\nnew file mode 100644\nindex 00000000000..d79f444d2f8\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/pr121268.c\n@@ -0,0 +1,39 @@\n+/* { dg-do compile } */\n+/* { dg-additional-options \"-march=rv64gcb_zicond -mabi=lp64d\" { target rv64 } } */\n+/* { dg-additional-options \"-march=rv32gcb_zicond -mabi=ilp32\" { target rv32 } } */\n+/* { dg-skip-if \"\" { *-*-* } { \"-O0\" \"-Og\" } } */\n+\n+#define F1(TYPE, NAME) TYPE f1##NAME (TYPE x) { return ~(x | -x); }\n+#define F2(TYPE, NAME) TYPE f2##NAME (TYPE x) { return ~x & (x - 1); }\n+#define F3(TYPE, NAME) TYPE f3##NAME (TYPE x) { return (x & -x) - 1; }\n+\n+F1 (unsigned char, uc)\n+F1 (unsigned short, us)\n+F1 (unsigned int, ui)\n+F1 (unsigned long, ul)\n+F1 (signed char, sc)\n+F1 (signed short, ss)\n+F1 (signed int, si)\n+F1 (signed long, sl)\n+\n+F2 (unsigned char, uc)\n+F2 (unsigned short, us)\n+F2 (unsigned int, ui)\n+F2 (unsigned long, ul)\n+F2 (signed char, sc)\n+F2 (signed short, ss)\n+F2 (signed int, si)\n+F2 (signed long, sl)\n+\n+F3 (unsigned char, uc)\n+F3 (unsigned short, us)\n+F3 (unsigned int, ui)\n+F3 (unsigned long, ul)\n+F3 (signed char, sc)\n+F3 (signed short, ss)\n+F3 (signed int, si)\n+F3 (signed long, sl)\n+\n+/* We match addi and addiw here on purpose. */\n+/* { dg-final { scan-assembler-times \"addi\" 24 } } */\n+/* { dg-final { scan-assembler-times \"andn\\t\" 24 } } */\n","prefixes":["to-be-committed","V3","PR","target/121268"]}