{"id":2228893,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2228893/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427124738.966578-23-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260427124738.966578-23-peter.maydell@linaro.org>","date":"2026-04-27T12:46:56","name":"[PULL,22/63] target/arm: Replace MO_TE -> mo_endian() for MVE helpers","commit_ref":null,"pull_url":null,"state":"not-applicable","archived":false,"hash":"71fe49938b09e2a51d4e1b442428d0d01ff6943e","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/1.1/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427124738.966578-23-peter.maydell@linaro.org/mbox/","series":[{"id":501642,"url":"http://patchwork.ozlabs.org/api/1.1/series/501642/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501642","date":"2026-04-27T12:46:34","name":"[PULL,01/63] docs/system: add FEAT_AA32 and FEAT_AA64 to emulation list","version":1,"mbox":"http://patchwork.ozlabs.org/series/501642/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2228893/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2228893/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=WpzsQy8Y;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g43cB3Kkpz1yHX\n\tfor ; Mon, 27 Apr 2026 23:01:46 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wHLRO-0003qx-ON; Mon, 27 Apr 2026 08:52:05 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wHLNc-00080l-Rb\n for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:16 -0400","from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wHLNZ-0005eC-D6\n for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:04 -0400","by mail-wm1-x32a.google.com with SMTP id\n 5b1f17b1804b1-48984d29fe3so122375705e9.0\n for ; Mon, 27 Apr 2026 05:47:59 -0700 (PDT)","from lanath.. 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charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::32a;\n envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Philippe Mathieu-Daudé \n\nSigned-off-by: Philippe Mathieu-Daudé \nReviewed-by: Richard Henderson \nMessage-id: 20260414005348.4767-7-philmd@linaro.org\nSigned-off-by: Peter Maydell \n---\n target/arm/tcg/mve_helper.c | 47 +++++++++++++++++++++++--------------\n 1 file changed, 30 insertions(+), 17 deletions(-)","diff":"diff --git a/target/arm/tcg/mve_helper.c b/target/arm/tcg/mve_helper.c\nindex a5a23c9705..64ab804abc 100644\n--- a/target/arm/tcg/mve_helper.c\n+++ b/target/arm/tcg/mve_helper.c\n@@ -160,7 +160,7 @@ static void mve_advance_vpt(CPUARMState *env)\n uint16_t eci_mask = mve_eci_mask(env); \\\n unsigned b, e; \\\n int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \\\n- MemOpIdx oi = make_memop_idx(MO_TE | MFLAG | MO_ALIGN, \\\n+ MemOpIdx oi = make_memop_idx(mo_endian(env) | MFLAG | MO_ALIGN, \\\n mmu_idx); \\\n /* \\\n * R_SXTM allows the dest reg to become UNKNOWN for abandoned \\\n@@ -184,7 +184,7 @@ static void mve_advance_vpt(CPUARMState *env)\n uint16_t mask = mve_element_mask(env); \\\n unsigned b, e; \\\n int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \\\n- MemOpIdx oi = make_memop_idx(MO_TE | MFLAG | MO_ALIGN, \\\n+ MemOpIdx oi = make_memop_idx(mo_endian(env) | MFLAG | MO_ALIGN, \\\n mmu_idx); \\\n for (b = 0, e = 0; b < 16; b += ESIZE, e++) { \\\n if (mask & (1 << b)) { \\\n@@ -235,7 +235,7 @@ DO_VSTR(vstrh_w, MO_UW, 2, stw, 4, int32_t)\n unsigned e; \\\n uint32_t addr; \\\n int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \\\n- MemOpIdx oi = make_memop_idx(MO_TE | MFLAG | MO_ALIGN, \\\n+ MemOpIdx oi = make_memop_idx(mo_endian(env) | MFLAG | MO_ALIGN, \\\n mmu_idx); \\\n for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE, eci_mask >>= ESIZE) { \\\n if (!(eci_mask & 1)) { \\\n@@ -263,7 +263,7 @@ DO_VSTR(vstrh_w, MO_UW, 2, stw, 4, int32_t)\n unsigned e; \\\n uint32_t addr; \\\n int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \\\n- MemOpIdx oi = make_memop_idx(MO_TE | MFLAG | MO_ALIGN, \\\n+ MemOpIdx oi = make_memop_idx(mo_endian(env) | MFLAG | MO_ALIGN, \\\n mmu_idx); \\\n for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE, eci_mask >>= ESIZE) { \\\n if (!(eci_mask & 1)) { \\\n@@ -326,7 +326,8 @@ DO_VSTR(vstrh_w, MO_UW, 2, stw, 4, int32_t)\n unsigned e; \\\n uint32_t addr; \\\n int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \\\n- MemOpIdx oi = make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\\\n+ MemOpIdx oi = make_memop_idx(mo_endian(env) | MO_UL | MO_ALIGN, \\\n+ mmu_idx); \\\n for (e = 0; e < 16 / 4; e++, mask >>= 4, eci_mask >>= 4) { \\\n if (!(eci_mask & 1)) { \\\n continue; \\\n@@ -413,7 +414,8 @@ DO_VSTR64_SG(vstrd_sg_wb_ud, ADDR_ADD, true)\n static const uint8_t off[4] = { O1, O2, O3, O4 }; \\\n uint32_t addr, data; \\\n int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \\\n- MemOpIdx oi = make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\\\n+ MemOpIdx oi = make_memop_idx(mo_endian(env) | MO_UL | MO_ALIGN, \\\n+ mmu_idx); \\\n for (beat = 0; beat < 4; beat++, mask >>= 4) { \\\n if ((mask & 1) == 0) { \\\n /* ECI says skip this beat */ \\\n@@ -439,7 +441,8 @@ DO_VSTR64_SG(vstrd_sg_wb_ud, ADDR_ADD, true)\n int y; /* y counts 0 2 0 2 */ \\\n uint16_t *qd; \\\n int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \\\n- MemOpIdx oi = make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\\\n+ MemOpIdx oi = make_memop_idx(mo_endian(env) | MO_UL | MO_ALIGN, \\\n+ mmu_idx); \\\n for (beat = 0, y = 0; beat < 4; beat++, mask >>= 4, y ^= 2) { \\\n if ((mask & 1) == 0) { \\\n /* ECI says skip this beat */ \\\n@@ -466,7 +469,8 @@ DO_VSTR64_SG(vstrd_sg_wb_ud, ADDR_ADD, true)\n uint32_t *qd; \\\n int y; \\\n int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \\\n- MemOpIdx oi = make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\\\n+ MemOpIdx oi = make_memop_idx(mo_endian(env) | MO_UL | MO_ALIGN, \\\n+ mmu_idx); \\\n for (beat = 0; beat < 4; beat++, mask >>= 4) { \\\n if ((mask & 1) == 0) { \\\n /* ECI says skip this beat */ \\\n@@ -505,7 +509,8 @@ DO_VLD4W(vld43w, 6, 7, 8, 9)\n uint32_t addr, data; \\\n uint8_t *qd; \\\n int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \\\n- MemOpIdx oi = make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\\\n+ MemOpIdx oi = make_memop_idx(mo_endian(env) | MO_UL | MO_ALIGN, \\\n+ mmu_idx); \\\n for (beat = 0; beat < 4; beat++, mask >>= 4) { \\\n if ((mask & 1) == 0) { \\\n /* ECI says skip this beat */ \\\n@@ -531,7 +536,8 @@ DO_VLD4W(vld43w, 6, 7, 8, 9)\n int e; \\\n uint16_t *qd; \\\n int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \\\n- MemOpIdx oi = make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\\\n+ MemOpIdx oi = make_memop_idx(mo_endian(env) | MO_UL | MO_ALIGN, \\\n+ mmu_idx); \\\n for (beat = 0; beat < 4; beat++, mask >>= 4) { \\\n if ((mask & 1) == 0) { \\\n /* ECI says skip this beat */ \\\n@@ -556,7 +562,8 @@ DO_VLD4W(vld43w, 6, 7, 8, 9)\n uint32_t addr, data; \\\n uint32_t *qd; \\\n int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \\\n- MemOpIdx oi = make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\\\n+ MemOpIdx oi = make_memop_idx(mo_endian(env) | MO_UL | MO_ALIGN, \\\n+ mmu_idx); \\\n for (beat = 0; beat < 4; beat++, mask >>= 4) { \\\n if ((mask & 1) == 0) { \\\n /* ECI says skip this beat */ \\\n@@ -587,7 +594,8 @@ DO_VLD2W(vld21w, 8, 12, 16, 20)\n static const uint8_t off[4] = { O1, O2, O3, O4 }; \\\n uint32_t addr, data; \\\n int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \\\n- MemOpIdx oi = make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\\\n+ MemOpIdx oi = make_memop_idx(mo_endian(env) | MO_UL | MO_ALIGN, \\\n+ mmu_idx); \\\n for (beat = 0; beat < 4; beat++, mask >>= 4) { \\\n if ((mask & 1) == 0) { \\\n /* ECI says skip this beat */ \\\n@@ -614,7 +622,8 @@ DO_VLD2W(vld21w, 8, 12, 16, 20)\n int y; /* y counts 0 2 0 2 */ \\\n uint16_t *qd; \\\n int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \\\n- MemOpIdx oi = make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\\\n+ MemOpIdx oi = make_memop_idx(mo_endian(env) | MO_UL | MO_ALIGN, \\\n+ mmu_idx); \\\n for (beat = 0, y = 0; beat < 4; beat++, mask >>= 4, y ^= 2) { \\\n if ((mask & 1) == 0) { \\\n /* ECI says skip this beat */ \\\n@@ -640,7 +649,8 @@ DO_VLD2W(vld21w, 8, 12, 16, 20)\n uint32_t *qd; \\\n int y; \\\n int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \\\n- MemOpIdx oi = make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\\\n+ MemOpIdx oi = make_memop_idx(mo_endian(env) | MO_UL | MO_ALIGN, \\\n+ mmu_idx); \\\n for (beat = 0; beat < 4; beat++, mask >>= 4) { \\\n if ((mask & 1) == 0) { \\\n /* ECI says skip this beat */ \\\n@@ -679,7 +689,8 @@ DO_VST4W(vst43w, 6, 7, 8, 9)\n uint32_t addr, data; \\\n uint8_t *qd; \\\n int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \\\n- MemOpIdx oi = make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\\\n+ MemOpIdx oi = make_memop_idx(mo_endian(env) | MO_UL | MO_ALIGN, \\\n+ mmu_idx); \\\n for (beat = 0; beat < 4; beat++, mask >>= 4) { \\\n if ((mask & 1) == 0) { \\\n /* ECI says skip this beat */ \\\n@@ -706,7 +717,8 @@ DO_VST4W(vst43w, 6, 7, 8, 9)\n int e; \\\n uint16_t *qd; \\\n int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \\\n- MemOpIdx oi = make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\\\n+ MemOpIdx oi = make_memop_idx(mo_endian(env) | MO_UL | MO_ALIGN, \\\n+ mmu_idx); \\\n for (beat = 0; beat < 4; beat++, mask >>= 4) { \\\n if ((mask & 1) == 0) { \\\n /* ECI says skip this beat */ \\\n@@ -732,7 +744,8 @@ DO_VST4W(vst43w, 6, 7, 8, 9)\n uint32_t addr, data; \\\n uint32_t *qd; \\\n int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \\\n- MemOpIdx oi = make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\\\n+ MemOpIdx oi = make_memop_idx(mo_endian(env) | MO_UL | MO_ALIGN, \\\n+ mmu_idx); \\\n for (beat = 0; beat < 4; beat++, mask >>= 4) { \\\n if ((mask & 1) == 0) { \\\n /* ECI says skip this beat */ \\\n","prefixes":["PULL","22/63"]}