{"id":2228879,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2228879/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427124738.966578-42-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260427124738.966578-42-peter.maydell@linaro.org>","date":"2026-04-27T12:47:15","name":"[PULL,41/63] target/arm: migrate basic syndrome helpers to registerfields","commit_ref":null,"pull_url":null,"state":"not-applicable","archived":false,"hash":"f9342eadedf3a8f3edc93775d672250847f361b0","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/1.1/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427124738.966578-42-peter.maydell@linaro.org/mbox/","series":[{"id":501642,"url":"http://patchwork.ozlabs.org/api/1.1/series/501642/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501642","date":"2026-04-27T12:46:34","name":"[PULL,01/63] docs/system: add FEAT_AA32 and FEAT_AA64 to emulation list","version":1,"mbox":"http://patchwork.ozlabs.org/series/501642/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2228879/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2228879/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=nRmmEamj;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g43Y64x3lz1yJX\n\tfor ; Mon, 27 Apr 2026 22:59:06 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wHLUf-0000TP-Tu; Mon, 27 Apr 2026 08:55:22 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wHLO4-0008BG-OW\n for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:35 -0400","from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wHLNr-0005iF-OH\n for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:27 -0400","by mail-wm1-x32f.google.com with SMTP id\n 5b1f17b1804b1-488b3f8fa2bso103395805e9.1\n for ; Mon, 27 Apr 2026 05:48:19 -0700 (PDT)","from lanath.. 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[81.2.115.145])\n by smtp.gmail.com with ESMTPSA id\n 5b1f17b1804b1-488ffc5e3f4sm448974115e9.2.2026.04.27.05.48.16\n for \n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Mon, 27 Apr 2026 05:48:16 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=linaro.org; s=google; t=1777294098; x=1777898898; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:to:from:from:to:cc:subject:date:message-id\n :reply-to; bh=YcYVYYNIRSP1snD5TdIYSPjOwpX5L7NMhYaBvEW9/ZM=;\n b=nRmmEamjySujWYaZNUHRrIEyHD5H0pmhkgx4W5S3I01EVUtaCfPxsWDWsYL0i9ZU5v\n 6AkJHUtlrI3eYpvMgOV/9xObp9eg2xVAfpLbdHCN8dhVTjrDxUT899y7ntt1Es1Fs1zI\n /hHuzEHHgBkSR05Gc5/xNx88/6ylKmiA3XdEW1vayWfZERpLVGKxwsByjKUz13E1MJ0H\n Vt0zE0E4p8V+2YmfKqWgcTkqM3ufK7OtkKn6V088BI/9Rnb/LX54B+0Ia3x4UYOq9Wwu\n ui0Qvuz5XZZuYww4d/Rbgwydhn/bdyRlbjatyOSlrlb/15wIpAgQehSmh2dmr2UYwIvR\n 26qA==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1777294098; x=1777898898;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to\n :cc:subject:date:message-id:reply-to;\n bh=YcYVYYNIRSP1snD5TdIYSPjOwpX5L7NMhYaBvEW9/ZM=;\n b=TYxupQW4IrnGitr3uc7/K96mvTy/u7MCCKXz7gx9gY+Q82Fd53YiM4mMz9MC2/2zoV\n 44xNlezRJZYYws2azfRSPpt3gN4+2dqdowYgN5dZvCsRVGCYeMDQKTcGcSpdsxpDiSo+\n bIemaNnorAN7AjGS2fHdso3/5cEHygYi3O3eYb9E77sCidULR1OHcZulbWMWZD9yREKo\n Ph39PxHTfSGyqjCPO1O79/rXzaSx7e4IF8RxHrX8C9Fi1n+YujdPJ/lyRweYAcrxmbIM\n oh0OH6JqAmUC5NCUpzbYzWQrahaQoamq5t3D8b4osW3ipSUOP12d5VVQ66x9fI6lKnnS\n TjtQ==","X-Gm-Message-State":"AOJu0Yxlxh4eVg7iXd6aBytwX1yf3jR7SjHkCZu8yeUDYpmX/4hOmU34\n KNWIfHQAQ5Mar0VSVviPiZH+rvwIXM3o+GHKjwJWKDHknpzHCT53GeL5TBX+LVdzep4jDItyukh\n hamsP","X-Gm-Gg":"AeBDieuVNPecX3tVFCmweYsGPa7FB0Z8/XY0uBw24J9b2vhIh7EvJIP7viNJxnWb10O\n wR5Mv13LZ8BX1A31EAphCdhZtF/NZXkDNRDMNIj7pCz76uqxDiHxxNtxj46XeVeQkC2euI1B8wS\n 5xSPGVVbwvLHWIXDlhIqj+6WtqmCzXNcCQzA6WAA8NYDKWc2xG5d7R0oImK2Q4wYCEcDuG18No4\n YRECZRU8poLY7of3dolhfv1ooWGPYMX6gAoRzChEaH3G173cqkkqb6aadsR/G1ba7K0WMrZlKoR\n TPwzKK1DTr9j4W4PN022O1z06RtJUGUWCG5tmUtvqE39yS9JrW0Pt7JKKkv6bX+/EO52oMuEcAS\n rSk+DJNl8OGepZEQ5FZ3d2pnAHre1Dxoj/u6Fqfj+9Q7vWQdzj9+cLAk6NHEy50WmvkDQ0ruQHE\n yHCJyboM8MKquiIY+mc4Rk/xY1fB3fsQc7gEUUYVQBt/bCpe9O/lNDV7iZ2wvR0R009noYpILeM\n 5DI9J9/U8vGlaAY2Lvo1kyMyUcQn/IA20uTu437cA==","X-Received":"by 2002:a05:600c:1d05:b0:489:1baf:8c03 with SMTP id\n 5b1f17b1804b1-4891baf8d2cmr441990475e9.11.1777294097635;\n Mon, 27 Apr 2026 05:48:17 -0700 (PDT)","From":"Peter Maydell ","To":"qemu-devel@nongnu.org","Subject":"[PULL 41/63] target/arm: migrate basic syndrome helpers to\n registerfields","Date":"Mon, 27 Apr 2026 13:47:15 +0100","Message-ID":"<20260427124738.966578-42-peter.maydell@linaro.org>","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"<20260427124738.966578-1-peter.maydell@linaro.org>","References":"<20260427124738.966578-1-peter.maydell@linaro.org>","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::32f;\n envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Alex Bennée \n\nWe have a registerfields interface which we can use for defining\nfields alongside helpers to access them. Define the basic syndrome\nlayout and convert the helpers that take the imm16 data directly.\n\nReviewed-by: Richard Henderson \nSigned-off-by: Alex Bennée \nMessage-id: 20260422125250.1303100-2-alex.bennee@linaro.org\nSigned-off-by: Peter Maydell \n---\n target/arm/syndrome.h | 75 ++++++++++++++++++++++++++++++++-----------\n 1 file changed, 57 insertions(+), 18 deletions(-)","diff":"diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h\nindex bff61f052c..517fb2368b 100644\n--- a/target/arm/syndrome.h\n+++ b/target/arm/syndrome.h\n@@ -25,7 +25,7 @@\n #ifndef TARGET_ARM_SYNDROME_H\n #define TARGET_ARM_SYNDROME_H\n \n-#include \"qemu/bitops.h\"\n+#include \"hw/core/registerfields.h\"\n \n /* Valid Syndrome Register EC field values */\n enum arm_exception_class {\n@@ -76,6 +76,11 @@ enum arm_exception_class {\n EC_AA64_BKPT = 0x3c,\n };\n \n+/* Generic syndrome encoding layout for HSR and lower 32 bits of ESR_EL2 */\n+FIELD(SYNDROME, EC, 26, 6)\n+FIELD(SYNDROME, IL, 25, 1)\n+FIELD(SYNDROME, ISS, 0, 25)\n+\n typedef enum {\n SME_ET_AccessTrap,\n SME_ET_Streaming,\n@@ -113,12 +118,12 @@ typedef enum {\n \n static inline uint32_t syn_get_ec(uint32_t syn)\n {\n- return syn >> ARM_EL_EC_SHIFT;\n+ return FIELD_EX32(syn, SYNDROME, EC);\n }\n \n static inline uint32_t syn_set_ec(uint32_t syn, uint32_t ec)\n {\n- return deposit32(syn, ARM_EL_EC_SHIFT, ARM_EL_EC_LENGTH, ec);\n+ return FIELD_DP32(syn, SYNDROME, EC, ec);\n }\n \n /*\n@@ -133,49 +138,74 @@ static inline uint32_t syn_set_ec(uint32_t syn, uint32_t ec)\n */\n static inline uint32_t syn_uncategorized(void)\n {\n- return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL;\n+ uint32_t res = syn_set_ec(0, EC_UNCATEGORIZED);\n+ res = FIELD_DP32(res, SYNDROME, IL, 1);\n+ return res;\n }\n \n+FIELD(ISS_IMM16, IMM16, 0, 16)\n+\n static inline uint32_t syn_aa64_svc(uint32_t imm16)\n {\n- return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);\n+ uint32_t res = syn_set_ec(0, EC_AA64_SVC);\n+ res = FIELD_DP32(res, SYNDROME, IL, 1);\n+ res = FIELD_DP32(res, ISS_IMM16, IMM16, imm16);\n+ return res;\n }\n \n static inline uint32_t syn_aa64_hvc(uint32_t imm16)\n {\n- return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);\n+ uint32_t res = syn_set_ec(0, EC_AA64_HVC);\n+ res = FIELD_DP32(res, SYNDROME, IL, 1);\n+ res = FIELD_DP32(res, ISS_IMM16, IMM16, imm16);\n+ return res;\n }\n \n static inline uint32_t syn_aa64_smc(uint32_t imm16)\n {\n- return (EC_AA64_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);\n+ uint32_t res = syn_set_ec(0, EC_AA64_SMC);\n+ res = FIELD_DP32(res, SYNDROME, IL, 1);\n+ res = FIELD_DP32(res, ISS_IMM16, IMM16, imm16);\n+ return res;\n }\n \n static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_16bit)\n {\n- return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff)\n- | (is_16bit ? 0 : ARM_EL_IL);\n+ uint32_t res = syn_set_ec(0, EC_AA32_SVC);\n+ res = FIELD_DP32(res, SYNDROME, IL, is_16bit ? 0 : 1);\n+ res = FIELD_DP32(res, ISS_IMM16, IMM16, imm16);\n+ return res;\n }\n \n static inline uint32_t syn_aa32_hvc(uint32_t imm16)\n {\n- return (EC_AA32_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);\n+ uint32_t res = syn_set_ec(0, EC_AA32_HVC);\n+ res = FIELD_DP32(res, SYNDROME, IL, 1);\n+ res = FIELD_DP32(res, ISS_IMM16, IMM16, imm16);\n+ return res;\n }\n \n static inline uint32_t syn_aa32_smc(void)\n {\n- return (EC_AA32_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL;\n+ uint32_t res = syn_set_ec(0, EC_AA32_SMC);\n+ res = FIELD_DP32(res, SYNDROME, IL, 1);\n+ return res;\n }\n \n static inline uint32_t syn_aa64_bkpt(uint32_t imm16)\n {\n- return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);\n+ uint32_t res = syn_set_ec(0, EC_AA64_BKPT);\n+ res = FIELD_DP32(res, SYNDROME, IL, 1);\n+ res = FIELD_DP32(res, ISS_IMM16, IMM16, imm16);\n+ return res;\n }\n \n static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_16bit)\n {\n- return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff)\n- | (is_16bit ? 0 : ARM_EL_IL);\n+ uint32_t res = syn_set_ec(0, EC_AA32_BKPT);\n+ res = FIELD_DP32(res, SYNDROME, IL, is_16bit ? 0 : 1);\n+ res = FIELD_DP32(res, ISS_IMM16, IMM16, imm16);\n+ return res;\n }\n \n static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2,\n@@ -246,7 +276,9 @@ static inline uint32_t syn_simd_access_trap(int cv, int cond, bool is_16bit)\n \n static inline uint32_t syn_sve_access_trap(void)\n {\n- return (EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL;\n+ uint32_t res = syn_set_ec(0, EC_SVEACCESSTRAP);\n+ res = FIELD_DP32(res, SYNDROME, IL, 1);\n+ return res;\n }\n \n /*\n@@ -361,12 +393,16 @@ static inline uint32_t syn_wfx(int cv, int cond, int ti, bool is_16bit)\n \n static inline uint32_t syn_illegalstate(void)\n {\n- return (EC_ILLEGALSTATE << ARM_EL_EC_SHIFT) | ARM_EL_IL;\n+ uint32_t res = syn_set_ec(0, EC_ILLEGALSTATE);\n+ res = FIELD_DP32(res, SYNDROME, IL, 1);\n+ return res;\n }\n \n static inline uint32_t syn_pcalignment(void)\n {\n- return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL;\n+ uint32_t res = syn_set_ec(0, EC_PCALIGNMENT);\n+ res = FIELD_DP32(res, SYNDROME, IL, 1);\n+ return res;\n }\n \n static inline uint32_t syn_gcs_data_check(GCSInstructionType it, int rn)\n@@ -388,7 +424,10 @@ static inline uint32_t syn_gcs_gcsstr(int ra, int rn)\n \n static inline uint32_t syn_serror(uint32_t extra)\n {\n- return (EC_SERROR << ARM_EL_EC_SHIFT) | ARM_EL_IL | extra;\n+ uint32_t res = syn_set_ec(0, EC_SERROR);\n+ res = FIELD_DP32(res, SYNDROME, IL, 1);\n+ res = FIELD_DP32(res, SYNDROME, ISS, extra);\n+ return res;\n }\n \n static inline uint32_t syn_mop(bool is_set, bool is_setg, int options,\n","prefixes":["PULL","41/63"]}