{"id":2228860,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2228860/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427124738.966578-43-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260427124738.966578-43-peter.maydell@linaro.org>","date":"2026-04-27T12:47:16","name":"[PULL,42/63] target/arm: migrate system/cp trap syndromes to registerfields","commit_ref":null,"pull_url":null,"state":"not-applicable","archived":false,"hash":"92f63a4c513623fd558f583e71201abedb65dd8a","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/1.1/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427124738.966578-43-peter.maydell@linaro.org/mbox/","series":[{"id":501642,"url":"http://patchwork.ozlabs.org/api/1.1/series/501642/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501642","date":"2026-04-27T12:46:34","name":"[PULL,01/63] docs/system: add FEAT_AA32 and FEAT_AA64 to emulation list","version":1,"mbox":"http://patchwork.ozlabs.org/series/501642/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2228860/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2228860/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=E/5Uhj41;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g43Vm4kmGz1yJX\n\tfor ; Mon, 27 Apr 2026 22:57:04 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wHLUd-0000B8-TI; Mon, 27 Apr 2026 08:55:20 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wHLO4-0008BO-SO\n for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:35 -0400","from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wHLNw-0005ic-IS\n for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:27 -0400","by mail-wm1-x32b.google.com with SMTP id\n 5b1f17b1804b1-48334ee0aeaso107050985e9.1\n for ; Mon, 27 Apr 2026 05:48:19 -0700 (PDT)","from lanath.. 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The co-processor syndromes are split\nbetween single and duel register moves.\n\nReviewed-by: Richard Henderson \nSigned-off-by: Alex Bennée \nMessage-id: 20260422125250.1303100-3-alex.bennee@linaro.org\nSigned-off-by: Peter Maydell \n---\n target/arm/syndrome.h | 124 ++++++++++++++++++++++++++++++++++--------\n 1 file changed, 102 insertions(+), 22 deletions(-)","diff":"diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h\nindex 517fb2368b..29462aa103 100644\n--- a/target/arm/syndrome.h\n+++ b/target/arm/syndrome.h\n@@ -78,7 +78,7 @@ enum arm_exception_class {\n \n /* Generic syndrome encoding layout for HSR and lower 32 bits of ESR_EL2 */\n FIELD(SYNDROME, EC, 26, 6)\n-FIELD(SYNDROME, IL, 25, 1)\n+FIELD(SYNDROME, IL, 25, 1) /* IL=1 for 32 bit instructions */\n FIELD(SYNDROME, ISS, 0, 25)\n \n typedef enum {\n@@ -172,7 +172,7 @@ static inline uint32_t syn_aa64_smc(uint32_t imm16)\n static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_16bit)\n {\n uint32_t res = syn_set_ec(0, EC_AA32_SVC);\n- res = FIELD_DP32(res, SYNDROME, IL, is_16bit ? 0 : 1);\n+ res = FIELD_DP32(res, SYNDROME, IL, !is_16bit);\n res = FIELD_DP32(res, ISS_IMM16, IMM16, imm16);\n return res;\n }\n@@ -203,58 +203,138 @@ static inline uint32_t syn_aa64_bkpt(uint32_t imm16)\n static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_16bit)\n {\n uint32_t res = syn_set_ec(0, EC_AA32_BKPT);\n- res = FIELD_DP32(res, SYNDROME, IL, is_16bit ? 0 : 1);\n+ res = FIELD_DP32(res, SYNDROME, IL, !is_16bit);\n res = FIELD_DP32(res, ISS_IMM16, IMM16, imm16);\n return res;\n }\n \n+/*\n+ * ISS encoding for an exception from MSR, MRS, or System instruction\n+ * in AArch64 state.\n+ */\n+FIELD(SYSREG_ISS, ISREAD, 0, 1) /* Direction, 1 is read */\n+FIELD(SYSREG_ISS, CRM, 1, 4)\n+FIELD(SYSREG_ISS, RT, 5, 5)\n+FIELD(SYSREG_ISS, CRN, 10, 4)\n+FIELD(SYSREG_ISS, OP1, 14, 3)\n+FIELD(SYSREG_ISS, OP2, 17, 3)\n+FIELD(SYSREG_ISS, OP0, 20, 2)\n+\n static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2,\n int crn, int crm, int rt,\n int isread)\n {\n- return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL\n- | (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5)\n- | (crm << 1) | isread;\n+ uint32_t res = syn_set_ec(0, EC_SYSTEMREGISTERTRAP);\n+ res = FIELD_DP32(res, SYNDROME, IL, 1);\n+\n+ res = FIELD_DP32(res, SYSREG_ISS, OP0, op0);\n+ res = FIELD_DP32(res, SYSREG_ISS, OP2, op2);\n+ res = FIELD_DP32(res, SYSREG_ISS, OP1, op1);\n+ res = FIELD_DP32(res, SYSREG_ISS, CRN, crn);\n+ res = FIELD_DP32(res, SYSREG_ISS, RT, rt);\n+ res = FIELD_DP32(res, SYSREG_ISS, CRM, crm);\n+ res = FIELD_DP32(res, SYSREG_ISS, ISREAD, isread);\n+\n+ return res;\n }\n \n+/*\n+ * ISS encoding for an exception from an MCR or MRC access\n+ * (move to/from co-processor)\n+ */\n+FIELD(COPROC_ISS, ISREAD, 0, 1)\n+FIELD(COPROC_ISS, CRM, 1, 4)\n+FIELD(COPROC_ISS, RT, 5, 5)\n+FIELD(COPROC_ISS, CRN, 10, 4)\n+FIELD(COPROC_ISS, OP1, 14, 3)\n+FIELD(COPROC_ISS, OP2, 17, 3)\n+FIELD(COPROC_ISS, COND, 20, 4)\n+FIELD(COPROC_ISS, CV, 24, 1)\n+\n static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int opc2,\n int crn, int crm, int rt, int isread,\n bool is_16bit)\n {\n- return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT)\n- | (is_16bit ? 0 : ARM_EL_IL)\n- | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14)\n- | (crn << 10) | (rt << 5) | (crm << 1) | isread;\n+ uint32_t res = syn_set_ec(0, EC_CP14RTTRAP);\n+ res = FIELD_DP32(res, SYNDROME, IL, !is_16bit);\n+\n+ res = FIELD_DP32(res, COPROC_ISS, CV, cv);\n+ res = FIELD_DP32(res, COPROC_ISS, COND, cond);\n+ res = FIELD_DP32(res, COPROC_ISS, OP2, opc2);\n+ res = FIELD_DP32(res, COPROC_ISS, OP1, opc1);\n+ res = FIELD_DP32(res, COPROC_ISS, CRN, crn);\n+ res = FIELD_DP32(res, COPROC_ISS, RT, rt);\n+ res = FIELD_DP32(res, COPROC_ISS, CRM, crm);\n+ res = FIELD_DP32(res, COPROC_ISS, ISREAD, isread);\n+\n+ return res;\n }\n \n static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int opc2,\n int crn, int crm, int rt, int isread,\n bool is_16bit)\n {\n- return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT)\n- | (is_16bit ? 0 : ARM_EL_IL)\n- | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14)\n- | (crn << 10) | (rt << 5) | (crm << 1) | isread;\n+ uint32_t res = syn_set_ec(0, EC_CP15RTTRAP);\n+ res = FIELD_DP32(res, SYNDROME, IL, !is_16bit);\n+\n+ res = FIELD_DP32(res, COPROC_ISS, CV, cv);\n+ res = FIELD_DP32(res, COPROC_ISS, COND, cond);\n+ res = FIELD_DP32(res, COPROC_ISS, OP2, opc2);\n+ res = FIELD_DP32(res, COPROC_ISS, OP1, opc1);\n+ res = FIELD_DP32(res, COPROC_ISS, CRN, crn);\n+ res = FIELD_DP32(res, COPROC_ISS, RT, rt);\n+ res = FIELD_DP32(res, COPROC_ISS, CRM, crm);\n+ res = FIELD_DP32(res, COPROC_ISS, ISREAD, isread);\n+\n+ return res;\n }\n \n+/*\n+ * ISS encoding for an exception from an MCRR or MRRC access\n+ * (move to/from co-processor with 2 regs)\n+ */\n+FIELD(COPROC_R2_ISS, ISREAD, 0, 1)\n+FIELD(COPROC_R2_ISS, CRM, 1, 4)\n+FIELD(COPROC_R2_ISS, RT, 5, 5)\n+FIELD(COPROC_R2_ISS, RT2, 10, 5)\n+FIELD(COPROC_R2_ISS, OP1, 16, 4)\n+FIELD(COPROC_R2_ISS, COND, 20, 4)\n+FIELD(COPROC_R2_ISS, CV, 24, 1)\n+\n static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int crm,\n int rt, int rt2, int isread,\n bool is_16bit)\n {\n- return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT)\n- | (is_16bit ? 0 : ARM_EL_IL)\n- | (cv << 24) | (cond << 20) | (opc1 << 16)\n- | (rt2 << 10) | (rt << 5) | (crm << 1) | isread;\n+ uint32_t res = syn_set_ec(0, EC_CP14RRTTRAP);\n+ res = FIELD_DP32(res, SYNDROME, IL, !is_16bit);\n+\n+ res = FIELD_DP32(res, COPROC_R2_ISS, CV, cv);\n+ res = FIELD_DP32(res, COPROC_R2_ISS, COND, cond);\n+ res = FIELD_DP32(res, COPROC_R2_ISS, OP1, opc1);\n+ res = FIELD_DP32(res, COPROC_R2_ISS, RT2, rt2);\n+ res = FIELD_DP32(res, COPROC_R2_ISS, RT, rt);\n+ res = FIELD_DP32(res, COPROC_R2_ISS, CRM, crm);\n+ res = FIELD_DP32(res, COPROC_R2_ISS, ISREAD, isread);\n+\n+ return res;\n }\n \n static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm,\n int rt, int rt2, int isread,\n bool is_16bit)\n {\n- return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT)\n- | (is_16bit ? 0 : ARM_EL_IL)\n- | (cv << 24) | (cond << 20) | (opc1 << 16)\n- | (rt2 << 10) | (rt << 5) | (crm << 1) | isread;\n+ uint32_t res = syn_set_ec(0, EC_CP15RRTTRAP);\n+ res = FIELD_DP32(res, SYNDROME, IL, !is_16bit);\n+\n+ res = FIELD_DP32(res, COPROC_R2_ISS, CV, cv);\n+ res = FIELD_DP32(res, COPROC_R2_ISS, COND, cond);\n+ res = FIELD_DP32(res, COPROC_R2_ISS, OP1, opc1);\n+ res = FIELD_DP32(res, COPROC_R2_ISS, RT2, rt2);\n+ res = FIELD_DP32(res, COPROC_R2_ISS, RT, rt);\n+ res = FIELD_DP32(res, COPROC_R2_ISS, CRM, crm);\n+ res = FIELD_DP32(res, COPROC_R2_ISS, ISREAD, isread);\n+\n+ return res;\n }\n \n static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit,\n","prefixes":["PULL","42/63"]}