{"id":2228852,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2228852/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427124738.966578-35-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260427124738.966578-35-peter.maydell@linaro.org>","date":"2026-04-27T12:47:08","name":"[PULL,34/63] target/arm/cpu64: Mitigate migration failures due to spurious TCR_EL1, PIRE0_EL1 and PIR_EL1","commit_ref":null,"pull_url":null,"state":"not-applicable","archived":false,"hash":"a78464ae25a22deb3a1f95e2d25c578eb59a069c","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/1.1/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427124738.966578-35-peter.maydell@linaro.org/mbox/","series":[{"id":501642,"url":"http://patchwork.ozlabs.org/api/1.1/series/501642/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501642","date":"2026-04-27T12:46:34","name":"[PULL,01/63] docs/system: add FEAT_AA32 and FEAT_AA64 to emulation list","version":1,"mbox":"http://patchwork.ozlabs.org/series/501642/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2228852/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2228852/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=q58AQbzB;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g43Tq45KXz1yHv\n\tfor ; Mon, 27 Apr 2026 22:56:15 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wHLPv-00019e-Uw; Mon, 27 Apr 2026 08:50:29 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wHLNw-00087E-QS\n for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:31 -0400","from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wHLNp-0005ga-24\n for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:19 -0400","by mail-wm1-x32e.google.com with SMTP id\n 5b1f17b1804b1-488a9033b2cso109080595e9.2\n for ; Mon, 27 Apr 2026 05:48:12 -0700 (PDT)","from lanath.. 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charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::32e;\n envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Eric Auger \n\nBefore linux v6.13 those registers were erroneously unconditionally\nexposed and this was fixed by commits:\n- 0fcb4eea5345 (\"KVM: arm64: Hide TCR2_EL1 from userspace when\n disabled for guests\")\n- a68cddbe47ef (\"KVM: arm64: Hide S1PIE registers from userspace\n when disabled for guests\")\nin v6.13.\n\nThis means if we migrate from an old kernel host to a >= 6.13 kernel\nhost, migration currently fails.\n\nDeclare cpreg migration tolerance for those registers.\n\nSigned-off-by: Eric Auger \nReviewed-by: Sebastian Ott \nReviewed-by: Peter Maydell \nMessage-id: 20260420140552.104369-5-eric.auger@redhat.com\nSigned-off-by: Peter Maydell \n---\n target/arm/cpu64.c | 28 ++++++++++++++++++++++++++++\n 1 file changed, 28 insertions(+)","diff":"diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c\nindex d6feba220e..e7014022df 100644\n--- a/target/arm/cpu64.c\n+++ b/target/arm/cpu64.c\n@@ -810,6 +810,33 @@ static void aarch64_a53_initfn(Object *obj)\n define_cortex_a72_a57_a53_cp_reginfo(cpu);\n }\n \n+#if defined(CONFIG_KVM)\n+static void kvm_arm_set_cpreg_mig_tolerances(ARMCPU *cpu)\n+{\n+ /*\n+ * Registers that may be in the incoming stream and not exposed\n+ * on the destination\n+ */\n+\n+ /*\n+ * TCR_EL1 was erroneously unconditionnally exposed before linux v6.13.\n+ * See commit 0fcb4eea5345 (\"KVM: arm64: Hide TCR2_EL1 from userspace\n+ * when disabled for guests\")\n+ */\n+ arm_register_cpreg_mig_tolerance(cpu, ARM64_SYS_REG(3, 0, 2, 0, 3),\n+ 0, 0, ToleranceNotOnBothEnds);\n+ /*\n+ * PIRE0_EL1 and PIR_EL1 were erroneously unconditionnally exposed\n+ * before linux v6.13. See commit a68cddbe47ef (\"KVM: arm64: Hide\n+ * S1PIE registers from userspace when disabled for guests\")\n+ */\n+ arm_register_cpreg_mig_tolerance(cpu, ARM64_SYS_REG(3, 0, 10, 2, 2),\n+ 0, 0, ToleranceNotOnBothEnds);\n+ arm_register_cpreg_mig_tolerance(cpu, ARM64_SYS_REG(3, 0, 10, 2, 3),\n+ 0, 0, ToleranceNotOnBothEnds);\n+}\n+#endif\n+\n static void aarch64_host_initfn(Object *obj)\n {\n ARMCPU *cpu = ARM_CPU(obj);\n@@ -822,6 +849,7 @@ static void aarch64_host_initfn(Object *obj)\n #endif\n \n #if defined(CONFIG_KVM)\n+ kvm_arm_set_cpreg_mig_tolerances(cpu);\n kvm_arm_set_cpu_features_from_host(cpu);\n aarch64_add_sve_properties(obj);\n #elif defined(CONFIG_HVF)\n","prefixes":["PULL","34/63"]}