{"id":2228831,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2228831/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427124738.966578-30-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260427124738.966578-30-peter.maydell@linaro.org>","date":"2026-04-27T12:47:03","name":"[PULL,29/63] target/arm: Allow 'aarch64=off' to be set for TCG CPUs","commit_ref":null,"pull_url":null,"state":"not-applicable","archived":false,"hash":"a8ecbc59ec555ef67bd9fc425c8161ec4a7bbff6","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/1.1/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427124738.966578-30-peter.maydell@linaro.org/mbox/","series":[{"id":501642,"url":"http://patchwork.ozlabs.org/api/1.1/series/501642/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501642","date":"2026-04-27T12:46:34","name":"[PULL,01/63] docs/system: add FEAT_AA32 and FEAT_AA64 to emulation list","version":1,"mbox":"http://patchwork.ozlabs.org/series/501642/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2228831/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2228831/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=ksd7aXot;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g43S05PLGz1xvV\n\tfor ; Mon, 27 Apr 2026 22:54:40 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wHLQR-0002I4-PZ; Mon, 27 Apr 2026 08:51:17 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wHLNq-00084l-9z\n for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:25 -0400","from mail-wm1-x329.google.com ([2a00:1450:4864:20::329])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wHLNi-0005fk-Pc\n for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:12 -0400","by mail-wm1-x329.google.com with SMTP id\n 5b1f17b1804b1-4891b0786beso72841525e9.1\n for ; Mon, 27 Apr 2026 05:48:07 -0700 (PDT)","from lanath.. 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charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::329;\n envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Allow the 'aarch64=off' property, which is currently KVM-only, to\nbe set for TCG CPUs also.\n\nNote that we don't permit it on the qemu-aarch64 user-mode binary:\nthis makes no sense as that executable can only handle AArch64\nsyscalls (and it would also assert at startup since it doesn't\ncompile in the A32-specific GDB xml files like arm-neon.xml).\n\nSigned-off-by: Peter Maydell \nReviewed-by: Richard Henderson \nTested-by: Clément Chigot \nReviewed-by: Philippe Mathieu-Daudé \nMessage-id: 20260416165353.589569-3-peter.maydell@linaro.org\n---\n docs/system/arm/cpu-features.rst | 10 +++++----\n target/arm/cpu-features.h | 5 +++++\n target/arm/cpu.c | 36 ++++++++++++++++++++++++++++----\n tests/qtest/arm-cpu-features.c | 8 ++-----\n 4 files changed, 45 insertions(+), 14 deletions(-)","diff":"diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-features.rst\nindex ce19ae6a04..10b0eff27e 100644\n--- a/docs/system/arm/cpu-features.rst\n+++ b/docs/system/arm/cpu-features.rst\n@@ -23,10 +23,12 @@ not implement ARMv8-A, will not have the ``aarch64`` CPU property.\n QEMU's support may be limited for some CPU features, only partially\n supporting the feature or only supporting the feature under certain\n configurations. For example, the ``aarch64`` CPU feature, which, when\n-disabled, enables the optional AArch32 CPU feature, is only supported\n-when using the KVM accelerator and when running on a host CPU type that\n-supports the feature. While ``aarch64`` currently only works with KVM,\n-it could work with TCG. CPU features that are specific to KVM are\n+disabled, enables the optional AArch32 CPU feature, can only be set to\n+``off`` on the TCG and KVM accelerators, and it cannot be set to\n+``off`` under KVM unless running on a host CPU type that supports\n+running guests in AArch32.\n+\n+CPU features that are inherently specific to KVM are\n prefixed with \"kvm-\" and are described in \"KVM VCPU Features\".\n \n CPU Feature Probing\ndiff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h\nindex b683c9551a..6e5212ff6c 100644\n--- a/target/arm/cpu-features.h\n+++ b/target/arm/cpu-features.h\n@@ -1071,6 +1071,11 @@ static inline bool isar_feature_aa64_aa32_el2(const ARMISARegisters *id)\n return FIELD_EX64_IDREG(id, ID_AA64PFR0, EL2) >= 2;\n }\n \n+static inline bool isar_feature_aa64_aa32_el3(const ARMISARegisters *id)\n+{\n+ return FIELD_EX64_IDREG(id, ID_AA64PFR0, EL3) >= 2;\n+}\n+\n static inline bool isar_feature_aa64_ras(const ARMISARegisters *id)\n {\n return FIELD_EX64_IDREG(id, ID_AA64PFR0, RAS) != 0;\ndiff --git a/target/arm/cpu.c b/target/arm/cpu.c\nindex 6705ee9db7..9b80dda140 100644\n--- a/target/arm/cpu.c\n+++ b/target/arm/cpu.c\n@@ -1244,10 +1244,38 @@ static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp)\n * uniform execution state like do_interrupt.\n */\n if (value == false) {\n- if (!kvm_enabled() || !kvm_arm_aarch32_supported()) {\n- error_setg(errp, \"'aarch64' feature cannot be disabled \"\n- \"unless KVM is enabled and 32-bit EL1 \"\n- \"is supported\");\n+ if (kvm_enabled()) {\n+ if (!kvm_arm_aarch32_supported()) {\n+ error_setg(errp, \"'aarch64' feature cannot be disabled for KVM \"\n+ \"because this host does not support 32-bit EL1\");\n+ return;\n+ }\n+ } else if (tcg_enabled()) {\n+#ifdef CONFIG_USER_ONLY\n+ error_setg(errp, \"'aarch64' feature cannot be disabled for \"\n+ \"usermode emulator qemu-aarch64; use qemu-arm instead\");\n+ return;\n+#else\n+ bool aa32_at_highest_el;\n+ if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {\n+ aa32_at_highest_el = cpu_isar_feature(aa64_aa32_el3, cpu);\n+ } else if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) {\n+ aa32_at_highest_el = cpu_isar_feature(aa64_aa32_el2, cpu);\n+ } else {\n+ aa32_at_highest_el = cpu_isar_feature(aa64_aa32_el1, cpu);\n+ }\n+\n+ if (!aa32_at_highest_el) {\n+ error_setg(errp, \"'aarch64' feature cannot be disabled for \"\n+ \"this TCG CPU because it does not support 32-bit \"\n+ \"execution at its highest implemented exception \"\n+ \"level\");\n+ return;\n+ }\n+#endif\n+ } else {\n+ error_setg(errp, \"'aarch64' feature cannot be disabled for \"\n+ \"this accelerator\");\n return;\n }\n unset_feature(&cpu->env, ARM_FEATURE_AARCH64);\ndiff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c\nindex bbdd89a81d..cb4d01fd46 100644\n--- a/tests/qtest/arm-cpu-features.c\n+++ b/tests/qtest/arm-cpu-features.c\n@@ -493,12 +493,8 @@ static void test_query_cpu_model_expansion(const void *data)\n sve_tests_default(qts, \"max\");\n pauth_tests_default(qts, \"max\");\n \n- /* Test that features that depend on KVM generate errors without. */\n- assert_error(qts, \"max\",\n- \"'aarch64' feature cannot be disabled \"\n- \"unless KVM is enabled and 32-bit EL1 \"\n- \"is supported\",\n- \"{ 'aarch64': false }\");\n+ /* TCG allows us to turn off AArch64 on the 'max' CPU type */\n+ assert_set_feature(qts, \"max\", \"aarch64\", false);\n }\n \n qtest_quit(qts);\n","prefixes":["PULL","29/63"]}