{"id":2228824,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2228824/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427124738.966578-52-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260427124738.966578-52-peter.maydell@linaro.org>","date":"2026-04-27T12:47:25","name":"[PULL,51/63] target/arm: migrate debug syndromes to registerfields","commit_ref":null,"pull_url":null,"state":"not-applicable","archived":false,"hash":"ecdb26468f68b6033c008f884d888d2f0f8dcb04","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/1.1/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427124738.966578-52-peter.maydell@linaro.org/mbox/","series":[{"id":501642,"url":"http://patchwork.ozlabs.org/api/1.1/series/501642/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501642","date":"2026-04-27T12:46:34","name":"[PULL,01/63] docs/system: add FEAT_AA32 and FEAT_AA64 to emulation list","version":1,"mbox":"http://patchwork.ozlabs.org/series/501642/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2228824/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2228824/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=UYM41hMf;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g43NT3WbPz1xvV\n\tfor ; Mon, 27 Apr 2026 22:51:37 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wHLQD-0002Bz-Hm; Mon, 27 Apr 2026 08:50:45 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wHLO7-0008D8-PY\n for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:36 -0400","from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wHLO4-0005ku-HT\n for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:35 -0400","by mail-wm1-x32e.google.com with SMTP id\n 5b1f17b1804b1-488b0e1b870so172754555e9.2\n for ; Mon, 27 Apr 2026 05:48:27 -0700 (PDT)","from lanath.. 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charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::32e;\n envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Alex Bennée \n\nMigrate syn_swstep, syn_watchpoint and syn_breakpoint to the\nregisterfields API.\n\nReviewed-by: Richard Henderson \nSigned-off-by: Alex Bennée \nMessage-id: 20260422125250.1303100-12-alex.bennee@linaro.org\nSigned-off-by: Peter Maydell \n---\n target/arm/syndrome.h | 54 ++++++++++++++++++++++++++++++++++++++-----\n 1 file changed, 48 insertions(+), 6 deletions(-)","diff":"diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h\nindex 2031b3704f..2ad6b97aea 100644\n--- a/target/arm/syndrome.h\n+++ b/target/arm/syndrome.h\n@@ -595,22 +595,64 @@ static inline uint32_t syn_data_abort_vncr(int ea, int wnr, int fsc)\n return res;\n }\n \n+/*\n+ * ISS encoding for an exception from a Software Step exception.\n+ */\n+FIELD(SOFTSTEP_ISS, IFSC, 0, 6)\n+FIELD(SOFTSTEP_ISS, EX, 6, 1)\n+FIELD(SOFTSTEP_ISS, ISV, 24, 1)\n+\n static inline uint32_t syn_swstep(int same_el, int isv, int ex)\n {\n- return (EC_SOFTWARESTEP << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)\n- | ARM_EL_IL | (isv << 24) | (ex << 6) | 0x22;\n+ uint32_t res = syn_set_ec(0, EC_SOFTWARESTEP + same_el);\n+ res = FIELD_DP32(res, SYNDROME, IL, 1);\n+\n+ res = FIELD_DP32(res, SOFTSTEP_ISS, ISV, isv);\n+ res = FIELD_DP32(res, SOFTSTEP_ISS, EX, ex);\n+ res = FIELD_DP32(res, SOFTSTEP_ISS, IFSC, 0x22);\n+\n+ return res;\n }\n \n+/*\n+ * ISS encoding for an exception from a Watchpoint exception\n+ */\n+FIELD(WATCHPOINT_ISS, DFSC, 0, 6)\n+FIELD(WATCHPOINT_ISS, WNR, 6, 1)\n+FIELD(WATCHPOINT_ISS, CM, 8, 1)\n+FIELD(WATCHPOINT_ISS, FnV, 10, 1)\n+FIELD(WATCHPOINT_ISS, VNCR, 13, 1) /* FEAT_NV2 */\n+FIELD(WATCHPOINT_ISS, FnP, 15, 1)\n+FIELD(WATCHPOINT_ISS, WPF, 16, 1)\n+/* bellow mandatory from FEAT_Debugv8p9 */\n+FIELD(WATCHPOINT_ISS, WPTV, 17, 1) /* FEAT_Debugv8p2 - WPT valid */\n+FIELD(WATCHPOINT_ISS, WPT, 18, 6) /* FEAT_Debugv8p2 - missing WP number */\n+\n static inline uint32_t syn_watchpoint(int same_el, int cm, int wnr)\n {\n- return (EC_WATCHPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)\n- | ARM_EL_IL | (cm << 8) | (wnr << 6) | 0x22;\n+ uint32_t res = syn_set_ec(0, EC_WATCHPOINT + same_el);\n+ res = FIELD_DP32(res, SYNDROME, IL, 1);\n+\n+ res = FIELD_DP32(res, WATCHPOINT_ISS, CM, cm);\n+ res = FIELD_DP32(res, WATCHPOINT_ISS, WNR, wnr);\n+ res = FIELD_DP32(res, WATCHPOINT_ISS, DFSC, 0x22);\n+\n+ return res;\n }\n \n+/*\n+ * ISS encoding for an exception from a Breakpoint or a Vector Catch\n+ * debug exception.\n+ */\n+FIELD(BREAKPOINT_ISS, IFSC, 0, 6)\n+\n static inline uint32_t syn_breakpoint(int same_el)\n {\n- return (EC_BREAKPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)\n- | ARM_EL_IL | 0x22;\n+ uint32_t res = syn_set_ec(0, EC_BREAKPOINT + same_el);\n+ res = FIELD_DP32(res, SYNDROME, IL, 1);\n+ res = FIELD_DP32(res, BREAKPOINT_ISS, IFSC, 0x22);\n+\n+ return res;\n }\n \n static inline uint32_t syn_wfx(int cv, int cond, int ti, bool is_16bit)\n","prefixes":["PULL","51/63"]}