{"id":2228818,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2228818/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427124738.966578-11-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260427124738.966578-11-peter.maydell@linaro.org>","date":"2026-04-27T12:46:44","name":"[PULL,10/63] hw/arm/fsl-imx8mm: Adding support for I2C emulation","commit_ref":null,"pull_url":null,"state":"not-applicable","archived":false,"hash":"4c9d580db0042354f4f8ee7ff6955dcfd106b709","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/1.1/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427124738.966578-11-peter.maydell@linaro.org/mbox/","series":[{"id":501642,"url":"http://patchwork.ozlabs.org/api/1.1/series/501642/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501642","date":"2026-04-27T12:46:34","name":"[PULL,01/63] docs/system: add FEAT_AA32 and FEAT_AA64 to emulation list","version":1,"mbox":"http://patchwork.ozlabs.org/series/501642/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2228818/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2228818/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=Lsa3H0st;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g43L16p1kz1yHX\n\tfor ; Mon, 27 Apr 2026 22:49:29 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wHLOZ-0000GB-Rw; Mon, 27 Apr 2026 08:49:09 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wHLNQ-0007nV-0a\n for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:47:53 -0400","from mail-wm1-x329.google.com ([2a00:1450:4864:20::329])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wHLNN-0005U3-Ip\n for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:47:51 -0400","by mail-wm1-x329.google.com with SMTP id\n 5b1f17b1804b1-488b150559bso81056025e9.1\n for ; Mon, 27 Apr 2026 05:47:49 -0700 (PDT)","from lanath.. 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helo=mail-wm1-x329.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Gaurav Sharma \n\nThis can be used to test and debug I2C device drivers.\nAdded I2C interrupts\n\nReviewed-by: Philippe Mathieu-Daude \nReviewed-by: Peter Maydell \nReviewed-by: Bernhard Beschow \nSigned-off-by: Gaurav Sharma \nSigned-off-by: Peter Maydell \n---\n hw/arm/Kconfig | 2 ++\n hw/arm/fsl-imx8mm.c | 27 +++++++++++++++++++++++++++\n include/hw/arm/fsl-imx8mm.h | 8 ++++++++\n 3 files changed, 37 insertions(+)","diff":"diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig\nindex 59d5aba2db..e8296f9a28 100644\n--- a/hw/arm/Kconfig\n+++ b/hw/arm/Kconfig\n@@ -620,10 +620,12 @@ config FSL_IMX8MP_EVK\n config FSL_IMX8MM\n bool\n imply PCI_DEVICES\n+ imply I2C_DEVICES\n select ARM_GIC\n select FSL_IMX8MP_ANALOG\n select FSL_IMX8MP_CCM\n select IMX\n+ select IMX_I2C\n select SDHCI\n select PCI_EXPRESS_DESIGNWARE\n select PCI_EXPRESS_FSL_IMX8M_PHY\ndiff --git a/hw/arm/fsl-imx8mm.c b/hw/arm/fsl-imx8mm.c\nindex 85bce5a788..3632d85197 100644\n--- a/hw/arm/fsl-imx8mm.c\n+++ b/hw/arm/fsl-imx8mm.c\n@@ -180,6 +180,11 @@ static void fsl_imx8mm_init(Object *obj)\n object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL);\n }\n \n+ for (i = 0; i < FSL_IMX8MM_NUM_I2CS; i++) {\n+ g_autofree char *name = g_strdup_printf(\"i2c%d\", i + 1);\n+ object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C);\n+ }\n+\n for (i = 0; i < FSL_IMX8MM_NUM_GPIOS; i++) {\n g_autofree char *name = g_strdup_printf(\"gpio%d\", i + 1);\n object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO);\n@@ -370,6 +375,27 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)\n fsl_imx8mm_memmap[FSL_IMX8MM_OCRAM].addr,\n &s->ocram);\n \n+ /* I2Cs */\n+ for (i = 0; i < FSL_IMX8MM_NUM_I2CS; i++) {\n+ static const struct {\n+ hwaddr addr;\n+ unsigned int irq;\n+ } i2c_table[FSL_IMX8MM_NUM_I2CS] = {\n+ { fsl_imx8mm_memmap[FSL_IMX8MM_I2C1].addr, FSL_IMX8MM_I2C1_IRQ },\n+ { fsl_imx8mm_memmap[FSL_IMX8MM_I2C2].addr, FSL_IMX8MM_I2C2_IRQ },\n+ { fsl_imx8mm_memmap[FSL_IMX8MM_I2C3].addr, FSL_IMX8MM_I2C3_IRQ },\n+ { fsl_imx8mm_memmap[FSL_IMX8MM_I2C4].addr, FSL_IMX8MM_I2C4_IRQ },\n+ };\n+\n+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), errp)) {\n+ return;\n+ }\n+\n+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);\n+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,\n+ qdev_get_gpio_in(gicdev, i2c_table[i].irq));\n+ }\n+\n /* GPIOs */\n for (i = 0; i < FSL_IMX8MM_NUM_GPIOS; i++) {\n static const struct {\n@@ -477,6 +503,7 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)\n case FSL_IMX8MM_GIC_DIST:\n case FSL_IMX8MM_GIC_REDIST:\n case FSL_IMX8MM_GPIO1 ... FSL_IMX8MM_GPIO5:\n+ case FSL_IMX8MM_I2C1 ... FSL_IMX8MM_I2C4:\n case FSL_IMX8MM_PCIE1:\n case FSL_IMX8MM_PCIE_PHY1:\n case FSL_IMX8MM_RAM:\ndiff --git a/include/hw/arm/fsl-imx8mm.h b/include/hw/arm/fsl-imx8mm.h\nindex 4fe27b9575..d6df16e9d4 100644\n--- a/include/hw/arm/fsl-imx8mm.h\n+++ b/include/hw/arm/fsl-imx8mm.h\n@@ -13,6 +13,7 @@\n #include \"cpu.h\"\n #include \"hw/char/imx_serial.h\"\n #include \"hw/gpio/imx_gpio.h\"\n+#include \"hw/i2c/imx_i2c.h\"\n #include \"hw/intc/arm_gicv3_common.h\"\n #include \"hw/misc/imx7_snvs.h\"\n #include \"hw/misc/imx8mp_analog.h\"\n@@ -32,6 +33,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(FslImx8mmState, FSL_IMX8MM)\n enum FslImx8mmConfiguration {\n FSL_IMX8MM_NUM_CPUS = 4,\n FSL_IMX8MM_NUM_GPIOS = 5,\n+ FSL_IMX8MM_NUM_I2CS = 4,\n FSL_IMX8MM_NUM_IRQS = 128,\n FSL_IMX8MM_NUM_UARTS = 4,\n FSL_IMX8MM_NUM_USDHCS = 3,\n@@ -46,6 +48,7 @@ struct FslImx8mmState {\n IMX8MPCCMState ccm;\n IMX8MPAnalogState analog;\n IMX7SNVSState snvs;\n+ IMXI2CState i2c[FSL_IMX8MM_NUM_I2CS];\n IMXSerialState uart[FSL_IMX8MM_NUM_UARTS];\n MemoryRegion ocram;\n SDHCIState usdhc[FSL_IMX8MM_NUM_USDHCS];\n@@ -174,6 +177,11 @@ enum FslImx8mmIrqs {\n FSL_IMX8MM_UART3_IRQ = 28,\n FSL_IMX8MM_UART4_IRQ = 29,\n \n+ FSL_IMX8MM_I2C1_IRQ = 35,\n+ FSL_IMX8MM_I2C2_IRQ = 36,\n+ FSL_IMX8MM_I2C3_IRQ = 37,\n+ FSL_IMX8MM_I2C4_IRQ = 38,\n+\n FSL_IMX8MM_GPIO1_LOW_IRQ = 64,\n FSL_IMX8MM_GPIO1_HIGH_IRQ = 65,\n FSL_IMX8MM_GPIO2_LOW_IRQ = 66,\n","prefixes":["PULL","10/63"]}