{"id":2228817,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2228817/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427124738.966578-5-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260427124738.966578-5-peter.maydell@linaro.org>","date":"2026-04-27T12:46:38","name":"[PULL,04/63] hw/arm/fsl-imx8mm: Add Analog device IP to iMX8MM SOC","commit_ref":null,"pull_url":null,"state":"not-applicable","archived":false,"hash":"84447c488b6a2219895ccbedd93e435ab565c11c","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/1.1/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427124738.966578-5-peter.maydell@linaro.org/mbox/","series":[{"id":501642,"url":"http://patchwork.ozlabs.org/api/1.1/series/501642/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501642","date":"2026-04-27T12:46:34","name":"[PULL,01/63] docs/system: add FEAT_AA32 and FEAT_AA64 to emulation list","version":1,"mbox":"http://patchwork.ozlabs.org/series/501642/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2228817/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2228817/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=WRVZjrrS;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g43Kv5b05z1yHX\n\tfor ; Mon, 27 Apr 2026 22:49:23 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wHLOG-0008Mm-BN; Mon, 27 Apr 2026 08:48:44 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wHLNL-0007lF-8C\n for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:47:51 -0400","from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wHLNI-0005RA-KM\n for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:47:46 -0400","by mail-wm1-x32b.google.com with SMTP id\n 5b1f17b1804b1-4896c22fcbaso74975685e9.0\n for ; Mon, 27 Apr 2026 05:47:44 -0700 (PDT)","from lanath.. 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So iMX8MM will be overriding this property\nwith its own reset-value.\n\nReviewed-by: Bernhard Beschow \nSigned-off-by: Gaurav Sharma \nSigned-off-by: Peter Maydell \n---\n hw/arm/Kconfig | 1 +\n hw/arm/fsl-imx8mm.c | 12 ++++++++++++\n include/hw/arm/fsl-imx8mm.h | 2 ++\n 3 files changed, 15 insertions(+)","diff":"diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig\nindex 86f4d9bc4d..b3db2d6848 100644\n--- a/hw/arm/Kconfig\n+++ b/hw/arm/Kconfig\n@@ -620,6 +620,7 @@ config FSL_IMX8MP_EVK\n config FSL_IMX8MM\n bool\n select ARM_GIC\n+ select FSL_IMX8MP_ANALOG\n select IMX\n \n config FSL_IMX8MM_EVK\ndiff --git a/hw/arm/fsl-imx8mm.c b/hw/arm/fsl-imx8mm.c\nindex 23a82613d7..8218448074 100644\n--- a/hw/arm/fsl-imx8mm.c\n+++ b/hw/arm/fsl-imx8mm.c\n@@ -169,6 +169,8 @@ static void fsl_imx8mm_init(Object *obj)\n \n object_initialize_child(obj, \"gic\", &s->gic, gicv3_class_name());\n \n+ object_initialize_child(obj, \"analog\", &s->analog, TYPE_IMX8MP_ANALOG);\n+\n for (i = 0; i < FSL_IMX8MM_NUM_UARTS; i++) {\n g_autofree char *name = g_strdup_printf(\"uart%d\", i + 1);\n object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL);\n@@ -303,6 +305,15 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)\n }\n }\n \n+ /* Analog */\n+ object_property_set_uint(OBJECT(&s->analog), \"arm-pll-fdiv-ctl0-reset\",\n+ 0x000fa030, &error_abort);\n+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->analog), errp)) {\n+ return;\n+ }\n+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->analog), 0,\n+ fsl_imx8mm_memmap[FSL_IMX8MM_ANA_PLL].addr);\n+\n /* UARTs */\n for (i = 0; i < FSL_IMX8MM_NUM_UARTS; i++) {\n static const struct {\n@@ -338,6 +349,7 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)\n /* Unimplemented devices */\n for (i = 0; i < ARRAY_SIZE(fsl_imx8mm_memmap); i++) {\n switch (i) {\n+ case FSL_IMX8MM_ANA_PLL:\n case FSL_IMX8MM_GIC_DIST:\n case FSL_IMX8MM_GIC_REDIST:\n case FSL_IMX8MM_RAM:\ndiff --git a/include/hw/arm/fsl-imx8mm.h b/include/hw/arm/fsl-imx8mm.h\nindex 2811e809b9..0a020c32a1 100644\n--- a/include/hw/arm/fsl-imx8mm.h\n+++ b/include/hw/arm/fsl-imx8mm.h\n@@ -13,6 +13,7 @@\n #include \"cpu.h\"\n #include \"hw/char/imx_serial.h\"\n #include \"hw/intc/arm_gicv3_common.h\"\n+#include \"hw/misc/imx8mp_analog.h\"\n #include \"qom/object.h\"\n #include \"qemu/units.h\"\n \n@@ -33,6 +34,7 @@ struct FslImx8mmState {\n \n ARMCPU cpu[FSL_IMX8MM_NUM_CPUS];\n GICv3State gic;\n+ IMX8MPAnalogState analog;\n IMXSerialState uart[FSL_IMX8MM_NUM_UARTS];\n MemoryRegion ocram;\n };\n","prefixes":["PULL","04/63"]}