{"id":2228816,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2228816/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427124738.966578-13-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260427124738.966578-13-peter.maydell@linaro.org>","date":"2026-04-27T12:46:46","name":"[PULL,12/63] hw/arm/fsl-imx8mm: Adding support for Watchdog Timers","commit_ref":null,"pull_url":null,"state":"not-applicable","archived":false,"hash":"e07544b4836524427b90a2ad71827189dba8e589","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/1.1/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427124738.966578-13-peter.maydell@linaro.org/mbox/","series":[{"id":501642,"url":"http://patchwork.ozlabs.org/api/1.1/series/501642/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501642","date":"2026-04-27T12:46:34","name":"[PULL,01/63] docs/system: add FEAT_AA32 and FEAT_AA64 to emulation list","version":1,"mbox":"http://patchwork.ozlabs.org/series/501642/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2228816/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2228816/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=bLWTlEwJ;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g43Kd4Hv1z1yHX\n\tfor ; Mon, 27 Apr 2026 22:49:09 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wHLOR-00005k-KY; Mon, 27 Apr 2026 08:48:56 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wHLNR-0007nb-5k\n for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:47:53 -0400","from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wHLNP-0005UQ-9L\n for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:47:52 -0400","by mail-wm1-x32d.google.com with SMTP id\n 5b1f17b1804b1-488b3f8fa2bso103390745e9.1\n for ; Mon, 27 Apr 2026 05:47:50 -0700 (PDT)","from lanath.. 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helo=mail-wm1-x32d.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Gaurav Sharma \n\nIt enables emulation of WDT in iMX8MM\nAdded WDT IRQ lines\n\nReviewed-by: Philippe Mathieu-Daude \nReviewed-by: Peter Maydell \nReviewed-by: Bernhard Beschow \nSigned-off-by: Gaurav Sharma \nSigned-off-by: Peter Maydell \n---\n hw/arm/Kconfig | 1 +\n hw/arm/fsl-imx8mm.c | 28 ++++++++++++++++++++++++++++\n include/hw/arm/fsl-imx8mm.h | 7 +++++++\n 3 files changed, 36 insertions(+)","diff":"diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig\nindex e8296f9a28..42901c4383 100644\n--- a/hw/arm/Kconfig\n+++ b/hw/arm/Kconfig\n@@ -629,6 +629,7 @@ config FSL_IMX8MM\n select SDHCI\n select PCI_EXPRESS_DESIGNWARE\n select PCI_EXPRESS_FSL_IMX8M_PHY\n+ select WDT_IMX2\n \n config FSL_IMX8MM_EVK\n bool\ndiff --git a/hw/arm/fsl-imx8mm.c b/hw/arm/fsl-imx8mm.c\nindex f433beeaf2..34645555d6 100644\n--- a/hw/arm/fsl-imx8mm.c\n+++ b/hw/arm/fsl-imx8mm.c\n@@ -200,6 +200,11 @@ static void fsl_imx8mm_init(Object *obj)\n object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI);\n }\n \n+ for (i = 0; i < FSL_IMX8MM_NUM_WDTS; i++) {\n+ g_autofree char *name = g_strdup_printf(\"wdt%d\", i);\n+ object_initialize_child(obj, name, &s->wdt[i], TYPE_IMX2_WDT);\n+ }\n+\n object_initialize_child(obj, \"pcie\", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST);\n object_initialize_child(obj, \"pcie_phy\", &s->pcie_phy,\n TYPE_FSL_IMX8M_PCIE_PHY);\n@@ -496,6 +501,28 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)\n sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0,\n fsl_imx8mm_memmap[FSL_IMX8MM_SNVS_HP].addr);\n \n+ /* Watchdogs */\n+ for (i = 0; i < FSL_IMX8MM_NUM_WDTS; i++) {\n+ static const struct {\n+ hwaddr addr;\n+ unsigned int irq;\n+ } wdog_table[FSL_IMX8MM_NUM_WDTS] = {\n+ { fsl_imx8mm_memmap[FSL_IMX8MM_WDOG1].addr, FSL_IMX8MM_WDOG1_IRQ },\n+ { fsl_imx8mm_memmap[FSL_IMX8MM_WDOG2].addr, FSL_IMX8MM_WDOG2_IRQ },\n+ { fsl_imx8mm_memmap[FSL_IMX8MM_WDOG3].addr, FSL_IMX8MM_WDOG3_IRQ },\n+ };\n+\n+ object_property_set_bool(OBJECT(&s->wdt[i]), \"pretimeout-support\",\n+ true, &error_abort);\n+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {\n+ return;\n+ }\n+\n+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, wdog_table[i].addr);\n+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0,\n+ qdev_get_gpio_in(gicdev, wdog_table[i].irq));\n+ }\n+\n /* PCIe */\n if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie), errp)) {\n return;\n@@ -537,6 +564,7 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)\n case FSL_IMX8MM_SNVS_HP:\n case FSL_IMX8MM_UART1 ... FSL_IMX8MM_UART4:\n case FSL_IMX8MM_USDHC1 ... FSL_IMX8MM_USDHC3:\n+ case FSL_IMX8MM_WDOG1 ... FSL_IMX8MM_WDOG3:\n /* device implemented and treated above */\n break;\n \ndiff --git a/include/hw/arm/fsl-imx8mm.h b/include/hw/arm/fsl-imx8mm.h\nindex 13c044412a..fd62b19a87 100644\n--- a/include/hw/arm/fsl-imx8mm.h\n+++ b/include/hw/arm/fsl-imx8mm.h\n@@ -22,6 +22,7 @@\n #include \"hw/pci-host/fsl_imx8m_phy.h\"\n #include \"hw/sd/sdhci.h\"\n #include \"hw/ssi/imx_spi.h\"\n+#include \"hw/watchdog/wdt_imx2.h\"\n #include \"qom/object.h\"\n #include \"qemu/units.h\"\n \n@@ -39,6 +40,7 @@ enum FslImx8mmConfiguration {\n FSL_IMX8MM_NUM_IRQS = 128,\n FSL_IMX8MM_NUM_UARTS = 4,\n FSL_IMX8MM_NUM_USDHCS = 3,\n+ FSL_IMX8MM_NUM_WDTS = 3,\n };\n \n struct FslImx8mmState {\n@@ -55,6 +57,7 @@ struct FslImx8mmState {\n IMXSerialState uart[FSL_IMX8MM_NUM_UARTS];\n MemoryRegion ocram;\n SDHCIState usdhc[FSL_IMX8MM_NUM_USDHCS];\n+ IMX2WdtState wdt[FSL_IMX8MM_NUM_WDTS];\n DesignwarePCIEHost pcie;\n FslImx8mPciePhyState pcie_phy;\n };\n@@ -200,6 +203,10 @@ enum FslImx8mmIrqs {\n FSL_IMX8MM_GPIO5_LOW_IRQ = 72,\n FSL_IMX8MM_GPIO5_HIGH_IRQ = 73,\n \n+ FSL_IMX8MM_WDOG1_IRQ = 78,\n+ FSL_IMX8MM_WDOG2_IRQ = 79,\n+ FSL_IMX8MM_WDOG3_IRQ = 10,\n+\n FSL_IMX8MM_PCI_INTA_IRQ = 122,\n FSL_IMX8MM_PCI_INTB_IRQ = 123,\n FSL_IMX8MM_PCI_INTC_IRQ = 124,\n","prefixes":["PULL","12/63"]}