{"id":2228812,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2228812/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427051507.727280-2-314abh@gmail.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260427051507.727280-2-314abh@gmail.com>","date":"2026-04-27T05:15:07","name":"[1/1] target/riscv: Fix medeleg[11] read-only zero bit for M-mode ECALL","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"c51c7882732bac9d9dd26fd21fe2886c99b4841e","submitter":{"id":93260,"url":"http://patchwork.ozlabs.org/api/1.1/people/93260/?format=json","name":"Abhigyan Kumar","email":"314abh@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427051507.727280-2-314abh@gmail.com/mbox/","series":[{"id":501641,"url":"http://patchwork.ozlabs.org/api/1.1/series/501641/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501641","date":"2026-04-27T05:15:06","name":"target/riscv: Fix medeleg[11] read-only zero bit for M-mode ECALL","version":1,"mbox":"http://patchwork.ozlabs.org/series/501641/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2228812/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2228812/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=sjEElzvB;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-pf1-x42a.google.com","X-Spam_score_int":"-13","X-Spam_score":"-1.4","X-Spam_bar":"-","X-Spam_report":"(-1.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001,\n FROM_STARTS_WITH_NUMS=0.738, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=no autolearn_force=no","X-Spam_action":"no action","X-Mailman-Approved-At":"Mon, 27 Apr 2026 08:47:18 -0400","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"RISC-V Privileged Specification 3.1.8 (Machine Trap Delegation Registers\n(medeleg and mideleg)) mentions:\n\n\"For exceptions that cannot occur in less privileged modes, the\ncorresponding medeleg bits should be read-only zero. In particular,\nmedeleg[11] is read-only zero.\"\n\nQEMU incorrectly included RISCV_EXCP_M_ECALL in DELEGABLE_EXCPS. It\nallowed the 11th bit to be written and read as set. Fixed by removing it\nfrom the DELEGABLE_EXCPS mask, adhering to the specification.\n\nResolves: https://gitlab.com/qemu-project/qemu/-/work_items/3438\nSigned-off-by: Abhigyan Kumar <314abh@gmail.com>\n---\n target/riscv/csr.c | 5 ++++-\n 1 file changed, 4 insertions(+), 1 deletion(-)","diff":"diff --git a/target/riscv/csr.c b/target/riscv/csr.c\nindex a75281539..c9bf73dd7 100644\n--- a/target/riscv/csr.c\n+++ b/target/riscv/csr.c\n@@ -1775,6 +1775,10 @@ static const uint64_t vs_delegable_ints =\n (VS_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & ~MIP_LCOFIP;\n static const uint64_t all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |\n HS_MODE_INTERRUPTS | LOCAL_INTERRUPTS;\n+/* \n+ * As per RSIC-V Privileged Spec Section 3.1.8, M-mode ecall should be a\n+ * read-only zero. Therefore, medeleg[11] is set to zero below. \n+ */\n #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \\\n (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \\\n (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \\\n@@ -1786,7 +1790,6 @@ static const uint64_t all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |\n (1ULL << (RISCV_EXCP_U_ECALL)) | \\\n (1ULL << (RISCV_EXCP_S_ECALL)) | \\\n (1ULL << (RISCV_EXCP_VS_ECALL)) | \\\n- (1ULL << (RISCV_EXCP_M_ECALL)) | \\\n (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | \\\n (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | \\\n (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | \\\n","prefixes":["1/1"]}