{"id":2228802,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2228802/?format=json","web_url":"http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20260427122742.210074-4-mkchauras@gmail.com/","project":{"id":2,"url":"http://patchwork.ozlabs.org/api/1.1/projects/2/?format=json","name":"Linux PPC development","link_name":"linuxppc-dev","list_id":"linuxppc-dev.lists.ozlabs.org","list_email":"linuxppc-dev@lists.ozlabs.org","web_url":"https://github.com/linuxppc/wiki/wiki","scm_url":"https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git","webscm_url":"https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/"},"msgid":"<20260427122742.210074-4-mkchauras@gmail.com>","date":"2026-04-27T12:27:37","name":"[v5,3/8] powerpc: introduce arch_enter_from_user_mode","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"182b745a1ee326862dd3cf30de8555c0e647f3d7","submitter":{"id":92575,"url":"http://patchwork.ozlabs.org/api/1.1/people/92575/?format=json","name":"Mukesh Kumar Chaurasiya","email":"mkchauras@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20260427122742.210074-4-mkchauras@gmail.com/mbox/","series":[{"id":501638,"url":"http://patchwork.ozlabs.org/api/1.1/series/501638/?format=json","web_url":"http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=501638","date":"2026-04-27T12:27:34","name":"Generic IRQ entry/exit support for powerpc","version":5,"mbox":"http://patchwork.ozlabs.org/series/501638/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2228802/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2228802/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=pgdIkCMj;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org\n (client-ip=2404:9400:21b9:f100::1; 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This helper prepares the CPU state when entering\nthe kernel from userspace, ensuring correct handling of KUAP/KUEP,\ntransactional memory, and debug register state.\n\nThis patch contains no functional changes, it is purely preparatory for\nenabling the generic syscall and interrupt entry path on PowerPC.\n\nSigned-off-by: Mukesh Kumar Chaurasiya \nTested-by: Samir M \nTested-by: David Gow \nTested-by: Venkat Rao Bagalkote \nReviewed-by: Shrikanth Hegde \n---\n arch/powerpc/include/asm/entry-common.h | 118 ++++++++++++++++++++++++\n 1 file changed, 118 insertions(+)","diff":"diff --git a/arch/powerpc/include/asm/entry-common.h b/arch/powerpc/include/asm/entry-common.h\nindex 05ce0583b600..837a7e020e82 100644\n--- a/arch/powerpc/include/asm/entry-common.h\n+++ b/arch/powerpc/include/asm/entry-common.h\n@@ -3,6 +3,124 @@\n #ifndef _ASM_PPC_ENTRY_COMMON_H\n #define _ASM_PPC_ENTRY_COMMON_H\n \n+#include \n+#include \n #include \n+#include \n+\n+static __always_inline void booke_load_dbcr0(void)\n+{\n+#ifdef CONFIG_PPC_ADV_DEBUG_REGS\n+\tunsigned long dbcr0 = current->thread.debug.dbcr0;\n+\n+\tif (likely(!(dbcr0 & DBCR0_IDM)))\n+\t\treturn;\n+\n+\t/*\n+\t * Check to see if the dbcr0 register is set up to debug.\n+\t * Use the internal debug mode bit to do this.\n+\t */\n+\tmtmsr(mfmsr() & ~MSR_DE);\n+\tif (IS_ENABLED(CONFIG_PPC32)) {\n+\t\tisync();\n+\t\tglobal_dbcr0[smp_processor_id()] = mfspr(SPRN_DBCR0);\n+\t}\n+\tmtspr(SPRN_DBCR0, dbcr0);\n+\tmtspr(SPRN_DBSR, -1);\n+#endif\n+}\n+\n+static __always_inline void arch_enter_from_user_mode(struct pt_regs *regs)\n+{\n+\tkuap_lock();\n+\n+\tif (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG))\n+\t\tBUG_ON(irq_soft_mask_return() != IRQS_ALL_DISABLED);\n+\n+\tBUG_ON(regs_is_unrecoverable(regs));\n+\tBUG_ON(!user_mode(regs));\n+\tBUG_ON(regs_irqs_disabled(regs));\n+\n+#ifdef CONFIG_PPC_PKEY\n+\tif (mmu_has_feature(MMU_FTR_PKEY) && trap_is_syscall(regs)) {\n+\t\tunsigned long amr, iamr;\n+\t\tbool flush_needed = false;\n+\t\t/*\n+\t\t * When entering from userspace we mostly have the AMR/IAMR\n+\t\t * different from kernel default values. Hence don't compare.\n+\t\t */\n+\t\tamr = mfspr(SPRN_AMR);\n+\t\tiamr = mfspr(SPRN_IAMR);\n+\t\tregs->amr = amr;\n+\t\tregs->iamr = iamr;\n+\t\tif (mmu_has_feature(MMU_FTR_KUAP)) {\n+\t\t\tmtspr(SPRN_AMR, AMR_KUAP_BLOCKED);\n+\t\t\tflush_needed = true;\n+\t\t}\n+\t\tif (mmu_has_feature(MMU_FTR_BOOK3S_KUEP)) {\n+\t\t\tmtspr(SPRN_IAMR, AMR_KUEP_BLOCKED);\n+\t\t\tflush_needed = true;\n+\t\t}\n+\t\tif (flush_needed)\n+\t\t\tisync();\n+\t}\n+#endif\n+\tkuap_assert_locked();\n+\tbooke_restore_dbcr0();\n+\taccount_cpu_user_entry();\n+\taccount_stolen_time();\n+\n+\t/*\n+\t * This is not required for the syscall exit path, but makes the\n+\t * stack frame look nicer. If this was initialised in the first stack\n+\t * frame, or if the unwinder was taught the first stack frame always\n+\t * returns to user with IRQS_ENABLED, this store could be avoided!\n+\t */\n+\tirq_soft_mask_regs_set_state(regs, IRQS_ENABLED);\n+\n+\t/*\n+\t * If system call is called with TM active, set _TIF_RESTOREALL to\n+\t * prevent RFSCV being used to return to userspace, because POWER9\n+\t * TM implementation has problems with this instruction returning to\n+\t * transactional state. Final register values are not relevant because\n+\t * the transaction will be aborted upon return anyway. Or in the case\n+\t * of unsupported_scv SIGILL fault, the return state does not much\n+\t * matter because it's an edge case.\n+\t */\n+\tif (IS_ENABLED(CONFIG_PPC_TRANSACTIONAL_MEM) &&\n+\t unlikely(MSR_TM_TRANSACTIONAL(regs->msr)))\n+\t\tset_bits(_TIF_RESTOREALL, ¤t_thread_info()->flags);\n+\n+\t/*\n+\t * If the system call was made with a transaction active, doom it and\n+\t * return without performing the system call. Unless it was an\n+\t * unsupported scv vector, in which case it's treated like an illegal\n+\t * instruction.\n+\t */\n+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM\n+\tif (unlikely(MSR_TM_TRANSACTIONAL(regs->msr)) &&\n+\t !trap_is_unsupported_scv(regs)) {\n+\t\t/* Enable TM in the kernel, and disable EE (for scv) */\n+\t\thard_irq_disable();\n+\t\tmtmsr(mfmsr() | MSR_TM);\n+\n+\t\t/* tabort, this dooms the transaction, nothing else */\n+\t\tasm volatile(\".long 0x7c00071d | ((%0) << 16)\"\n+\t\t\t :: \"r\"(TM_CAUSE_SYSCALL | TM_CAUSE_PERSISTENT));\n+\n+\t\t/*\n+\t\t * Userspace will never see the return value. Execution will\n+\t\t * resume after the tbegin. of the aborted transaction with the\n+\t\t * checkpointed register state. A context switch could occur\n+\t\t * or signal delivered to the process before resuming the\n+\t\t * doomed transaction context, but that should all be handled\n+\t\t * as expected.\n+\t\t */\n+\t\treturn;\n+\t}\n+#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */\n+}\n+\n+#define arch_enter_from_user_mode arch_enter_from_user_mode\n \n #endif /* _ASM_PPC_ENTRY_COMMON_H */\n","prefixes":["v5","3/8"]}