{"id":2228736,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2228736/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/patch/20260427094945.47448-1-garthlei@linux.alibaba.com/","project":{"id":17,"url":"http://patchwork.ozlabs.org/api/1.1/projects/17/?format=json","name":"GNU Compiler Collection","link_name":"gcc","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260427094945.47448-1-garthlei@linux.alibaba.com>","date":"2026-04-27T09:49:45","name":"[v6] simplify-rtx: Simplify (cmp (and/ior x C1) C2)","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"1e8758a7b734315e11dfe8863904df743c7a2128","submitter":{"id":89310,"url":"http://patchwork.ozlabs.org/api/1.1/people/89310/?format=json","name":"Bohan Lei","email":"garthlei@linux.alibaba.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/gcc/patch/20260427094945.47448-1-garthlei@linux.alibaba.com/mbox/","series":[{"id":501615,"url":"http://patchwork.ozlabs.org/api/1.1/series/501615/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/list/?series=501615","date":"2026-04-27T09:49:45","name":"[v6] simplify-rtx: Simplify (cmp (and/ior x C1) C2)","version":6,"mbox":"http://patchwork.ozlabs.org/series/501615/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2228736/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2228736/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=linux.alibaba.com header.i=@linux.alibaba.com\n header.a=rsa-sha256 header.s=default header.b=gsJPWH1u;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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c=relaxed/simple;\n bh=aX7j7d3abwntbqxtjmtuMxuAMisRgI5oarL3OnA/0Dk=;\n h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version;\n b=J4eW9TXRWAfyqPEMBI8EnR1Rnsf4SIqYdRa8WPjfUcRGZuj2/ujRCae0mXX8P8fqq6E8e3pHwSz00HCLbBhKcgls/uQsZLwQOy7E0QTHibAMnPTKgck3q2XuMSKmj8O1DQR2VduKY2LhuJiCsSwZjnqcdrEF4QqO5R5tHApZf08=","ARC-Authentication-Results":"i=1; server2.sourceware.org","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=linux.alibaba.com; s=default;\n t=1777283406; h=From:To:Subject:Date:Message-Id:MIME-Version;\n bh=RnrbjJN+4FgEh48VKwjRU149yKi+mP7/CgVvz7N9FxQ=;\n b=gsJPWH1uczeW3r1N+KYvRgsfjAQg2ExGEaMOdzM+OfNcaSzzT362ffSS1uQgG5/vmhyH6Jf2t9CUzzTylRrTWCaoPBrAxPc/ENRzs/Q78X9Y/6048k012eqtksLiSeOBRd+xPwQ+4gHitzIWxgNfc6Tl2OTfGv2yiDItow8IypM=","X-Alimail-AntiSpam":"AC=PASS; BC=-1|-1; BR=01201311R451e4; CH=green;\n DM=||false|;\n DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=maildocker-contentspam033045098064;\n MF=garthlei@linux.alibaba.com; NM=1; PH=DS; RN=5; SR=0;\n TI=SMTPD_---0X1mHRFE_1777283397;","From":"Bohan Lei ","To":"gcc-patches@gcc.gnu.org","Cc":"jeffrey.law@oss.qualcomm.com, philipp.tomsich@vrull.eu,\n andrew.pinski@oss.qualcomm.com, Bohan Lei ","Subject":"[PATCH v6] simplify-rtx: Simplify (cmp (and/ior x C1) C2)","Date":"Mon, 27 Apr 2026 17:49:45 +0800","Message-Id":"<20260427094945.47448-1-garthlei@linux.alibaba.com>","X-Mailer":"git-send-email 2.39.3 (Apple Git-146)","In-Reply-To":"<20260427015626.4256-1-garthlei@linux.alibaba.com>","References":"<20260427015626.4256-1-garthlei@linux.alibaba.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org"},"content":"This is v6 of\nhttps://gcc.gnu.org/pipermail/gcc-patches/2026-March/711809.html, fixed\nand enhanced as was suggested by Philipp and Andrew. The previous\nversion:\nhttps://gcc.gnu.org/pipermail/gcc-patches/2026-April/714878.html.\nAndrew noticed the x86 regression and suggested updating the testcase.\n\nThis patch adds missing simplifications for (cmp (and/ior x C1) C2) in\nspecial cases. In the AND case, when (and C1 C2) is not equal to C1,\nsome bits set in C2 are not set in C1, and thus (eq (and x C1) C2) can\nnever be true. The OR case is similar when (and C1 C2) is not equal to\nC2. As we know that the result of (and x C1) cannot be greater than C1,\nand that that of (or x C1) cannot be less than C1 for unsigned integers,\nLTU, LEU, GTU, GEU cases can be optimized, too.\n\nThe patch is meant to fix an ICE on RISC-V. In a former patch, I tried\nto change the insn condition directly, but Jeff pointed out that it was\nmore reasonable to optimize it out before the split. As was suggested\nby Jeff, this patch tries to simplify the expression in\nsimplify_relational_operation_1.\n\nThe URL for the former patch:\nhttps://patchwork.sourceware.org/project/gcc/patch/20251229024238.15044-1-garthlei@linux.alibaba.com/\n\ngcc/ChangeLog:\n\n\t* simplify-rtx.cc (simplify_context::simplify_relational_operation_1):\n\tAdd simplifications for `(cmp (and/ior x C1) C2)`.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/i386/pr113609-1.c: Change assembly check after\n\toptimization.\n\t* gcc.target/riscv/zbs-if_then_else-02.c: New test.\n---\n gcc/simplify-rtx.cc | 45 +++++++++++++++++++\n gcc/testsuite/gcc.target/i386/pr113609-1.c | 4 +-\n .../gcc.target/riscv/zbs-if_then_else-02.c | 32 +++++++++++++\n 3 files changed, 79 insertions(+), 2 deletions(-)\n create mode 100644 gcc/testsuite/gcc.target/riscv/zbs-if_then_else-02.c","diff":"diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc\nindex 50fc51152ca..9fcb160ad92 100644\n--- a/gcc/simplify-rtx.cc\n+++ b/gcc/simplify-rtx.cc\n@@ -6731,6 +6731,51 @@ simplify_context::simplify_relational_operation_1 (rtx_code code,\n \t}\n }\n \n+ /* Optimize (cmp (and/ior x C1) C2) depending on the CMP and C1 and C2's\n+ relationship. */\n+ if ((op0code == AND || op0code == IOR)\n+ && CONST_INT_P (op1)\n+ && CONST_INT_P (XEXP (op0, 1)))\n+ {\n+ unsigned HOST_WIDE_INT c1 = UINTVAL (XEXP (op0, 1));\n+ unsigned HOST_WIDE_INT c2 = UINTVAL (op1);\n+\n+ /* For AND operations:\n+\t - (x & c1) == c2 when some bits are set in c2 but not in c1 -> false\n+\t - (x & c1) != c2 when some bits are set in c2 but not in c1 -> true\n+\t - (x & c1) >= c2 when c1 is less than c2 -> false\n+\t - (x & c1) < c2 when c1 is less than c2 -> true\n+\t - (x & c1) > c2 when c1 is less than or equal to c2 -> false\n+\t - (x & c1) <= c2 when c1 is less than or equal to c2 -> true\n+\n+\t For IOR operations:\n+\t - (x | c1) == c2 when some bits are set in c1 but not in c2 -> false\n+\t - (x | c1) != c2 when some bits are set in c1 but not in c2 -> true\n+\t - (x | c1) <= c2 when c1 is greater than c2 -> false\n+\t - (x | c1) > c2 when c1 is greater than c2 -> true\n+\t - (x | c1) < c2 when c1 is greater than or equal to c2 -> false\n+\t - (x | c1) >= c2 when c1 is greater than or equal to c2 -> true */\n+ if ((op0code == AND\n+\t && ((code == EQ && (c1 & c2) != c2)\n+\t || (code == GEU && c1 < c2)\n+\t || (code == GTU && c1 <= c2)))\n+\t || ((op0code == IOR\n+\t && ((code == EQ && (c1 & c2) != c1)\n+\t\t || (code == LEU && c1 > c2)\n+\t\t || (code == LTU && c1 >= c2)))))\n+\treturn const0_rtx;\n+\n+ if ((op0code == AND\n+\t && ((code == NE && (c1 & c2) != c2)\n+\t || (code == LTU && c1 < c2)\n+\t || (code == LEU && c1 <= c2)))\n+\t || ((op0code == IOR\n+\t && ((code == NE && (c1 & c2) != c1)\n+\t\t || (code == GTU && c1 > c2)\n+\t\t || (code == GEU && c1 >= c2)))))\n+\treturn const_true_rtx;\n+ }\n+\n /* (eq/ne (bswap x) C1) simplifies to (eq/ne x C2) with C2 swapped. */\n if ((code == EQ || code == NE)\n && GET_CODE (op0) == BSWAP\ndiff --git a/gcc/testsuite/gcc.target/i386/pr113609-1.c b/gcc/testsuite/gcc.target/i386/pr113609-1.c\nindex f0639b8500a..be20bbb86ee 100644\n--- a/gcc/testsuite/gcc.target/i386/pr113609-1.c\n+++ b/gcc/testsuite/gcc.target/i386/pr113609-1.c\n@@ -9,9 +9,9 @@\n /* { dg-final { scan-assembler-times \"\\[ \\\\t\\]+sete\" 1 { target { ia32 } } } } */\n /* { dg-final { scan-assembler-times \"\\[ \\\\t\\]+setne\" 1 { target { ia32 } } } } */\n /* { dg-final { scan-assembler-times \"\\[ \\\\t\\]+je\" 1 { target { ia32 } } } } */\n-/* { dg-final { scan-assembler-times \"\\[ \\\\t\\]+jne\" 2 { target { ia32 } } } } */\n+/* { dg-final { scan-assembler-times \"\\[ \\\\t\\]+jne\" 1 { target { ia32 } } } } */\n /* { dg-final { scan-assembler-times \"kortest\" 12 { target { ia32 } } } } */\n-/* { dg-final { scan-assembler-times \"kortest\" 17 { target { ! ia32 } } } } */\n+/* { dg-final { scan-assembler-times \"kortest\" 16 { target { ! ia32 } } } } */\n \n #include \n \ndiff --git a/gcc/testsuite/gcc.target/riscv/zbs-if_then_else-02.c b/gcc/testsuite/gcc.target/riscv/zbs-if_then_else-02.c\nnew file mode 100644\nindex 00000000000..3393bea8898\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/zbs-if_then_else-02.c\n@@ -0,0 +1,32 @@\n+/* { dg-do link { target { rv64 } } } */\n+/* { dg-options \"-march=rv64gc_zbb_zbs -mabi=lp64d -flto\" } */\n+/* { dg-skip-if \"\" { *-*-* } { \"-O0\" \"-Og\" \"-O1\" } } */\n+\n+struct S {\n+ int a;\n+ char b;\n+ int c;\n+} s;\n+\n+const signed char c = -37;\n+int d;\n+struct S v1[] = {{0, 8}, 0, 0, -108976}, v2[] = {{}, 0, 0, 2804};\n+int a;\n+struct S v3[3];\n+int *p = &a;\n+\n+void foo() {\n+ int a;\n+ if (a)\n+ ;\n+ else if (v1[0].b)\n+ s.a = 0;\n+ else\n+ d = 0;\n+ if (*p)\n+ if (v3[1].c)\n+ if (1 ^ (d & c & v2[1].c & ~v1[1].c | s.a))\n+ v3[2].c = 0;\n+}\n+\n+int main() { foo(); }\n","prefixes":["v6"]}