{"id":2228617,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2228617/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/patch/20260427070312.81679-4-clamor95@gmail.com/","project":{"id":21,"url":"http://patchwork.ozlabs.org/api/1.1/projects/21/?format=json","name":"Linux Tegra Development","link_name":"linux-tegra","list_id":"linux-tegra.vger.kernel.org","list_email":"linux-tegra@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260427070312.81679-4-clamor95@gmail.com>","date":"2026-04-27T07:03:08","name":"[v2,3/7] dt-bindings: memory: Document Tegra114 External Memory Controller","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"f95e54c19c66d5f0a2491dae1e8fa26ba8908bf3","submitter":{"id":84146,"url":"http://patchwork.ozlabs.org/api/1.1/people/84146/?format=json","name":"Svyatoslav Ryhel","email":"clamor95@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-tegra/patch/20260427070312.81679-4-clamor95@gmail.com/mbox/","series":[{"id":501587,"url":"http://patchwork.ozlabs.org/api/1.1/series/501587/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/list/?series=501587","date":"2026-04-27T07:03:06","name":"Tegra114: implement EMC support","version":2,"mbox":"http://patchwork.ozlabs.org/series/501587/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2228617/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2228617/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-tegra@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=KKUymfWs;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c15:e001:75::12fc:5321; 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These are the registers (see\n- section \"15.6.2 EMC Registers\" in the TRM) whose values need to\n+ section \"20.11.2 EMC Registers\" in the Tegra114 TRM or section\n+ \"15.6.2 EMC Registers\" in the Tegra124 TRM) whose values need to\n be specified, according to the board documentation.\n $ref: /schemas/types.yaml#/definitions/uint32-array\n- items:\n- - description: EMC_RC\n- - description: EMC_RFC\n- - description: EMC_RFC_SLR\n- - description: EMC_RAS\n- - description: EMC_RP\n- - description: EMC_R2W\n- - description: EMC_W2R\n- - description: EMC_R2P\n- - description: EMC_W2P\n- - description: EMC_RD_RCD\n- - description: EMC_WR_RCD\n- - description: EMC_RRD\n- - description: EMC_REXT\n- - description: EMC_WEXT\n- - description: EMC_WDV\n- - description: EMC_WDV_MASK\n- - description: EMC_QUSE\n- - description: EMC_QUSE_WIDTH\n- - description: EMC_IBDLY\n- - description: EMC_EINPUT\n- - description: EMC_EINPUT_DURATION\n- - description: EMC_PUTERM_EXTRA\n- - description: EMC_PUTERM_WIDTH\n- - description: EMC_PUTERM_ADJ\n- - description: EMC_CDB_CNTL_1\n- - description: EMC_CDB_CNTL_2\n- - description: EMC_CDB_CNTL_3\n- - description: EMC_QRST\n- - description: EMC_QSAFE\n- - description: EMC_RDV\n- - description: EMC_RDV_MASK\n- - description: EMC_REFRESH\n- - description: EMC_BURST_REFRESH_NUM\n- - description: EMC_PRE_REFRESH_REQ_CNT\n- - description: EMC_PDEX2WR\n- - description: EMC_PDEX2RD\n- - description: EMC_PCHG2PDEN\n- - description: EMC_ACT2PDEN\n- - description: EMC_AR2PDEN\n- - description: EMC_RW2PDEN\n- - description: EMC_TXSR\n- - description: EMC_TXSRDLL\n- - description: EMC_TCKE\n- - description: EMC_TCKESR\n- - description: EMC_TPD\n- - description: EMC_TFAW\n- - description: EMC_TRPAB\n- - description: EMC_TCLKSTABLE\n- - description: EMC_TCLKSTOP\n- - description: EMC_TREFBW\n- - description: EMC_FBIO_CFG6\n- - description: EMC_ODT_WRITE\n- - description: EMC_ODT_READ\n- - description: EMC_FBIO_CFG5\n- - description: EMC_CFG_DIG_DLL\n- - description: EMC_CFG_DIG_DLL_PERIOD\n- - description: EMC_DLL_XFORM_DQS0\n- - description: EMC_DLL_XFORM_DQS1\n- - description: EMC_DLL_XFORM_DQS2\n- - description: EMC_DLL_XFORM_DQS3\n- - description: EMC_DLL_XFORM_DQS4\n- - description: EMC_DLL_XFORM_DQS5\n- - description: EMC_DLL_XFORM_DQS6\n- - description: EMC_DLL_XFORM_DQS7\n- - description: EMC_DLL_XFORM_DQS8\n- - description: EMC_DLL_XFORM_DQS9\n- - description: EMC_DLL_XFORM_DQS10\n- - description: EMC_DLL_XFORM_DQS11\n- - description: EMC_DLL_XFORM_DQS12\n- - description: EMC_DLL_XFORM_DQS13\n- - description: EMC_DLL_XFORM_DQS14\n- - description: EMC_DLL_XFORM_DQS15\n- - description: EMC_DLL_XFORM_QUSE0\n- - description: EMC_DLL_XFORM_QUSE1\n- - description: EMC_DLL_XFORM_QUSE2\n- - description: EMC_DLL_XFORM_QUSE3\n- - description: EMC_DLL_XFORM_QUSE4\n- - description: EMC_DLL_XFORM_QUSE5\n- - description: EMC_DLL_XFORM_QUSE6\n- - description: EMC_DLL_XFORM_QUSE7\n- - description: EMC_DLL_XFORM_ADDR0\n- - description: EMC_DLL_XFORM_ADDR1\n- - description: EMC_DLL_XFORM_ADDR2\n- - description: EMC_DLL_XFORM_ADDR3\n- - description: EMC_DLL_XFORM_ADDR4\n- - description: EMC_DLL_XFORM_ADDR5\n- - description: EMC_DLL_XFORM_QUSE8\n- - description: EMC_DLL_XFORM_QUSE9\n- - description: EMC_DLL_XFORM_QUSE10\n- - description: EMC_DLL_XFORM_QUSE11\n- - description: EMC_DLL_XFORM_QUSE12\n- - description: EMC_DLL_XFORM_QUSE13\n- - description: EMC_DLL_XFORM_QUSE14\n- - description: EMC_DLL_XFORM_QUSE15\n- - description: EMC_DLI_TRIM_TXDQS0\n- - description: EMC_DLI_TRIM_TXDQS1\n- - description: EMC_DLI_TRIM_TXDQS2\n- - description: EMC_DLI_TRIM_TXDQS3\n- - description: EMC_DLI_TRIM_TXDQS4\n- - description: EMC_DLI_TRIM_TXDQS5\n- - description: EMC_DLI_TRIM_TXDQS6\n- - description: EMC_DLI_TRIM_TXDQS7\n- - description: EMC_DLI_TRIM_TXDQS8\n- - description: EMC_DLI_TRIM_TXDQS9\n- - description: EMC_DLI_TRIM_TXDQS10\n- - description: EMC_DLI_TRIM_TXDQS11\n- - description: EMC_DLI_TRIM_TXDQS12\n- - description: EMC_DLI_TRIM_TXDQS13\n- - description: EMC_DLI_TRIM_TXDQS14\n- - description: EMC_DLI_TRIM_TXDQS15\n- - description: EMC_DLL_XFORM_DQ0\n- - description: EMC_DLL_XFORM_DQ1\n- - description: EMC_DLL_XFORM_DQ2\n- - description: EMC_DLL_XFORM_DQ3\n- - description: EMC_DLL_XFORM_DQ4\n- - description: EMC_DLL_XFORM_DQ5\n- - description: EMC_DLL_XFORM_DQ6\n- - description: EMC_DLL_XFORM_DQ7\n- - description: EMC_XM2CMDPADCTRL\n- - description: EMC_XM2CMDPADCTRL4\n- - description: EMC_XM2CMDPADCTRL5\n- - description: EMC_XM2DQPADCTRL2\n- - description: EMC_XM2DQPADCTRL3\n- - description: EMC_XM2CLKPADCTRL\n- - description: EMC_XM2CLKPADCTRL2\n- - description: EMC_XM2COMPPADCTRL\n- - description: EMC_XM2VTTGENPADCTRL\n- - description: EMC_XM2VTTGENPADCTRL2\n- - description: EMC_XM2VTTGENPADCTRL3\n- - description: EMC_XM2DQSPADCTRL3\n- - description: EMC_XM2DQSPADCTRL4\n- - description: EMC_XM2DQSPADCTRL5\n- - description: EMC_XM2DQSPADCTRL6\n- - description: EMC_DSR_VTTGEN_DRV\n- - description: EMC_TXDSRVTTGEN\n- - description: EMC_FBIO_SPARE\n- - description: EMC_ZCAL_WAIT_CNT\n- - description: EMC_MRS_WAIT_CNT2\n- - description: EMC_CTT\n- - description: EMC_CTT_DURATION\n- - description: EMC_CFG_PIPE\n- - description: EMC_DYN_SELF_REF_CONTROL\n- - description: EMC_QPOP\n+ minItems: 97\n+ maxItems: 143\n \n required:\n - clock-frequency\n@@ -318,9 +182,7 @@ patternProperties:\n - nvidia,emc-auto-cal-config2\n - nvidia,emc-auto-cal-config3\n - nvidia,emc-auto-cal-interval\n- - nvidia,emc-bgbias-ctl0\n - nvidia,emc-cfg\n- - nvidia,emc-cfg-2\n - nvidia,emc-ctt-term-ctrl\n - nvidia,emc-mode-1\n - nvidia,emc-mode-2\n@@ -344,6 +206,22 @@ required:\n - \"#interconnect-cells\"\n - operating-points-v2\n \n+allOf:\n+ - if:\n+ properties:\n+ compatible:\n+ contains:\n+ enum:\n+ - nvidia,tegra124-emc\n+ then:\n+ patternProperties:\n+ \"^emc-timings-[0-9]+$\":\n+ patternProperties:\n+ \"^timing-[0-9]+$\":\n+ required:\n+ - nvidia,emc-bgbias-ctl0\n+ - nvidia,emc-cfg-2\n+\n additionalProperties: false\n \n examples:\n","prefixes":["v2","3/7"]}