{"id":2228612,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2228612/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/patch/20260427070312.81679-2-clamor95@gmail.com/","project":{"id":21,"url":"http://patchwork.ozlabs.org/api/1.1/projects/21/?format=json","name":"Linux Tegra Development","link_name":"linux-tegra","list_id":"linux-tegra.vger.kernel.org","list_email":"linux-tegra@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260427070312.81679-2-clamor95@gmail.com>","date":"2026-04-27T07:03:06","name":"[v2,1/7] dt-bindings: memory: Document Tegra114 Memory Controller","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"c7ae5fc8843a029c82ee3c534b8834e7f5202fcd","submitter":{"id":84146,"url":"http://patchwork.ozlabs.org/api/1.1/people/84146/?format=json","name":"Svyatoslav Ryhel","email":"clamor95@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-tegra/patch/20260427070312.81679-2-clamor95@gmail.com/mbox/","series":[{"id":501587,"url":"http://patchwork.ozlabs.org/api/1.1/series/501587/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/list/?series=501587","date":"2026-04-27T07:03:06","name":"Tegra114: implement EMC support","version":2,"mbox":"http://patchwork.ozlabs.org/series/501587/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2228612/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2228612/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-tegra@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=KB3aeIqu;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; 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See section\n- \"15.6.1 MC Registers\" in the TRM.\n- items:\n- - description: MC_EMEM_ARB_CFG\n- - description: MC_EMEM_ARB_OUTSTANDING_REQ\n- - description: MC_EMEM_ARB_TIMING_RCD\n- - description: MC_EMEM_ARB_TIMING_RP\n- - description: MC_EMEM_ARB_TIMING_RC\n- - description: MC_EMEM_ARB_TIMING_RAS\n- - description: MC_EMEM_ARB_TIMING_FAW\n- - description: MC_EMEM_ARB_TIMING_RRD\n- - description: MC_EMEM_ARB_TIMING_RAP2PRE\n- - description: MC_EMEM_ARB_TIMING_WAP2PRE\n- - description: MC_EMEM_ARB_TIMING_R2R\n- - description: MC_EMEM_ARB_TIMING_W2W\n- - description: MC_EMEM_ARB_TIMING_R2W\n- - description: MC_EMEM_ARB_TIMING_W2R\n- - description: MC_EMEM_ARB_DA_TURNS\n- - description: MC_EMEM_ARB_DA_COVERS\n- - description: MC_EMEM_ARB_MISC0\n- - description: MC_EMEM_ARB_MISC1\n- - description: MC_EMEM_ARB_RING1_THROTTLE\n+ \"20.11.1 MC Registers\" in the Tegea114 TRM or\n+ \"15.6.1 MC Registers\" in the Tegra124 TRM.\n+ minItems: 18\n+ maxItems: 19\n \n required:\n - clock-frequency\ndiff --git a/include/dt-bindings/memory/tegra114-mc.h b/include/dt-bindings/memory/tegra114-mc.h\nindex dfe99c8a5ba5..5e0d6a1b91f2 100644\n--- a/include/dt-bindings/memory/tegra114-mc.h\n+++ b/include/dt-bindings/memory/tegra114-mc.h\n@@ -40,4 +40,71 @@\n #define TEGRA114_MC_RESET_VDE\t\t14\n #define TEGRA114_MC_RESET_VI\t\t15\n \n+#define TEGRA114_MC_PTCR\t\t0\n+#define TEGRA114_MC_DISPLAY0A\t\t1\n+#define TEGRA114_MC_DISPLAY0AB\t\t2\n+#define TEGRA114_MC_DISPLAY0B\t\t3\n+#define TEGRA114_MC_DISPLAY0BB\t\t4\n+#define TEGRA114_MC_DISPLAY0C\t\t5\n+#define TEGRA114_MC_DISPLAY0CB\t\t6\n+#define TEGRA114_MC_DISPLAY1B\t\t7\n+#define TEGRA114_MC_DISPLAY1BB\t\t8\n+#define TEGRA114_MC_EPPUP\t\t9\n+#define TEGRA114_MC_G2PR\t\t10\n+#define TEGRA114_MC_G2SR\t\t11\n+#define TEGRA114_MC_MPEUNIFBR\t\t12\n+#define TEGRA114_MC_VIRUV\t\t13\n+#define TEGRA114_MC_AFIR\t\t14\n+#define TEGRA114_MC_AVPCARM7R\t\t15\n+#define TEGRA114_MC_DISPLAYHC\t\t16\n+#define TEGRA114_MC_DISPLAYHCB\t\t17\n+#define TEGRA114_MC_FDCDRD\t\t18\n+#define TEGRA114_MC_FDCDRD2\t\t19\n+#define TEGRA114_MC_G2DR\t\t20\n+#define TEGRA114_MC_HDAR\t\t21\n+#define TEGRA114_MC_HOST1XDMAR\t\t22\n+#define TEGRA114_MC_HOST1XR\t\t23\n+#define TEGRA114_MC_IDXSRD\t\t24\n+#define TEGRA114_MC_IDXSRD2\t\t25\n+#define TEGRA114_MC_MPE_IPRED\t\t26\n+#define TEGRA114_MC_MPEAMEMRD\t\t27\n+#define TEGRA114_MC_MPECSRD\t\t28\n+#define TEGRA114_MC_PPCSAHBDMAR\t\t29\n+#define TEGRA114_MC_PPCSAHBSLVR\t\t30\n+#define TEGRA114_MC_SATAR\t\t31\n+#define TEGRA114_MC_TEXSRD\t\t32\n+#define TEGRA114_MC_TEXSRD2\t\t33\n+#define TEGRA114_MC_VDEBSEVR\t\t34\n+#define TEGRA114_MC_VDEMBER\t\t35\n+#define TEGRA114_MC_VDEMCER\t\t36\n+#define TEGRA114_MC_VDETPER\t\t37\n+#define TEGRA114_MC_MPCORELPR\t\t38\n+#define TEGRA114_MC_MPCORER\t\t39\n+#define TEGRA114_MC_EPPU\t\t40\n+#define TEGRA114_MC_EPPV\t\t41\n+#define TEGRA114_MC_EPPY\t\t42\n+#define TEGRA114_MC_MPEUNIFBW\t\t43\n+#define TEGRA114_MC_VIWSB\t\t44\n+#define TEGRA114_MC_VIWU\t\t45\n+#define TEGRA114_MC_VIWV\t\t46\n+#define TEGRA114_MC_VIWY\t\t47\n+#define TEGRA114_MC_G2DW\t\t48\n+#define TEGRA114_MC_AFIW\t\t49\n+#define TEGRA114_MC_AVPCARM7W\t\t50\n+#define TEGRA114_MC_FDCDWR\t\t51\n+#define TEGRA114_MC_FDCDWR2\t\t52\n+#define TEGRA114_MC_HDAW\t\t53\n+#define TEGRA114_MC_HOST1XW\t\t54\n+#define TEGRA114_MC_ISPW\t\t55\n+#define TEGRA114_MC_MPCORELPW\t\t56\n+#define TEGRA114_MC_MPCOREW\t\t57\n+#define TEGRA114_MC_MPECSWR\t\t58\n+#define TEGRA114_MC_PPCSAHBDMAW\t\t59\n+#define TEGRA114_MC_PPCSAHBSLVW\t\t60\n+#define TEGRA114_MC_SATAW\t\t61\n+#define TEGRA114_MC_VDEBSEVW\t\t62\n+#define TEGRA114_MC_VDEDBGW\t\t63\n+#define TEGRA114_MC_VDEMBEW\t\t64\n+#define TEGRA114_MC_VDETPMW\t\t65\n+\n #endif\n","prefixes":["v2","1/7"]}