{"id":2228586,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2228586/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/7403163ebf59380f88c7503b3adf0dae07428df8.1777269009.git.nicolinc@nvidia.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/1.1/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<7403163ebf59380f88c7503b3adf0dae07428df8.1777269009.git.nicolinc@nvidia.com>","date":"2026-04-27T05:54:02","name":"[v4,3/3] iommu/arm-smmu-v3: Allow ATS to be always on","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"f15d026a4d8d8a6fd31c5ca9938cc46185025259","submitter":{"id":82183,"url":"http://patchwork.ozlabs.org/api/1.1/people/82183/?format=json","name":"Nicolin Chen","email":"nicolinc@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/7403163ebf59380f88c7503b3adf0dae07428df8.1777269009.git.nicolinc@nvidia.com/mbox/","series":[{"id":501574,"url":"http://patchwork.ozlabs.org/api/1.1/series/501574/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=501574","date":"2026-04-27T05:53:59","name":"Allow ATS to be always on for certain ATS-capable devices","version":4,"mbox":"http://patchwork.ozlabs.org/series/501574/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2228586/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2228586/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=oKseFeC8;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.105.105.114; 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And\nwhen there is no PASID support or no active PASID, mode 2 is used.\n\nThe driver will also downgrade an STE from mode 1 to mode 2, when the last\nactive substream becomes inactive.\n\nHowever, there are PCIe devices that demand ATS to be always on. For these\ndevices, their STEs have to use the mode 1 as HW ignores EATS with mode 2.\n\nChange the driver accordingly:\n - always use the mode 1\n - never downgrade to mode 2\n - allocate and retain a CD table (see note below)\n\nNote that these devices might not support PASID, i.e. doing non-PASID ATS.\nIn such a case, the ssid_bits is set to 0. However, s1cdmax must be set to\na !0 value in order to keep the S1DSS field effective. Thus, when a master\nrequires ats_always_on, set its s1cdmax to at least 1, meaning that the CD\ntable will have a dummy entry (SSID=1) that will never be used.\n\nNow for these devices, arm_smmu_cdtab_allocated() will always return true,\nv.s. false prior to this change. When its default substream is attached to\nan IDENTITY domain, its first CD is NULL in the table, which is a totally\nvalid case. Thus, add \"!master->ats_always_on\" to the condition.\n\nReviewed-by: Jonathan Cameron \nTested-by: Nirmoy Das \nAcked-by: Nirmoy Das \nReviewed-by: Jason Gunthorpe \nReviewed-by: Kevin Tian \nSigned-off-by: Nicolin Chen \n---\n drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 +\n drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 75 ++++++++++++++++++---\n 2 files changed, 68 insertions(+), 8 deletions(-)","diff":"diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h\nindex ef42df4753ec4..8c3600f4364c5 100644\n--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h\n+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h\n@@ -943,6 +943,7 @@ struct arm_smmu_master {\n \tbool\t\t\t\tats_enabled : 1;\n \tbool\t\t\t\tste_ats_enabled : 1;\n \tbool\t\t\t\tstall_enabled;\n+\tbool\t\t\t\tats_always_on;\n \tunsigned int\t\t\tssid_bits;\n \tunsigned int\t\t\tiopf_refcount;\n };\ndiff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c\nindex e8d7dbe495f03..d478f148cd34b 100644\n--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c\n+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c\n@@ -1742,8 +1742,11 @@ void arm_smmu_clear_cd(struct arm_smmu_master *master, ioasid_t ssid)\n \tif (!arm_smmu_cdtab_allocated(&master->cd_table))\n \t\treturn;\n \tcdptr = arm_smmu_get_cd_ptr(master, ssid);\n-\tif (WARN_ON(!cdptr))\n+\tif (!cdptr) {\n+\t\t/* Only ats_always_on allows a NULL CD on default substream */\n+\t\tWARN_ON(!master->ats_always_on || ssid);\n \t\treturn;\n+\t}\n \tarm_smmu_write_cd_entry(master, ssid, cdptr, &target);\n }\n \n@@ -1756,6 +1759,22 @@ static int arm_smmu_alloc_cd_tables(struct arm_smmu_master *master)\n \tstruct arm_smmu_ctx_desc_cfg *cd_table = &master->cd_table;\n \n \tcd_table->s1cdmax = master->ssid_bits;\n+\n+\t/*\n+\t * When a device doesn't support PASID (non default SSID), ssid_bits is\n+\t * set to 0. This also sets S1CDMAX to 0, which disables the substreams\n+\t * and ignores the S1DSS field.\n+\t *\n+\t * On the other hand, if a device demands ATS to be always on even when\n+\t * its default substream is IOMMU bypassed, it has to use EATS that is\n+\t * only effective with an STE (CFG=S1translate, S1DSS=Bypass). For such\n+\t * use cases, S1CDMAX has to be !0, in order to make use of S1DSS/EATS.\n+\t *\n+\t * Set S1CDMAX no lower than 1. This would add a dummy substream in the\n+\t * CD table but it should never be used by an actual CD.\n+\t */\n+\tif (master->ats_always_on)\n+\t\tcd_table->s1cdmax = max_t(u8, cd_table->s1cdmax, 1);\n \tmax_contexts = 1 << cd_table->s1cdmax;\n \n \tif (!(smmu->features & ARM_SMMU_FEAT_2_LVL_CDTAB) ||\n@@ -3851,7 +3870,8 @@ static int arm_smmu_blocking_set_dev_pasid(struct iommu_domain *new_domain,\n \t * When the last user of the CD table goes away downgrade the STE back\n \t * to a non-cd_table one, by re-attaching its sid_domain.\n \t */\n-\tif (!arm_smmu_ssids_in_use(&master->cd_table)) {\n+\tif (!master->ats_always_on &&\n+\t !arm_smmu_ssids_in_use(&master->cd_table)) {\n \t\tstruct iommu_domain *sid_domain =\n \t\t\tiommu_driver_get_domain_for_dev(master->dev);\n \n@@ -3875,6 +3895,8 @@ static void arm_smmu_attach_dev_ste(struct iommu_domain *domain,\n \t\t.old_domain = old_domain,\n \t\t.ssid = IOMMU_NO_PASID,\n \t};\n+\tbool ats_always_on = master->ats_always_on &&\n+\t\t\t s1dss != STRTAB_STE_1_S1DSS_TERMINATE;\n \n \t/*\n \t * Do not allow any ASID to be changed while are working on the STE,\n@@ -3886,7 +3908,7 @@ static void arm_smmu_attach_dev_ste(struct iommu_domain *domain,\n \t * If the CD table is not in use we can use the provided STE, otherwise\n \t * we use a cdtable STE with the provided S1DSS.\n \t */\n-\tif (arm_smmu_ssids_in_use(&master->cd_table)) {\n+\tif (ats_always_on || arm_smmu_ssids_in_use(&master->cd_table)) {\n \t\t/*\n \t\t * If a CD table has to be present then we need to run with ATS\n \t\t * on because we have to assume a PASID is using ATS. For\n@@ -4215,6 +4237,42 @@ static void arm_smmu_remove_master(struct arm_smmu_master *master)\n \tkfree(master->build_invs);\n }\n \n+static int arm_smmu_master_prepare_ats(struct arm_smmu_master *master)\n+{\n+\tbool s1p = master->smmu->features & ARM_SMMU_FEAT_TRANS_S1;\n+\tunsigned int stu = __ffs(master->smmu->pgsize_bitmap);\n+\tstruct pci_dev *pdev;\n+\tint ret;\n+\n+\tif (!arm_smmu_ats_supported(master))\n+\t\treturn 0;\n+\n+\tpdev = to_pci_dev(master->dev);\n+\n+\tif (!pci_ats_always_on(pdev))\n+\t\tgoto out_prepare;\n+\n+\t/*\n+\t * S1DSS is required for ATS to be always on for identity domain cases.\n+\t * However, the S1DSS field is ignored if !IDR0_S1P or !IDR1_SSIDSIZE.\n+\t */\n+\tif (!s1p || !master->smmu->ssid_bits) {\n+\t\tdev_info_once(master->dev,\n+\t\t\t \"SMMU doesn't support ATS to be always on\\n\");\n+\t\tgoto out_prepare;\n+\t}\n+\n+\tmaster->ats_always_on = true;\n+\n+\tret = arm_smmu_alloc_cd_tables(master);\n+\tif (ret)\n+\t\treturn ret;\n+\n+out_prepare:\n+\tpci_prepare_ats(pdev, stu);\n+\treturn 0;\n+}\n+\n static struct iommu_device *arm_smmu_probe_device(struct device *dev)\n {\n \tint ret;\n@@ -4263,14 +4321,15 @@ static struct iommu_device *arm_smmu_probe_device(struct device *dev)\n \t smmu->features & ARM_SMMU_FEAT_STALL_FORCE)\n \t\tmaster->stall_enabled = true;\n \n-\tif (dev_is_pci(dev)) {\n-\t\tunsigned int stu = __ffs(smmu->pgsize_bitmap);\n-\n-\t\tpci_prepare_ats(to_pci_dev(dev), stu);\n-\t}\n+\tret = arm_smmu_master_prepare_ats(master);\n+\tif (ret)\n+\t\tgoto err_disable_pasid;\n \n \treturn &smmu->iommu;\n \n+err_disable_pasid:\n+\tarm_smmu_disable_pasid(master);\n+\tarm_smmu_remove_master(master);\n err_free_master:\n \tkfree(master);\n \treturn ERR_PTR(ret);\n","prefixes":["v4","3/3"]}