{"id":2228478,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2228478/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260426134002.865628-22-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260426134002.865628-22-richard.henderson@linaro.org>","date":"2026-04-26T13:38:58","name":"[21/84] fpu: Drop parts_float_to_sint_modulo","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"a9a2958f1141668fdca47e0677b851c9a22cfe5a","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.1/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260426134002.865628-22-richard.henderson@linaro.org/mbox/","series":[{"id":501533,"url":"http://patchwork.ozlabs.org/api/1.1/series/501533/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501533","date":"2026-04-26T13:38:37","name":"fpu: Export some internals for targets","version":1,"mbox":"http://patchwork.ozlabs.org/series/501533/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2228478/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2228478/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=df+ZDg8T;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g3Sv54XLcz1yJ1\n\tfor ; Sun, 26 Apr 2026 23:57:37 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wGzjP-0007Sh-LJ; Sun, 26 Apr 2026 09:41:07 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wGzjO-0007S6-VV\n for qemu-devel@nongnu.org; Sun, 26 Apr 2026 09:41:06 -0400","from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wGzjN-0008Uo-36\n for qemu-devel@nongnu.org; Sun, 26 Apr 2026 09:41:06 -0400","by mail-pl1-x62e.google.com with SMTP id\n d9443c01a7336-2b2589c26e3so87797875ad.1\n for ; Sun, 26 Apr 2026 06:41:04 -0700 (PDT)","from stoup.. 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helo=mail-pl1-x62e.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Use parts64_float_to_sint_modulo at each call site.\n\nThat leaves parts128_float_to_sint_modulo unused,\nso move the whole function back to softfloat.c and\nspecialize for FloatParts64.\n\nSigned-off-by: Richard Henderson \n---\n fpu/softfloat.c | 84 +++++++++++++++++++++++++++++++++------\n fpu/softfloat-parts.c.inc | 79 ------------------------------------\n 2 files changed, 72 insertions(+), 91 deletions(-)","diff":"diff --git a/fpu/softfloat.c b/fpu/softfloat.c\nindex 869b592cd0..0b2638c34b 100644\n--- a/fpu/softfloat.c\n+++ b/fpu/softfloat.c\n@@ -779,16 +779,6 @@ static float128 QEMU_FLATTEN float128_pack_raw(const FloatParts128 *p)\n FloatParts128 *: parts128_##NAME, \\\n FloatParts256 *: parts256_##NAME)\n \n-static int64_t parts64_float_to_sint_modulo(FloatParts64 *p,\n- FloatRoundMode rmode,\n- int bitsm1, float_status *s);\n-static int64_t parts128_float_to_sint_modulo(FloatParts128 *p,\n- FloatRoundMode rmode,\n- int bitsm1, float_status *s);\n-\n-#define parts_float_to_sint_modulo(P, R, M, S) \\\n- PARTS_GENERIC_64_128(float_to_sint_modulo, P)(P, R, M, S)\n-\n static void parts64_sint_to_float(FloatParts64 *p, int64_t a,\n int scale, float_status *s);\n static void parts128_sint_to_float(FloatParts128 *p, int64_t a,\n@@ -3558,13 +3548,83 @@ int64_t bfloat16_to_int64_round_to_zero(bfloat16 a, float_status *s)\n return bfloat16_to_int64_scalbn(a, float_round_to_zero, 0, s);\n }\n \n+/*\n+ * Like partsN(float_to_sint), except do not saturate the result.\n+ * Instead, return the rounded unbounded precision two's compliment result,\n+ * modulo 2**(bitsm1 + 1).\n+ */\n+static int64_t parts64_float_to_sint_modulo(FloatParts64 *p,\n+ FloatRoundMode rmode,\n+ int bitsm1, float_status *s)\n+{\n+ int flags = 0;\n+ uint64_t r;\n+ bool overflow = false;\n+\n+ switch (p->cls) {\n+ case float_class_snan:\n+ flags |= float_flag_invalid_snan;\n+ /* fall through */\n+ case float_class_qnan:\n+ flags |= float_flag_invalid;\n+ r = 0;\n+ break;\n+\n+ case float_class_inf:\n+ overflow = true;\n+ r = 0;\n+ break;\n+\n+ case float_class_zero:\n+ return 0;\n+\n+ case float_class_normal:\n+ case float_class_denormal:\n+ /* TODO: 64 - 2 is frac_size for rounding; could use input fmt. */\n+ if (parts64_round_to_int_normal(p, rmode, 0, 64 - 2)) {\n+ flags = float_flag_inexact;\n+ }\n+\n+ if (p->exp <= DECOMPOSED_BINARY_POINT) {\n+ r = p->frac >> (DECOMPOSED_BINARY_POINT - p->exp);\n+ if (p->exp < bitsm1) {\n+ /* Result in range. */\n+ } else if (p->exp == bitsm1) {\n+ /* The only in-range value is INT_MIN. */\n+ overflow = !p->sign || p->frac != DECOMPOSED_IMPLICIT_BIT;\n+ } else {\n+ overflow = true;\n+ }\n+ } else {\n+ /* Overflow, but there might still be bits to return. */\n+ int shl = p->exp - DECOMPOSED_BINARY_POINT;\n+ r = (shl < 64 ? p->frac << shl : 0);\n+ overflow = true;\n+ }\n+\n+ if (p->sign) {\n+ r = -r;\n+ }\n+ break;\n+\n+ default:\n+ g_assert_not_reached();\n+ }\n+\n+ if (overflow) {\n+ flags = float_flag_invalid | float_flag_invalid_cvti;\n+ }\n+ float_raise(flags, s);\n+ return r;\n+}\n+\n int32_t float64_to_int32_modulo(float64 a, FloatRoundMode rmode,\n float_status *s)\n {\n FloatParts64 p;\n \n float64_unpack_canonical(&p, a, s);\n- return parts_float_to_sint_modulo(&p, rmode, 31, s);\n+ return parts64_float_to_sint_modulo(&p, rmode, 31, s);\n }\n \n int64_t float64_to_int64_modulo(float64 a, FloatRoundMode rmode,\n@@ -3573,7 +3633,7 @@ int64_t float64_to_int64_modulo(float64 a, FloatRoundMode rmode,\n FloatParts64 p;\n \n float64_unpack_canonical(&p, a, s);\n- return parts_float_to_sint_modulo(&p, rmode, 63, s);\n+ return parts64_float_to_sint_modulo(&p, rmode, 63, s);\n }\n \n /*\ndiff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc\nindex 9b719ac5cf..d8eb9f5b78 100644\n--- a/fpu/softfloat-parts.c.inc\n+++ b/fpu/softfloat-parts.c.inc\n@@ -1415,85 +1415,6 @@ static uint64_t partsN(float_to_uint)(FloatPartsN *p, FloatRoundMode rmode,\n return r;\n }\n \n-/*\n- * Like partsN(float_to_sint), except do not saturate the result.\n- * Instead, return the rounded unbounded precision two's compliment result,\n- * modulo 2**(bitsm1 + 1).\n- */\n-static int64_t partsN(float_to_sint_modulo)(FloatPartsN *p,\n- FloatRoundMode rmode,\n- int bitsm1, float_status *s)\n-{\n- int flags = 0;\n- uint64_t r;\n- bool overflow = false;\n-\n- switch (p->cls) {\n- case float_class_snan:\n- flags |= float_flag_invalid_snan;\n- /* fall through */\n- case float_class_qnan:\n- flags |= float_flag_invalid;\n- r = 0;\n- break;\n-\n- case float_class_inf:\n- overflow = true;\n- r = 0;\n- break;\n-\n- case float_class_zero:\n- return 0;\n-\n- case float_class_normal:\n- case float_class_denormal:\n- /* TODO: N - 2 is frac_size for rounding; could use input fmt. */\n- if (partsN(round_to_int_normal)(p, rmode, 0, N - 2)) {\n- flags = float_flag_inexact;\n- }\n-\n- if (p->exp <= DECOMPOSED_BINARY_POINT) {\n- /*\n- * Because we rounded to integral, and exp < 64,\n- * we know frac_low is zero.\n- */\n- r = p->frac_hi >> (DECOMPOSED_BINARY_POINT - p->exp);\n- if (p->exp < bitsm1) {\n- /* Result in range. */\n- } else if (p->exp == bitsm1) {\n- /* The only in-range value is INT_MIN. */\n- overflow = !p->sign || p->frac_hi != DECOMPOSED_IMPLICIT_BIT;\n- } else {\n- overflow = true;\n- }\n- } else {\n- /* Overflow, but there might still be bits to return. */\n- int shl = p->exp - DECOMPOSED_BINARY_POINT;\n- if (shl < N) {\n- frac_shl(p, shl);\n- r = p->frac_hi;\n- } else {\n- r = 0;\n- }\n- overflow = true;\n- }\n-\n- if (p->sign) {\n- r = -r;\n- }\n- break;\n-\n- default:\n- g_assert_not_reached();\n- }\n-\n- if (overflow) {\n- flags = float_flag_invalid | float_flag_invalid_cvti;\n- }\n- float_raise(flags, s);\n- return r;\n-}\n-\n /*\n * Integer to float conversions\n *\n","prefixes":["21/84"]}