{"id":2228464,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2228464/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260426134002.865628-84-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260426134002.865628-84-richard.henderson@linaro.org>","date":"2026-04-26T13:40:00","name":"[83/84] target/arm: Drop oddstatus from is_ebf and bfdotadd_ebf","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"d68f545b92313deef0e3fb6d5f5380abdd82fc5c","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.1/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260426134002.865628-84-richard.henderson@linaro.org/mbox/","series":[{"id":501533,"url":"http://patchwork.ozlabs.org/api/1.1/series/501533/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501533","date":"2026-04-26T13:38:37","name":"fpu: Export some internals for targets","version":1,"mbox":"http://patchwork.ozlabs.org/series/501533/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2228464/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2228464/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=GXDlAH7e;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g3Sry1nvWz1xvV\n\tfor ; Sun, 26 Apr 2026 23:55:46 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wGzsj-00009a-Py; Sun, 26 Apr 2026 09:50:46 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wGzs4-00078m-0k\n for qemu-devel@nongnu.org; Sun, 26 Apr 2026 09:50:05 -0400","from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wGzs1-0002th-62\n for qemu-devel@nongnu.org; Sun, 26 Apr 2026 09:50:03 -0400","by mail-pf1-x436.google.com with SMTP id\n d2e1a72fcca58-82fbf5d4dc2so5614769b3a.1\n for ; Sun, 26 Apr 2026 06:50:00 -0700 (PDT)","from stoup.. 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helo=mail-pf1-x436.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"This argument is no longer used.\n\nSigned-off-by: Richard Henderson \n---\n target/arm/tcg/vec_internal.h | 12 +++------\n target/arm/tcg/sme_helper.c | 6 ++---\n target/arm/tcg/vec_helper.c | 50 +++++++++++++++--------------------\n 3 files changed, 29 insertions(+), 39 deletions(-)","diff":"diff --git a/target/arm/tcg/vec_internal.h b/target/arm/tcg/vec_internal.h\nindex 4edd2b4fc1..c7ccb28b18 100644\n--- a/target/arm/tcg/vec_internal.h\n+++ b/target/arm/tcg/vec_internal.h\n@@ -270,7 +270,6 @@ float32 bfdotadd(float32 sum, uint32_t e1, uint32_t e2, float_status *fpst);\n * @sum: addend\n * @e1, @e2: multiplicand vectors\n * @fpst: floating-point status to use\n- * @fpst_odd: floating-point status to use for round-to-odd operations\n *\n * BFloat16 2-way dot product of @e1 & @e2, accumulating with @sum.\n * The @e1 and @e2 operands correspond to the 32-bit source vector\n@@ -279,23 +278,20 @@ float32 bfdotadd(float32 sum, uint32_t e1, uint32_t e2, float_status *fpst);\n * Corresponds to the ARM pseudocode function BFDotAdd, specialized\n * for the FPCR.EBF == 1 case.\n */\n-float32 bfdotadd_ebf(float32 sum, uint32_t e1, uint32_t e2,\n- float_status *fpst, float_status *fpst_odd);\n+float32 bfdotadd_ebf(float32 sum, uint32_t e1, uint32_t e2, float_status *fpst);\n \n /**\n * is_ebf:\n * @env: CPU state\n * @statusp: pointer to floating point status to fill in\n- * @oddstatusp: pointer to floating point status to fill in for round-to-odd\n *\n * Determine whether a BFDotAdd operation should use FPCR.EBF = 0\n- * or FPCR.EBF = 1 semantics. On return, has initialized *statusp\n- * and *oddstatusp to suitable float_status arguments to use with either\n- * bfdotadd() or bfdotadd_ebf().\n+ * or FPCR.EBF = 1 semantics. On return, has initialized *statusp as suitable\n+ * for float_status arguments to either bfdotadd() or bfdotadd_ebf().\n * Returns true for EBF = 1, false for EBF = 0. (The caller should use this\n * to decide whether to call bfdotadd() or bfdotadd_ebf().)\n */\n-bool is_ebf(CPUARMState *env, float_status *statusp, float_status *oddstatusp);\n+bool is_ebf(CPUARMState *env, float_status *statusp);\n \n /*\n * Negate as for FPCR.AH=1 -- do not negate NaNs.\ndiff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c\nindex ab5999c592..0702a1b129 100644\n--- a/target/arm/tcg/sme_helper.c\n+++ b/target/arm/tcg/sme_helper.c\n@@ -1435,9 +1435,9 @@ static void do_bfmopa_w(void *vza, void *vzn, void *vzm,\n uint32_t desc, uint32_t negx, bool ah_neg)\n {\n intptr_t row, col, oprsz = simd_maxsz(desc);\n- float_status fpst, fpst_odd;\n+ float_status fpst;\n \n- if (is_ebf(env, &fpst, &fpst_odd)) {\n+ if (is_ebf(env, &fpst)) {\n for (row = 0; row < oprsz; ) {\n uint16_t prow = pn[H2(row >> 4)];\n do {\n@@ -1458,7 +1458,7 @@ static void do_bfmopa_w(void *vza, void *vzn, void *vzm,\n uint32_t m = *(uint32_t *)(vzm + H1_4(col));\n \n m = f16mop_adj_pair(m, pcol, 0);\n- *a = bfdotadd_ebf(*a, n, m, &fpst, &fpst_odd);\n+ *a = bfdotadd_ebf(*a, n, m, &fpst);\n }\n col += 4;\n pcol >>= 4;\ndiff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c\nindex 1f305515cf..d004be5e1b 100644\n--- a/target/arm/tcg/vec_helper.c\n+++ b/target/arm/tcg/vec_helper.c\n@@ -2845,7 +2845,7 @@ DO_MMLA_B(gvec_usmmla_b, do_usmmla_b)\n * BFloat16 Dot Product\n */\n \n-bool is_ebf(CPUARMState *env, float_status *statusp, float_status *oddstatusp)\n+bool is_ebf(CPUARMState *env, float_status *statusp)\n {\n /*\n * For BFDOT, BFMMLA, etc, the behaviour depends on FPCR.EBF.\n@@ -2865,11 +2865,7 @@ bool is_ebf(CPUARMState *env, float_status *statusp, float_status *oddstatusp)\n *statusp = env->vfp.fp_status[is_a64(env) ? FPST_A64 : FPST_A32];\n set_default_nan_mode(true, statusp);\n \n- if (ebf) {\n- /* EBF=1 needs to do a step with round-to-odd semantics */\n- *oddstatusp = *statusp;\n- set_float_rounding_mode(float_round_to_odd, oddstatusp);\n- } else {\n+ if (!ebf) {\n set_flush_to_zero(true, statusp);\n set_flush_inputs_to_zero(true, statusp);\n set_float_rounding_mode(float_round_to_odd_inf, statusp);\n@@ -2893,8 +2889,7 @@ float32 bfdotadd(float32 sum, uint32_t e1, uint32_t e2, float_status *fpst)\n return t1;\n }\n \n-float32 bfdotadd_ebf(float32 sum, uint32_t e1, uint32_t e2,\n- float_status *fpst, float_status *fpst_odd)\n+float32 bfdotadd_ebf(float32 sum, uint32_t e1, uint32_t e2, float_status *fpst)\n {\n /* Unpack two BFloat16 into two Float32, trivially. */\n float32 s1r = e1 << 16;\n@@ -2965,11 +2960,11 @@ void HELPER(gvec_bfdot)(void *vd, void *vn, void *vm, void *va,\n intptr_t i, opr_sz = simd_oprsz(desc);\n float32 *d = vd, *a = va;\n uint32_t *n = vn, *m = vm;\n- float_status fpst, fpst_odd;\n+ float_status fpst;\n \n- if (is_ebf(env, &fpst, &fpst_odd)) {\n+ if (is_ebf(env, &fpst)) {\n for (i = 0; i < opr_sz / 4; ++i) {\n- d[i] = bfdotadd_ebf(a[i], n[i], m[i], &fpst, &fpst_odd);\n+ d[i] = bfdotadd_ebf(a[i], n[i], m[i], &fpst);\n }\n } else {\n for (i = 0; i < opr_sz / 4; ++i) {\n@@ -2988,14 +2983,14 @@ void HELPER(gvec_bfdot_idx)(void *vd, void *vn, void *vm,\n intptr_t eltspersegment = MIN(16 / 4, elements);\n float32 *d = vd, *a = va;\n uint32_t *n = vn, *m = vm;\n- float_status fpst, fpst_odd;\n+ float_status fpst;\n \n- if (is_ebf(env, &fpst, &fpst_odd)) {\n+ if (is_ebf(env, &fpst)) {\n for (i = 0; i < elements; i += eltspersegment) {\n uint32_t m_idx = m[i + H4(index)];\n \n for (j = i; j < i + eltspersegment; j++) {\n- d[j] = bfdotadd_ebf(a[j], n[j], m_idx, &fpst, &fpst_odd);\n+ d[j] = bfdotadd_ebf(a[j], n[j], m_idx, &fpst);\n }\n }\n } else {\n@@ -3022,17 +3017,16 @@ void HELPER(sme2_bfvdot_idx)(void *vd, void *vn, void *vm,\n uint16_t *n0 = vn;\n uint16_t *n1 = vn + sizeof(ARMVectorReg);\n uint32_t *m = vm;\n- float_status fpst, fpst_odd;\n+ float_status fpst;\n \n- if (is_ebf(env, &fpst, &fpst_odd)) {\n+ if (is_ebf(env, &fpst)) {\n for (i = 0; i < elements; i += eltspersegment) {\n uint32_t m_idx = m[i + H4(idx)];\n \n for (j = 0; j < eltspersegment; j++) {\n uint32_t nn = (n0[H2(2 * (i + j) + sel)])\n | (n1[H2(2 * (i + j) + sel)] << 16);\n- d[i + H4(j)] = bfdotadd_ebf(a[i + H4(j)], nn, m_idx,\n- &fpst, &fpst_odd);\n+ d[i + H4(j)] = bfdotadd_ebf(a[i + H4(j)], nn, m_idx, &fpst);\n }\n }\n } else {\n@@ -3055,9 +3049,9 @@ void HELPER(gvec_bfmmla)(void *vd, void *vn, void *vm, void *va,\n intptr_t s, opr_sz = simd_oprsz(desc);\n float32 *d = vd, *a = va;\n uint32_t *n = vn, *m = vm;\n- float_status fpst, fpst_odd;\n+ float_status fpst;\n \n- if (is_ebf(env, &fpst, &fpst_odd)) {\n+ if (is_ebf(env, &fpst)) {\n for (s = 0; s < opr_sz / 4; s += 4) {\n float32 sum00, sum01, sum10, sum11;\n \n@@ -3069,20 +3063,20 @@ void HELPER(gvec_bfmmla)(void *vd, void *vn, void *vm, void *va,\n * i j i k j k\n */\n sum00 = a[s + H4(0 + 0)];\n- sum00 = bfdotadd_ebf(sum00, n[s + H4(0 + 0)], m[s + H4(0 + 0)], &fpst, &fpst_odd);\n- sum00 = bfdotadd_ebf(sum00, n[s + H4(0 + 1)], m[s + H4(0 + 1)], &fpst, &fpst_odd);\n+ sum00 = bfdotadd_ebf(sum00, n[s + H4(0 + 0)], m[s + H4(0 + 0)], &fpst);\n+ sum00 = bfdotadd_ebf(sum00, n[s + H4(0 + 1)], m[s + H4(0 + 1)], &fpst);\n \n sum01 = a[s + H4(0 + 1)];\n- sum01 = bfdotadd_ebf(sum01, n[s + H4(0 + 0)], m[s + H4(2 + 0)], &fpst, &fpst_odd);\n- sum01 = bfdotadd_ebf(sum01, n[s + H4(0 + 1)], m[s + H4(2 + 1)], &fpst, &fpst_odd);\n+ sum01 = bfdotadd_ebf(sum01, n[s + H4(0 + 0)], m[s + H4(2 + 0)], &fpst);\n+ sum01 = bfdotadd_ebf(sum01, n[s + H4(0 + 1)], m[s + H4(2 + 1)], &fpst);\n \n sum10 = a[s + H4(2 + 0)];\n- sum10 = bfdotadd_ebf(sum10, n[s + H4(2 + 0)], m[s + H4(0 + 0)], &fpst, &fpst_odd);\n- sum10 = bfdotadd_ebf(sum10, n[s + H4(2 + 1)], m[s + H4(0 + 1)], &fpst, &fpst_odd);\n+ sum10 = bfdotadd_ebf(sum10, n[s + H4(2 + 0)], m[s + H4(0 + 0)], &fpst);\n+ sum10 = bfdotadd_ebf(sum10, n[s + H4(2 + 1)], m[s + H4(0 + 1)], &fpst);\n \n sum11 = a[s + H4(2 + 1)];\n- sum11 = bfdotadd_ebf(sum11, n[s + H4(2 + 0)], m[s + H4(2 + 0)], &fpst, &fpst_odd);\n- sum11 = bfdotadd_ebf(sum11, n[s + H4(2 + 1)], m[s + H4(2 + 1)], &fpst, &fpst_odd);\n+ sum11 = bfdotadd_ebf(sum11, n[s + H4(2 + 0)], m[s + H4(2 + 0)], &fpst);\n+ sum11 = bfdotadd_ebf(sum11, n[s + H4(2 + 1)], m[s + H4(2 + 1)], &fpst);\n \n d[s + H4(0 + 0)] = sum00;\n d[s + H4(0 + 1)] = sum01;\n","prefixes":["83/84"]}