{"id":2228458,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2228458/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260426134002.865628-83-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260426134002.865628-83-richard.henderson@linaro.org>","date":"2026-04-26T13:39:59","name":"[82/84] target/arm: Use FloatParts64 in bfdotadd_ebf","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"08bb30b41c96b52829488219e10669b3ee1fa3bf","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.1/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260426134002.865628-83-richard.henderson@linaro.org/mbox/","series":[{"id":501533,"url":"http://patchwork.ozlabs.org/api/1.1/series/501533/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501533","date":"2026-04-26T13:38:37","name":"fpu: Export some internals for targets","version":1,"mbox":"http://patchwork.ozlabs.org/series/501533/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2228458/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2228458/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=rlYK4HFa;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g3Sp317ZDz1yHg\n\tfor ; Sun, 26 Apr 2026 23:53:15 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wGzsX-0007eO-J8; Sun, 26 Apr 2026 09:50:33 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wGzs1-000763-W4\n for qemu-devel@nongnu.org; Sun, 26 Apr 2026 09:50:05 -0400","from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wGzry-0002sh-1i\n for qemu-devel@nongnu.org; Sun, 26 Apr 2026 09:50:01 -0400","by mail-pf1-x42b.google.com with SMTP id\n d2e1a72fcca58-82f69a286dbso7071144b3a.2\n for ; Sun, 26 Apr 2026 06:49:57 -0700 (PDT)","from stoup.. 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helo=mail-pf1-x42b.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Use softfloat-parts.h so that we can more naturally\nperform the required operations witha single rounding step.\nThis happens to also simplify the NaN detection step.\n\nSigned-off-by: Richard Henderson \n---\n target/arm/tcg/vec_helper.c | 77 +++++++++++++++++++------------------\n 1 file changed, 40 insertions(+), 37 deletions(-)","diff":"diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c\nindex 91e98d28ae..1f305515cf 100644\n--- a/target/arm/tcg/vec_helper.c\n+++ b/target/arm/tcg/vec_helper.c\n@@ -22,6 +22,7 @@\n #include \"helper.h\"\n #include \"tcg/tcg-gvec-desc.h\"\n #include \"fpu/softfloat.h\"\n+#include \"fpu/softfloat-parts.h\"\n #include \"qemu/int128.h\"\n #include \"crypto/clmul.h\"\n #include \"vec_internal.h\"\n@@ -2895,61 +2896,63 @@ float32 bfdotadd(float32 sum, uint32_t e1, uint32_t e2, float_status *fpst)\n float32 bfdotadd_ebf(float32 sum, uint32_t e1, uint32_t e2,\n float_status *fpst, float_status *fpst_odd)\n {\n+ /* Unpack two BFloat16 into two Float32, trivially. */\n float32 s1r = e1 << 16;\n float32 s1c = e1 & 0xffff0000u;\n float32 s2r = e2 << 16;\n float32 s2c = e2 & 0xffff0000u;\n float32 t32;\n \n+ /*\n+ * Compare f16_dotadd() in sme_helper.c, but here we have\n+ * bfloat16 inputs. In particular that means that we do not\n+ * want the FPCR.FZ16 flush semantics, so we use the normal\n+ * float_status for the input handling here.\n+ */\n+ FloatParts64 p1r = float32_unpack_canonical(s1r, fpst);\n+ FloatParts64 p1c = float32_unpack_canonical(s1c, fpst);\n+ FloatParts64 p2r = float32_unpack_canonical(s2r, fpst);\n+ FloatParts64 p2c = float32_unpack_canonical(s2c, fpst);\n+\n+ int all_mask = (float_cmask(p1r.cls) | float_cmask(p1c.cls) |\n+ float_cmask(p1r.cls) | float_cmask(p1c.cls));\n+\n /* C.f. FPProcessNaNs4 */\n- if (float32_is_any_nan(s1r) || float32_is_any_nan(s1c) ||\n- float32_is_any_nan(s2r) || float32_is_any_nan(s2c)) {\n- if (float32_is_signaling_nan(s1r, fpst)) {\n- t32 = s1r;\n- } else if (float32_is_signaling_nan(s1c, fpst)) {\n- t32 = s1c;\n- } else if (float32_is_signaling_nan(s2r, fpst)) {\n- t32 = s2r;\n- } else if (float32_is_signaling_nan(s2c, fpst)) {\n- t32 = s2c;\n- } else if (float32_is_any_nan(s1r)) {\n- t32 = s1r;\n- } else if (float32_is_any_nan(s1c)) {\n- t32 = s1c;\n- } else if (float32_is_any_nan(s2r)) {\n- t32 = s2r;\n+ if (unlikely(all_mask & float_cmask_anynan)) {\n+ if (unlikely(all_mask & float_cmask_snan)) {\n+ if (p1r.cls == float_class_snan) {\n+ t32 = s1r;\n+ } else if (p1c.cls == float_class_snan) {\n+ t32 = s1c;\n+ } else if (p2r.cls == float_class_snan) {\n+ t32 = s2r;\n+ } else {\n+ t32 = s2c;\n+ }\n } else {\n- t32 = s2c;\n+ if (p1r.cls == float_class_qnan) {\n+ t32 = s1r;\n+ } else if (p1c.cls == float_class_qnan) {\n+ t32 = s1c;\n+ } else if (p2r.cls == float_class_qnan) {\n+ t32 = s2r;\n+ } else {\n+ t32 = s2c;\n+ }\n }\n /*\n * FPConvertNaN(FPProcessNaN(t32)) will be done as part\n * of the final addition below.\n */\n } else {\n- /*\n- * Compare f16_dotadd() in sme_helper.c, but here we have\n- * bfloat16 inputs. In particular that means that we do not\n- * want the FPCR.FZ16 flush semantics, so we use the normal\n- * float_status for the input handling here.\n- */\n- float64 e1r = float32_to_float64(s1r, fpst);\n- float64 e1c = float32_to_float64(s1c, fpst);\n- float64 e2r = float32_to_float64(s2r, fpst);\n- float64 e2c = float32_to_float64(s2c, fpst);\n- float64 t64;\n-\n /*\n * The ARM pseudocode function FPDot performs both multiplies\n- * and the add with a single rounding operation. Emulate this\n- * by performing the first multiply in round-to-odd, then doing\n- * the second multiply as fused multiply-add, and rounding to\n- * float32 all in one step.\n+ * and the add with a single rounding operation.\n */\n- t64 = float64_mul(e1r, e2r, fpst_odd);\n- t64 = float64r32_muladd(e1c, e2c, t64, 0, fpst);\n+ FloatParts64 tmp = parts64_mul(&p1r, &p2r, fpst);\n+ tmp = parts64_muladd_scalbn(&p1c, &p2c, &tmp, 0, 0, fpst);\n \n- /* This conversion is exact, because we've already rounded. */\n- t32 = float64_to_float32(t64, fpst);\n+ t32 = float32_round_pack_canonical(&tmp, fpst);\n }\n \n /* The final accumulation step is not fused. */\n","prefixes":["82/84"]}