{"id":2228451,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2228451/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260426134002.865628-61-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260426134002.865628-61-richard.henderson@linaro.org>","date":"2026-04-26T13:39:37","name":"[60/84] fpu: Return struct from parts{64,128}_default_nan","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"ad22b6593594d8788fdd822236ed0f2fd51a864a","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.1/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260426134002.865628-61-richard.henderson@linaro.org/mbox/","series":[{"id":501533,"url":"http://patchwork.ozlabs.org/api/1.1/series/501533/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501533","date":"2026-04-26T13:38:37","name":"fpu: Export some internals for targets","version":1,"mbox":"http://patchwork.ozlabs.org/series/501533/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2228451/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2228451/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=q5rEP9rI;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g3SmJ6lNQz1yJ1\n\tfor ; Sun, 26 Apr 2026 23:51:43 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wGzpX-00083K-Ua; Sun, 26 Apr 2026 09:47:27 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wGzoG-0005wR-PJ\n for qemu-devel@nongnu.org; Sun, 26 Apr 2026 09:46:11 -0400","from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wGzoD-0001WH-GC\n for qemu-devel@nongnu.org; Sun, 26 Apr 2026 09:46:08 -0400","by mail-pl1-x62e.google.com with SMTP id\n d9443c01a7336-2b4583f0a1aso58280925ad.3\n for ; Sun, 26 Apr 2026 06:45:54 -0700 (PDT)","from stoup.. ([180.233.125.15]) by smtp.gmail.com with ESMTPSA id\n d9443c01a7336-2b5faa34ea7sm280544085ad.34.2026.04.26.06.45.51\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Sun, 26 Apr 2026 06:45:52 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=linaro.org; s=google; t=1777211153; x=1777815953; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=TnxSC/joRQiFHOM0JVKPwA6B6Eb0DecPwNp7R0mi00U=;\n b=q5rEP9rIjySiXDFcrgkOjFSKSt49NaUDNCDQ0eJptOaFZnLGnQF0xiJjbEfPAok4AE\n hJD96koCzhSnEbR2HavJNnVxKrt2aAA9W+g8ldTMhSLkArqeg+syPot8kTkQHxyNETCy\n R7r2FCUYuxeROYgFOtJDKKC66WvKaopx5ZO6GZICy2Cmofy4pujcr8mSF4wKIup6+wje\n d3AEY6QhCjSBQn2KKqYb7OdLSlijhNcXl0FWTLEK2/FX4qofeLg2k+GQgOhRFFMe/yv9\n zfyZmIc/ZGszAiR1vdQgc5GJvLsKEwGU2o/YKIfrSLo4F7N0xN7suntPh/TQOF1leb5c\n M6fQ==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1777211153; x=1777815953;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=TnxSC/joRQiFHOM0JVKPwA6B6Eb0DecPwNp7R0mi00U=;\n b=LfaEsCV6uOP6pwIcZk6+BCvEQMuDCmfvpwGMVmrgie+t7GlNS28Sy4sFyg0d1H9NoS\n gyjnWd3ohNZIp8ZqrBg2vPqq1hHjWsu015vopEk4aPEbMlZpCrhUew+p9GtE2N+n4IEu\n b9ucoGGwASjv6DmwrQL094s00S4lbe9v7ceOFQedxNvEjZV7nH9TvhmyVPfVi3U12k/2\n js6FQ4iATD1i94gNoWBEvl+T5xXAYXVH+/2+ZEkwlihNvNFzgn0nEj7i48qe5Z4qak+a\n yUM8OK3533HZ4tUbPvU8OR20ITPQ/jmxzKbFpwHLQNWIWC5vpC99soLTT8RLM5eP/K18\n UGAw==","X-Gm-Message-State":"AOJu0Ywy1xQrYFq0xfG1Vs2vD8NYyzEkQR2ay17ILH75lGbG/u2LcGgp\n OXN7s3rKltUyY+LRmc+HxJOHKUMxHsVj2T/HFDO6+hPls62GhBfp5N7s82L110gd2lFvwJOz8t9\n cXtLnZTE=","X-Gm-Gg":"AeBDies4JIYGqgh7v0k/d/aJJn0GKiSHhb3Q4KLRJMABVGMYPRnBxlkZF3rXxhevJcl\n Vr2jOpS5vM97VBji884n6VN54l8mtk83w/nBDpV+C/lAW1ykRqFQO/4OcTKBeMBwvLmxEv/dAyK\n AHXOzDstBvdpXRrqxUlwMFFKsZhIl1Ci7fpRmFpIjpGOeL/D8a49PGOd+qawAemGsfkTKd+l2xz\n FiJ4D08Nn5SmIqwGUPLlpFQ622alDPuFpLT6I+lqF79LzfzRHt5Xe/SXBeBRUdBYY8+sV5IpMz0\n dGlXdZ3KJrsCiT0p/6kmg/oyZ5RRaR8NBIXgAKZ4lJsNYXDjRwhSV8Ylw6RH7ftBNNG5/He82Xw\n /uzb1qZzsGxJ6hpYb5pSUnzE1ikPiEXcVC1Csf3hfIJFfaHgjQ+lhZPltChqLJPixPQHJkR8SmG\n k41CrcPcS45X3Drakp80EozoQVtCRM3EochGAHHH9R","X-Received":"by 2002:a17:902:d501:b0:2b2:5099:2f3e with SMTP id\n d9443c01a7336-2b5f9e7be29mr431590505ad.4.1777211153289;\n Sun, 26 Apr 2026 06:45:53 -0700 (PDT)","From":"Richard Henderson ","To":"qemu-devel@nongnu.org","Cc":"qemu-arm@nongnu.org,\n\tqemu-s390x@nongnu.org","Subject":"[PATCH 60/84] fpu: Return struct from parts{64,128}_default_nan","Date":"Sun, 26 Apr 2026 23:39:37 +1000","Message-ID":"<20260426134002.865628-61-richard.henderson@linaro.org>","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"<20260426134002.865628-1-richard.henderson@linaro.org>","References":"<20260426134002.865628-1-richard.henderson@linaro.org>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2607:f8b0:4864:20::62e;\n envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Signed-off-by: Richard Henderson \n---\n fpu/softfloat.c | 29 ++++++++++++-----------------\n fpu/softfloat-parts.c.inc | 22 +++++++++++-----------\n fpu/softfloat-specialize.c.inc | 22 ++++++++++------------\n 3 files changed, 33 insertions(+), 40 deletions(-)","diff":"diff --git a/fpu/softfloat.c b/fpu/softfloat.c\nindex b857c13d91..fa8913a288 100644\n--- a/fpu/softfloat.c\n+++ b/fpu/softfloat.c\n@@ -2678,7 +2678,7 @@ float32 floatx80_to_float32(floatx80 a, float_status *s)\n if (floatx80_unpack_canonical(&p128, a, s)) {\n p64 = parts128_to_parts64(&p128, s);\n } else {\n- parts64_default_nan(&p64, s);\n+ p64 = parts64_default_nan(s);\n }\n return float32_round_pack_canonical(&p64, s);\n }\n@@ -2691,7 +2691,7 @@ float64 floatx80_to_float64(floatx80 a, float_status *s)\n if (floatx80_unpack_canonical(&p128, a, s)) {\n p64 = parts128_to_parts64(&p128, s);\n } else {\n- parts64_default_nan(&p64, s);\n+ p64 = parts64_default_nan(s);\n }\n return float64_round_pack_canonical(&p64, s);\n }\n@@ -2703,7 +2703,7 @@ float128 floatx80_to_float128(floatx80 a, float_status *s)\n if (floatx80_unpack_canonical(&p, a, s)) {\n parts128_float_to_float(&p, s);\n } else {\n- parts128_default_nan(&p, s);\n+ p = parts128_default_nan(s);\n }\n return float128_round_pack_canonical(&p, s);\n }\n@@ -2964,7 +2964,7 @@ static int32_t floatx80_to_int32_scalbn(floatx80 a, FloatRoundMode rmode,\n FloatParts128 p;\n \n if (!floatx80_unpack_canonical(&p, a, s)) {\n- parts128_default_nan(&p, s);\n+ p = parts128_default_nan(s);\n }\n return parts128_float_to_sint(&p, rmode, scale, INT32_MIN, INT32_MAX, s);\n }\n@@ -2975,7 +2975,7 @@ static int64_t floatx80_to_int64_scalbn(floatx80 a, FloatRoundMode rmode,\n FloatParts128 p;\n \n if (!floatx80_unpack_canonical(&p, a, s)) {\n- parts128_default_nan(&p, s);\n+ p = parts128_default_nan(s);\n }\n return parts128_float_to_sint(&p, rmode, scale, INT64_MIN, INT64_MAX, s);\n }\n@@ -4562,7 +4562,7 @@ static void parts64_log2(FloatParts64 *a, float_status *s, const FloatFmt *fmt)\n \n d_nan:\n float_raise(float_flag_invalid, s);\n- parts64_default_nan(a, s);\n+ *a = parts64_default_nan(s);\n }\n \n float32 float32_log2(float32 a, float_status *status)\n@@ -4587,45 +4587,40 @@ float64 float64_log2(float64 a, float_status *status)\n \n float16 float16_default_nan(float_status *status)\n {\n- FloatParts64 p;\n+ FloatParts64 p = parts64_default_nan(status);\n \n- parts64_default_nan(&p, status);\n p.frac >>= float16_params.frac_shift;\n return pack_raw64(&p, &float16_params);\n }\n \n float32 float32_default_nan(float_status *status)\n {\n- FloatParts64 p;\n+ FloatParts64 p = parts64_default_nan(status);\n \n- parts64_default_nan(&p, status);\n p.frac >>= float32_params.frac_shift;\n return pack_raw64(&p, &float32_params);\n }\n \n float64 float64_default_nan(float_status *status)\n {\n- FloatParts64 p;\n+ FloatParts64 p = parts64_default_nan(status);\n \n- parts64_default_nan(&p, status);\n p.frac >>= float64_params.frac_shift;\n return pack_raw64(&p, &float64_params);\n }\n \n float128 float128_default_nan(float_status *status)\n {\n- FloatParts128 p;\n+ FloatParts128 p = parts128_default_nan(status);\n \n- parts128_default_nan(&p, status);\n frac128_shr(&p, float128_params.frac_shift);\n return float128_pack_raw(&p);\n }\n \n bfloat16 bfloat16_default_nan(float_status *status)\n {\n- FloatParts64 p;\n+ FloatParts64 p = parts64_default_nan(status);\n \n- parts64_default_nan(&p, status);\n p.frac >>= bfloat16_params.frac_shift;\n return pack_raw64(&p, &bfloat16_params);\n }\n@@ -5131,7 +5126,7 @@ static void parts_s390_divide_to_integer(FloatParts64 *a, FloatParts64 *b,\n *n = *r;\n *cc = 1;\n } else if (a->cls == float_class_inf || b->cls == float_class_zero) {\n- parts64_default_nan(r, status);\n+ *r = parts64_default_nan(status);\n *n = *r;\n *cc = 1;\n status->float_exception_flags |= float_flag_invalid;\ndiff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc\nindex 5d344f9afe..ed7080d886 100644\n--- a/fpu/softfloat-parts.c.inc\n+++ b/fpu/softfloat-parts.c.inc\n@@ -21,14 +21,14 @@ static void partsN(return_nan)(FloatPartsN *a, float_status *s)\n case float_class_snan:\n float_raise(float_flag_invalid | float_flag_invalid_snan, s);\n if (s->default_nan_mode) {\n- partsN(default_nan)(a, s);\n+ *a = partsN(default_nan)(s);\n } else {\n partsN(silence_nan)(a, s);\n }\n break;\n case float_class_qnan:\n if (s->default_nan_mode) {\n- partsN(default_nan)(a, s);\n+ *a = partsN(default_nan)(s);\n }\n break;\n default:\n@@ -49,7 +49,7 @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,\n }\n \n if (s->default_nan_mode) {\n- partsN(default_nan)(a, s);\n+ *a = partsN(default_nan)(s);\n return a;\n }\n \n@@ -184,7 +184,7 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,\n return ret;\n \n default_nan:\n- partsN(default_nan)(a, s);\n+ *a = partsN(default_nan)(s);\n return a;\n }\n \n@@ -281,7 +281,7 @@ static void partsN(uncanon_e4m3_overflow)(FloatPartsN *p, float_status *s,\n p->exp = fmt->exp_max;\n p->frac_hi = E4M3_NORMAL_FRAC_MAX;\n } else {\n- partsN(default_nan)(p, s);\n+ *p = partsN(default_nan)(s);\n }\n }\n \n@@ -568,7 +568,7 @@ static FloatPartsN *partsN(addsub)(FloatPartsN *a, FloatPartsN *b,\n }\n /* Inf - Inf */\n float_raise(float_flag_invalid | float_flag_invalid_isi, s);\n- partsN(default_nan)(a, s);\n+ *a = partsN(default_nan)(s);\n return a;\n }\n } else {\n@@ -641,7 +641,7 @@ static FloatPartsN *partsN(mul)(FloatPartsN *a, FloatPartsN *b,\n /* Inf * Zero == NaN */\n if (unlikely(ab_mask == float_cmask_infzero)) {\n float_raise(float_flag_invalid | float_flag_invalid_imz, s);\n- partsN(default_nan)(a, s);\n+ *a = partsN(default_nan)(s);\n return a;\n }\n \n@@ -796,7 +796,7 @@ static FloatPartsN *partsN(muladd_scalbn)(FloatPartsN *a, FloatPartsN *b,\n goto finish_sign;\n \n d_nan:\n- partsN(default_nan)(a, s);\n+ *a = partsN(default_nan)(s);\n return a;\n }\n \n@@ -864,7 +864,7 @@ static FloatPartsN *partsN(div)(FloatPartsN *a, FloatPartsN *b,\n return a;\n \n d_nan:\n- partsN(default_nan)(a, s);\n+ *a = partsN(default_nan)(s);\n return a;\n }\n \n@@ -896,7 +896,7 @@ static FloatPartsN *partsN(modrem)(FloatPartsN *a, FloatPartsN *b,\n /* Inf % N; N % 0 */\n if (a->cls == float_class_inf || b->cls == float_class_zero) {\n float_raise(float_flag_invalid, s);\n- partsN(default_nan)(a, s);\n+ *a = partsN(default_nan)(s);\n return a;\n }\n \n@@ -1118,7 +1118,7 @@ static void partsN(sqrt)(FloatPartsN *a, float_status *status,\n \n d_nan:\n float_raise(float_flag_invalid | float_flag_invalid_sqrt, status);\n- partsN(default_nan)(a, status);\n+ *a = partsN(default_nan)(status);\n }\n \n /*\ndiff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc\nindex 9ed968c79b..dd65432813 100644\n--- a/fpu/softfloat-specialize.c.inc\n+++ b/fpu/softfloat-specialize.c.inc\n@@ -118,7 +118,7 @@ static bool parts_is_snan_frac(uint64_t frac, float_status *status)\n | The pattern for a default generated deconstructed floating-point NaN.\n *----------------------------------------------------------------------------*/\n \n-static void parts64_default_nan(FloatParts64 *p, float_status *status)\n+static FloatParts64 parts64_default_nan(float_status *status)\n {\n bool sign = 0;\n uint64_t frac;\n@@ -134,7 +134,7 @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)\n frac = deposit64(0, DECOMPOSED_BINARY_POINT - 7, 7, dnan_pattern);\n frac = deposit64(frac, 0, DECOMPOSED_BINARY_POINT - 7, -(dnan_pattern & 1));\n \n- *p = (FloatParts64) {\n+ return (FloatParts64) {\n .cls = float_class_qnan,\n .sign = sign,\n .exp = INT_MAX,\n@@ -142,17 +142,16 @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)\n };\n }\n \n-static void parts128_default_nan(FloatParts128 *p, float_status *status)\n+static FloatParts128 parts128_default_nan(float_status *status)\n {\n /*\n * Extrapolate from the choices made by parts64_default_nan to fill\n * in the quad-floating format. If the low bit is set, assume we\n * want to set all non-snan bits.\n */\n- FloatParts64 p64;\n- parts64_default_nan(&p64, status);\n+ FloatParts64 p64 = parts64_default_nan(status);\n \n- *p = (FloatParts128) {\n+ return (FloatParts128) {\n .cls = float_class_qnan,\n .sign = p64.sign,\n .exp = INT_MAX,\n@@ -197,19 +196,18 @@ static void parts128_silence_nan(FloatParts128 *p, float_status *status)\n *----------------------------------------------------------------------------*/\n floatx80 floatx80_default_nan(float_status *status)\n {\n- floatx80 r;\n /*\n * Extrapolate from the choices made by parts64_default_nan to fill\n * in the floatx80 format. We assume that floatx80's explicit\n * integer bit is always set (this is true for i386 and m68k,\n * which are the only real users of this format).\n */\n- FloatParts64 p64;\n- parts64_default_nan(&p64, status);\n+ FloatParts64 p64 = parts64_default_nan(status);\n \n- r.high = 0x7FFF | (p64.sign << 15);\n- r.low = (1ULL << DECOMPOSED_BINARY_POINT) | p64.frac;\n- return r;\n+ return (floatx80) {\n+ .high = 0x7FFF | (p64.sign << 15),\n+ .low = (1ULL << DECOMPOSED_BINARY_POINT) | p64.frac,\n+ };\n }\n \n /*----------------------------------------------------------------------------\n","prefixes":["60/84"]}