{"id":2228450,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2228450/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260426134002.865628-73-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260426134002.865628-73-richard.henderson@linaro.org>","date":"2026-04-26T13:39:49","name":"[72/84] fpu: Return struct from parts{64,128}_pick_nan_muladd","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"988b8910d948c4c55fd3e700d954187bd6072bae","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.1/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260426134002.865628-73-richard.henderson@linaro.org/mbox/","series":[{"id":501533,"url":"http://patchwork.ozlabs.org/api/1.1/series/501533/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501533","date":"2026-04-26T13:38:37","name":"fpu: Export some internals for targets","version":1,"mbox":"http://patchwork.ozlabs.org/series/501533/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2228450/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2228450/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=Z3z6DUAv;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g3SmJ6pV5z1yJJ\n\tfor ; Sun, 26 Apr 2026 23:51:43 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wGzpb-0008UC-FG; Sun, 26 Apr 2026 09:47:31 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wGzoZ-00069y-Uw\n for qemu-devel@nongnu.org; Sun, 26 Apr 2026 09:46:29 -0400","from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wGzoY-0001f1-3O\n for qemu-devel@nongnu.org; Sun, 26 Apr 2026 09:46:27 -0400","by mail-pj1-x1034.google.com with SMTP id\n 98e67ed59e1d1-35d9f68d011so6121888a91.2\n for ; Sun, 26 Apr 2026 06:46:25 -0700 (PDT)","from stoup.. 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helo=mail-pj1-x1034.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Signed-off-by: Richard Henderson \n---\n fpu/softfloat-parts.c.inc | 22 ++++++++++++----------\n 1 file changed, 12 insertions(+), 10 deletions(-)","diff":"diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc\nindex 87460306f4..5eaac357ec 100644\n--- a/fpu/softfloat-parts.c.inc\n+++ b/fpu/softfloat-parts.c.inc\n@@ -114,13 +114,15 @@ FloatPartsN partsN(pick_nan)(const FloatPartsN *a, const FloatPartsN *b,\n return *ret;\n }\n \n-static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,\n- FloatPartsN *c, float_status *s,\n- int ab_mask, int abc_mask)\n+static FloatPartsN partsN(pick_nan_muladd)(const FloatPartsN *a,\n+ const FloatPartsN *b,\n+ const FloatPartsN *c,\n+ float_status *s,\n+ int ab_mask, int abc_mask)\n {\n bool infzero = (ab_mask == float_cmask_infzero);\n bool have_snan = (abc_mask & float_cmask_snan);\n- FloatPartsN *ret;\n+ const FloatPartsN *ret;\n \n if (unlikely(have_snan)) {\n float_raise(float_flag_invalid | float_flag_invalid_snan, s);\n@@ -160,7 +162,7 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,\n }\n ret = c;\n } else {\n- FloatPartsN *val[R_3NAN_1ST_MASK + 1] = { a, b, c };\n+ const FloatPartsN *val[R_3NAN_1ST_MASK + 1] = { a, b, c };\n Float3NaNPropRule rule = s->float_3nan_prop_rule;\n \n assert(rule != float_3nan_prop_none);\n@@ -179,13 +181,12 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,\n }\n \n if (is_snan(ret->cls)) {\n- *ret = partsN(silence_nan)(ret, s);\n+ return partsN(silence_nan)(ret, s);\n }\n- return ret;\n+ return *ret;\n \n default_nan:\n- *a = partsN(default_nan)(s);\n- return a;\n+ return partsN(default_nan)(s);\n }\n \n /*\n@@ -698,7 +699,8 @@ static FloatPartsN *partsN(muladd_scalbn)(FloatPartsN *a, FloatPartsN *b,\n * off to the target-specific pick-a-NaN routine.\n */\n if (unlikely(abc_mask & float_cmask_anynan)) {\n- return partsN(pick_nan_muladd)(a, b, c, s, ab_mask, abc_mask);\n+ *a = partsN(pick_nan_muladd)(a, b, c, s, ab_mask, abc_mask);\n+ return a;\n }\n \n if (flags & float_muladd_negate_c) {\n","prefixes":["72/84"]}