{"id":2228446,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2228446/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260426134002.865628-59-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260426134002.865628-59-richard.henderson@linaro.org>","date":"2026-04-26T13:39:35","name":"[58/84] fpu: Export FloatFmt structures","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"b0e4c5c9d81773dd7d160aec83bcf852aa98eb7e","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.1/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260426134002.865628-59-richard.henderson@linaro.org/mbox/","series":[{"id":501533,"url":"http://patchwork.ozlabs.org/api/1.1/series/501533/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501533","date":"2026-04-26T13:38:37","name":"fpu: Export some internals for targets","version":1,"mbox":"http://patchwork.ozlabs.org/series/501533/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2228446/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2228446/checks/","tags":{},"headers":{"Return-Path":"<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=Ay4kyAeP;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g3Slt1JPyz1yHg\n\tfor <incoming@patchwork.ozlabs.org>; Sun, 26 Apr 2026 23:51:22 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wGzpV-0007el-P8; Sun, 26 Apr 2026 09:47:25 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <richard.henderson@linaro.org>)\n id 1wGzoF-0005wK-Rd\n for qemu-devel@nongnu.org; Sun, 26 Apr 2026 09:46:11 -0400","from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <richard.henderson@linaro.org>)\n id 1wGzoC-0001Ut-JG\n for qemu-devel@nongnu.org; Sun, 26 Apr 2026 09:46:06 -0400","by mail-pl1-x62f.google.com with SMTP id\n d9443c01a7336-2ad9a9be502so58239345ad.0\n for <qemu-devel@nongnu.org>; Sun, 26 Apr 2026 06:45:49 -0700 (PDT)","from stoup.. ([180.233.125.15]) by smtp.gmail.com with ESMTPSA id\n d9443c01a7336-2b5faa34ea7sm280544085ad.34.2026.04.26.06.45.46\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Sun, 26 Apr 2026 06:45:47 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=linaro.org; s=google; t=1777211148; x=1777815948; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=s95gOsMYgi/f4zhiYit5ShyHyWR6YE2CuPY1Rv/+Q0w=;\n b=Ay4kyAePka02/goQCElt3a4a58enaFMmJz35ZAUr0dj/F+Ej0IeIR2U9BkQLMaiyM7\n XS75rtaiocElAQEsa9qUc8qUkKh4w3BMdiNaXSQPyFJO1MJU5lKUTImqtV3Ik7fD8mit\n HAcgNds+OKdsVZt/5N+VTZCDtRYgI54znIynONJlfbEVPiUPJ9hJWUVbxgfIoqrebR/p\n PEYFydr0iSRUJiT38ErhOBQuENOl3+vIGh+f3Jt302htq2m3xWA6TqL7knVl6tHWrWDA\n Z2ieLjmTQpXv6mMINes7h083n26aZ3agz9BC4RhoSvUC26W6p7RR2woxCotv73i48htM\n J9+A==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1777211148; x=1777815948;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=s95gOsMYgi/f4zhiYit5ShyHyWR6YE2CuPY1Rv/+Q0w=;\n b=HAG3+BS8ITTZoWE6Cq4zcs2SgvjwQjeYN6riusZX0JbTsG3xloi8lATy/fPOymHnXK\n op2XqNSe5IsGtWFVaugyUAN6CxfQUY/MDR0IxP9dUcs2QZGqUJMxebMWvUVQQJNyVdmy\n i5F9FduARWCjpBsIPx0PjNZMRQCC1mQfPKl+pV5BZ7Q3uwIQN5JC2LEjQkV9J0JQaN7G\n NDgeK11+Jwa2YSDtu0N/ZhQaT0GG3q2u4N4CmUwHJR60XwOGxwkxUgFW59Uhs5EE+wjj\n 0zIHkZlxusRNa1XEyUoh1FZFh0OEudihCYgr8CnqAjKaZQ4YF1V2Ua4gg4xUJUp+45jO\n RedQ==","X-Gm-Message-State":"AOJu0YzPW+OEziVRvLdQxHJdB7g8o2XyC0KgB4Z2RcNtpqHDdcJ5XwBr\n CLpjFu94c1MXV39JK7vxpP3kEBwJBvoPk0YSeFZUASBZMEOBjF+ipTC+f49gX3is0dSsJGyRT+j\n VBEWVAMY=","X-Gm-Gg":"AeBDietlZdgPFWLKdW0FJMBudVw6/jYHTUZ3E2DykXOZW9poiu/wDjXIKN3wE3DdAMU\n cvVI6nv+PjlSJkdnN2O7ZGhnFJ6txNweYx2nYyqD+TU1GSUcz/fKcVSLfAwND1l+WtBVGh63WJ+\n fNDfCnRniUSg863Q1LKD3RXoohUDAStm7GQ8ZyNBW3t+UDi6vUfIa+RRN91hpKSeD9xgXhagvZQ\n MI2Ut0P7LgwtZvhnMTjBp9iiKB9+skWvoQVYJECpLZW2whpxV/2RZa1ThzbtbJftKlqkwTN+uUI\n md1eIymgKM2Ob7Dp7aDxSatp3XzJjO52BxmVNdvsoZJmD4BbcR2brfQaTvmF7L43d4lN6/E+xf8\n bp5tCQ/T76VYosq7U9YqucdDHSfeSJqM0SpzHDTs3E+BZJPPwcq7Fvpg0aXAX3BoBX8YwHSNFIx\n d4iSRfzO5xqxGe3dGBSyxJTNdtpjAzOcqMIAZBal6b","X-Received":"by 2002:a17:903:2acb:b0:2b4:6398:6aa2 with SMTP id\n d9443c01a7336-2b5f9f3a802mr451335435ad.27.1777211148231;\n Sun, 26 Apr 2026 06:45:48 -0700 (PDT)","From":"Richard Henderson <richard.henderson@linaro.org>","To":"qemu-devel@nongnu.org","Cc":"qemu-arm@nongnu.org,\n\tqemu-s390x@nongnu.org","Subject":"[PATCH 58/84] fpu: Export FloatFmt structures","Date":"Sun, 26 Apr 2026 23:39:35 +1000","Message-ID":"<20260426134002.865628-59-richard.henderson@linaro.org>","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"<20260426134002.865628-1-richard.henderson@linaro.org>","References":"<20260426134002.865628-1-richard.henderson@linaro.org>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2607:f8b0:4864:20::62f;\n envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development <qemu-devel.nongnu.org>","List-Unsubscribe":"<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>","List-Archive":"<https://lists.nongnu.org/archive/html/qemu-devel>","List-Post":"<mailto:qemu-devel@nongnu.org>","List-Help":"<mailto:qemu-devel-request@nongnu.org?subject=help>","List-Subscribe":"<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Export most of the FloatFmt structures.\nSkip float16_params_ahp and the floatx80 precisions.\n\nSigned-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n include/fpu/softfloat-parts.h | 48 ++++++++++++++++++++++++++++++\n fpu/softfloat.c               | 55 +++++------------------------------\n 2 files changed, 56 insertions(+), 47 deletions(-)","diff":"diff --git a/include/fpu/softfloat-parts.h b/include/fpu/softfloat-parts.h\nindex 13c1f3d2d6..a3ae12bb45 100644\n--- a/include/fpu/softfloat-parts.h\n+++ b/include/fpu/softfloat-parts.h\n@@ -18,6 +18,54 @@\n #ifndef SOFTFLOAT_PARTS_H\n #define SOFTFLOAT_PARTS_H\n \n+/* Format-specific handling of exp == exp_max */\n+typedef enum __attribute__((__packed__)) {\n+    /* exp==max, frac==0 ? infinity : nan; this is ieee standard. */\n+    float_expmax_ieee,\n+    /* exp==max is a normal number; no infinity or nan representation. */\n+    float_expmax_normal,\n+    /* exp==max, frac==max ? nan : normal; no infinity representation. */\n+    float_expmax_e4m3,\n+} FloatFmtExpMaxKind;\n+\n+/*\n+ * Structure holding all of the relevant parameters for a format.\n+ *   exp_size: the size of the exponent field\n+ *   exp_bias: the offset applied to the exponent field\n+ *   exp_max: the maximum normalised exponent\n+ *   frac_size: the size of the fraction field\n+ *   frac_shift: shift to normalise the fraction with DECOMPOSED_BINARY_POINT\n+ * The following are computed based the size of fraction\n+ *   round_mask: bits below lsb which must be rounded\n+ * The following optional modifiers are available:\n+ *   exp_max_kind: affects how exp == exp_max is interpreted\n+ *   has_explicit_bit: has an explicit integer bit; this affects whether\n+ *       the float_status floatx80_behaviour handling applies\n+ *   overflow_raises_invalid: for float_expmax_normal, raise invalid\n+ *       instead of overflow.\n+ */\n+typedef struct {\n+    int exp_size;\n+    int exp_bias;\n+    int exp_re_bias;\n+    int exp_max;\n+    int frac_size;\n+    int frac_shift;\n+    FloatFmtExpMaxKind exp_max_kind;\n+    bool has_explicit_bit;\n+    bool overflow_raises_invalid;\n+    uint64_t round_mask;\n+} FloatFmt;\n+\n+extern const FloatFmt float4_e2m1_params;\n+extern const FloatFmt float8_e4m3_params;\n+extern const FloatFmt float8_e5m2_params;\n+extern const FloatFmt float16_params;\n+extern const FloatFmt bfloat16_params;\n+extern const FloatFmt float32_params;\n+extern const FloatFmt float64_params;\n+extern const FloatFmt float128_params;\n+\n /*\n  * Classify a floating point number. Everything above float_class_qnan\n  * is a NaN so cls >= float_class_qnan is any NaN.\ndiff --git a/fpu/softfloat.c b/fpu/softfloat.c\nindex cd75df3160..d3277e3f60 100644\n--- a/fpu/softfloat.c\n+++ b/fpu/softfloat.c\n@@ -457,45 +457,6 @@ typedef struct {\n #define DECOMPOSED_BINARY_POINT    63\n #define DECOMPOSED_IMPLICIT_BIT    (1ull << DECOMPOSED_BINARY_POINT)\n \n-/* Format-specific handling of exp == exp_max */\n-typedef enum __attribute__((__packed__)) {\n-    /* exp==max, frac==0 ? infinity : nan; this is ieee standard. */\n-    float_expmax_ieee,\n-    /* exp==max is a normal number; no infinity or nan representation. */\n-    float_expmax_normal,\n-    /* exp==max, frac==max ? nan : normal; no infinity representation. */\n-    float_expmax_e4m3,\n-} FloatFmtExpMaxKind;\n-\n-/*\n- * Structure holding all of the relevant parameters for a format.\n- *   exp_size: the size of the exponent field\n- *   exp_bias: the offset applied to the exponent field\n- *   exp_max: the maximum normalised exponent\n- *   frac_size: the size of the fraction field\n- *   frac_shift: shift to normalise the fraction with DECOMPOSED_BINARY_POINT\n- * The following are computed based the size of fraction\n- *   round_mask: bits below lsb which must be rounded\n- * The following optional modifiers are available:\n- *   exp_max_kind: affects how exp == exp_max is interpreted\n- *   has_explicit_bit: has an explicit integer bit; this affects whether\n- *       the float_status floatx80_behaviour handling applies\n- *   overflow_raises_invalid: for float_expmax_normal, raise invalid\n- *       instead of overflow.\n- */\n-typedef struct {\n-    int exp_size;\n-    int exp_bias;\n-    int exp_re_bias;\n-    int exp_max;\n-    int frac_size;\n-    int frac_shift;\n-    FloatFmtExpMaxKind exp_max_kind;\n-    bool has_explicit_bit;\n-    bool overflow_raises_invalid;\n-    uint64_t round_mask;\n-} FloatFmt;\n-\n /* Expand fields based on the size of exponent and fraction */\n #define FLOAT_PARAMS_(E)                                \\\n     .exp_size       = E,                                \\\n@@ -509,12 +470,12 @@ typedef struct {\n     .frac_shift     = (-F - 1) & 63,                    \\\n     .round_mask     = (1ull << ((-F - 1) & 63)) - 1\n \n-static const FloatFmt float4_e2m1_params = {\n+const FloatFmt float4_e2m1_params = {\n     FLOAT_PARAMS(2, 1),\n     .exp_max_kind = float_expmax_normal,\n };\n \n-static const FloatFmt float8_e4m3_params = {\n+const FloatFmt float8_e4m3_params = {\n     FLOAT_PARAMS(4, 3),\n     .exp_max_kind = float_expmax_e4m3\n };\n@@ -522,11 +483,11 @@ static const FloatFmt float8_e4m3_params = {\n /* 110 << frac_shift, with the implicit bit set */\n #define E4M3_NORMAL_FRAC_MAX  0xe000000000000000ull\n \n-static const FloatFmt float8_e5m2_params = {\n+const FloatFmt float8_e5m2_params = {\n     FLOAT_PARAMS(5, 2)\n };\n \n-static const FloatFmt float16_params = {\n+const FloatFmt float16_params = {\n     FLOAT_PARAMS(5, 10)\n };\n \n@@ -536,19 +497,19 @@ static const FloatFmt float16_params_ahp = {\n     .overflow_raises_invalid = true,\n };\n \n-static const FloatFmt bfloat16_params = {\n+const FloatFmt bfloat16_params = {\n     FLOAT_PARAMS(8, 7)\n };\n \n-static const FloatFmt float32_params = {\n+const FloatFmt float32_params = {\n     FLOAT_PARAMS(8, 23)\n };\n \n-static const FloatFmt float64_params = {\n+const FloatFmt float64_params = {\n     FLOAT_PARAMS(11, 52)\n };\n \n-static const FloatFmt float128_params = {\n+const FloatFmt float128_params = {\n     FLOAT_PARAMS(15, 112)\n };\n \n","prefixes":["58/84"]}