{"id":2228429,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2228429/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260426134002.865628-78-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260426134002.865628-78-richard.henderson@linaro.org>","date":"2026-04-26T13:39:54","name":"[77/84] fpu: Return struct from parts{64,128}_mul","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"cc058549d9a15245ddfe1ea22c3cb7b7ccf55729","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.1/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260426134002.865628-78-richard.henderson@linaro.org/mbox/","series":[{"id":501533,"url":"http://patchwork.ozlabs.org/api/1.1/series/501533/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501533","date":"2026-04-26T13:38:37","name":"fpu: Export some internals for targets","version":1,"mbox":"http://patchwork.ozlabs.org/series/501533/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2228429/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2228429/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=FyWMDIp3;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g3Shr0v0Zz1y2d\n\tfor ; Sun, 26 Apr 2026 23:48:44 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wGzpe-0000KX-MO; Sun, 26 Apr 2026 09:47:34 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wGzor-0006WK-QV\n for qemu-devel@nongnu.org; Sun, 26 Apr 2026 09:46:45 -0400","from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wGzon-0001rZ-Iv\n for qemu-devel@nongnu.org; Sun, 26 Apr 2026 09:46:44 -0400","by mail-pj1-x1029.google.com with SMTP id\n 98e67ed59e1d1-3567e2b4159so6302556a91.0\n for ; Sun, 26 Apr 2026 06:46:41 -0700 (PDT)","from stoup.. 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","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"At the same time, export.\n\nSigned-off-by: Richard Henderson \n---\n include/fpu/softfloat-parts.h | 5 +++++\n fpu/softfloat.c | 34 +++++++++++++++++-----------------\n fpu/softfloat-parts.c.inc | 35 ++++++++++++++++-------------------\n 3 files changed, 38 insertions(+), 36 deletions(-)","diff":"diff --git a/include/fpu/softfloat-parts.h b/include/fpu/softfloat-parts.h\nindex f8f96e2f68..f2c31eb7a6 100644\n--- a/include/fpu/softfloat-parts.h\n+++ b/include/fpu/softfloat-parts.h\n@@ -189,6 +189,11 @@ FloatRelation parts64_compare(const FloatParts64 *a, const FloatParts64 *b,\n FloatRelation parts128_compare(const FloatParts128 *a, const FloatParts128 *b,\n float_status *s, bool quiet);\n \n+FloatParts64 parts64_mul(const FloatParts64 *a, const FloatParts64 *b,\n+ float_status *s);\n+FloatParts128 parts128_mul(const FloatParts128 *a, const FloatParts128 *b,\n+ float_status *s);\n+\n FloatParts64 parts64_muladd_scalbn(const FloatParts64 *a,\n const FloatParts64 *b,\n const FloatParts64 *c,\ndiff --git a/fpu/softfloat.c b/fpu/softfloat.c\nindex d51920652a..2db08ca660 100644\n--- a/fpu/softfloat.c\n+++ b/fpu/softfloat.c\n@@ -1801,9 +1801,9 @@ float16 QEMU_FLATTEN float16_mul(float16 a, float16 b, float_status *status)\n {\n FloatParts64 pa = float16_unpack_canonical(a, status);\n FloatParts64 pb = float16_unpack_canonical(b, status);\n- FloatParts64 *pr = parts64_mul(&pa, &pb, status);\n+ FloatParts64 pr = parts64_mul(&pa, &pb, status);\n \n- return float16_round_pack_canonical(pr, status);\n+ return float16_round_pack_canonical(&pr, status);\n }\n \n static float32 QEMU_SOFTFLOAT_ATTR\n@@ -1811,9 +1811,9 @@ soft_f32_mul(float32 a, float32 b, float_status *status)\n {\n FloatParts64 pa = float32_unpack_canonical(a, status);\n FloatParts64 pb = float32_unpack_canonical(b, status);\n- FloatParts64 *pr = parts64_mul(&pa, &pb, status);\n+ FloatParts64 pr = parts64_mul(&pa, &pb, status);\n \n- return float32_round_pack_canonical(pr, status);\n+ return float32_round_pack_canonical(&pr, status);\n }\n \n static float64 QEMU_SOFTFLOAT_ATTR\n@@ -1821,9 +1821,9 @@ soft_f64_mul(float64 a, float64 b, float_status *status)\n {\n FloatParts64 pa = float64_unpack_canonical(a, status);\n FloatParts64 pb = float64_unpack_canonical(b, status);\n- FloatParts64 *pr = parts64_mul(&pa, &pb, status);\n+ FloatParts64 pr = parts64_mul(&pa, &pb, status);\n \n- return float64_round_pack_canonical(pr, status);\n+ return float64_round_pack_canonical(&pr, status);\n }\n \n static float hard_f32_mul(float a, float b)\n@@ -1854,9 +1854,9 @@ float64 float64r32_mul(float64 a, float64 b, float_status *status)\n {\n FloatParts64 pa = float64_unpack_canonical(a, status);\n FloatParts64 pb = float64_unpack_canonical(b, status);\n- FloatParts64 *pr = parts64_mul(&pa, &pb, status);\n+ FloatParts64 pr = parts64_mul(&pa, &pb, status);\n \n- return float64r32_round_pack_canonical(pr, status);\n+ return float64r32_round_pack_canonical(&pr, status);\n }\n \n bfloat16 QEMU_FLATTEN\n@@ -1864,9 +1864,9 @@ bfloat16_mul(bfloat16 a, bfloat16 b, float_status *status)\n {\n FloatParts64 pa = bfloat16_unpack_canonical(a, status);\n FloatParts64 pb = bfloat16_unpack_canonical(b, status);\n- FloatParts64 *pr = parts64_mul(&pa, &pb, status);\n+ FloatParts64 pr = parts64_mul(&pa, &pb, status);\n \n- return bfloat16_round_pack_canonical(pr, status);\n+ return bfloat16_round_pack_canonical(&pr, status);\n }\n \n float128 QEMU_FLATTEN\n@@ -1874,23 +1874,23 @@ float128_mul(float128 a, float128 b, float_status *status)\n {\n FloatParts128 pa = float128_unpack_canonical(a, status);\n FloatParts128 pb = float128_unpack_canonical(b, status);\n- FloatParts128 *pr = parts128_mul(&pa, &pb, status);\n+ FloatParts128 pr = parts128_mul(&pa, &pb, status);\n \n- return float128_round_pack_canonical(pr, status);\n+ return float128_round_pack_canonical(&pr, status);\n }\n \n floatx80 QEMU_FLATTEN\n floatx80_mul(floatx80 a, floatx80 b, float_status *status)\n {\n- FloatParts128 pa, pb, *pr;\n+ FloatParts128 pa, pb;\n \n if (!floatx80_unpack_canonical(&pa, a, status) ||\n !floatx80_unpack_canonical(&pb, b, status)) {\n return floatx80_default_nan(status);\n }\n \n- pr = parts128_mul(&pa, &pb, status);\n- return floatx80_round_pack_canonical(pr, status);\n+ pa = parts128_mul(&pa, &pb, status);\n+ return floatx80_round_pack_canonical(&pa, status);\n }\n \n /*\n@@ -5108,14 +5108,14 @@ float32 float32_exp2(float32 a, float_status *status)\n float_raise(float_flag_inexact, status);\n \n tp = float64_unpack_canonical(float64_ln2, status);\n- xp = *parts64_mul(&xp, &tp, status);\n+ xp = parts64_mul(&xp, &tp, status);\n xnp = xp;\n \n rp = float64_unpack_canonical(float64_one, status);\n for (int i = 0; i < 15; i++) {\n tp = float64_unpack_canonical(float32_exp2_coefficients[i], status);\n rp = parts64_muladd_scalbn(&tp, &xnp, &rp, 0, 0, status);\n- xnp = *parts64_mul(&xnp, &xp, status);\n+ xnp = parts64_mul(&xnp, &xp, status);\n }\n \n return float32_round_pack_canonical(&rp, status);\ndiff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc\nindex fcb6b33f23..dca751fb94 100644\n--- a/fpu/softfloat-parts.c.inc\n+++ b/fpu/softfloat-parts.c.inc\n@@ -613,55 +613,52 @@ static FloatPartsN *partsN(addsub)(FloatPartsN *a, FloatPartsN *b,\n * `b'. The operation is performed according to the IEC/IEEE Standard\n * for Binary Floating-Point Arithmetic.\n */\n-static FloatPartsN *partsN(mul)(FloatPartsN *a, FloatPartsN *b,\n- float_status *s)\n+FloatPartsN partsN(mul)(const FloatPartsN *a, const FloatPartsN *b,\n+ float_status *s)\n {\n int ab_mask = float_cmask(a->cls) | float_cmask(b->cls);\n bool sign = a->sign ^ b->sign;\n \n if (likely(cmask_is_only_normals(ab_mask))) {\n FloatPartsW tmp;\n+ FloatPartsN r = {\n+ .cls = float_class_normal,\n+ .sign = sign,\n+ .exp = a->exp + b->exp + 1,\n+ };\n \n record_denormals_used(ab_mask, s);\n \n fracN(mulw)(&tmp, a, b);\n- fracN(truncjam)(a, &tmp);\n+ fracN(truncjam)(&r, &tmp);\n \n- a->exp += b->exp + 1;\n- if (!(a->frac_hi & DECOMPOSED_IMPLICIT_BIT)) {\n- fracN(add)(a, a, a);\n- a->exp -= 1;\n+ if (!(r.frac_hi & DECOMPOSED_IMPLICIT_BIT)) {\n+ fracN(add)(&r, &r, &r);\n+ r.exp -= 1;\n }\n \n- a->sign = sign;\n- return a;\n+ return r;\n }\n \n /* Inf * Zero == NaN */\n if (unlikely(ab_mask == float_cmask_infzero)) {\n float_raise(float_flag_invalid | float_flag_invalid_imz, s);\n- *a = partsN(default_nan)(s);\n- return a;\n+ return partsN(default_nan)(s);\n }\n \n if (unlikely(ab_mask & float_cmask_anynan)) {\n- *a = partsN(pick_nan)(a, b, s);\n-\treturn a;\n+ return partsN(pick_nan)(a, b, s);\n }\n \n /* Multiply by 0 or Inf */\n record_denormals_used(ab_mask, s);\n \n if (ab_mask & float_cmask_inf) {\n- a->cls = float_class_inf;\n- a->sign = sign;\n- return a;\n+ return (FloatPartsN){ .cls = float_class_inf, .sign = sign };\n }\n \n g_assert(ab_mask & float_cmask_zero);\n- a->cls = float_class_zero;\n- a->sign = sign;\n- return a;\n+ return (FloatPartsN){ .cls = float_class_zero, .sign = sign };\n }\n \n /*\n","prefixes":["77/84"]}