{"id":2228408,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2228408/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260426134002.865628-5-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260426134002.865628-5-richard.henderson@linaro.org>","date":"2026-04-26T13:38:41","name":"[04/84] fpu: Drop parts_default_nan","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"75c8d80d90d981c3c7414cfa47c9947646fc7682","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.1/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260426134002.865628-5-richard.henderson@linaro.org/mbox/","series":[{"id":501533,"url":"http://patchwork.ozlabs.org/api/1.1/series/501533/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501533","date":"2026-04-26T13:38:37","name":"fpu: Export some internals for targets","version":1,"mbox":"http://patchwork.ozlabs.org/series/501533/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2228408/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2228408/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=gCqTIaqg;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g3SfP01whz1y2d\n\tfor ; Sun, 26 Apr 2026 23:46:35 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wGzix-00071E-Px; Sun, 26 Apr 2026 09:40:39 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wGzig-0006sk-RJ\n for qemu-devel@nongnu.org; Sun, 26 Apr 2026 09:40:23 -0400","from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wGzie-0008Gz-Qa\n for qemu-devel@nongnu.org; Sun, 26 Apr 2026 09:40:22 -0400","by mail-pl1-x632.google.com with SMTP id\n d9443c01a7336-2ab46931cf1so70757525ad.0\n for ; Sun, 26 Apr 2026 06:40:20 -0700 (PDT)","from stoup.. ([180.233.125.15]) by smtp.gmail.com with ESMTPSA id\n d9443c01a7336-2b5fab30f29sm277940375ad.68.2026.04.26.06.40.16\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Sun, 26 Apr 2026 06:40:18 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=linaro.org; s=google; t=1777210819; x=1777815619; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=wkmJsSnzSIeu5aRXxhdaCCtrL9SrqbsTI14aS+J1vKY=;\n b=gCqTIaqgBcFXbgxd5O5WwlXUC7zl++LqUqdvJVFsNcdSTzP9ogHEzCrlIg3sOpHiz4\n FEDmFc+ieU4WRktixM3kq1zCmhaiQpBUOltll3EIKhyLXJuaD2b+UMB2BhD02yTZ/Rw0\n XrYYwU1FIjTk1x+0IEUA9zlrAE0U/UfWY41gpgXzmYzuhGFlPW9ukbTRLYAGohN6p96B\n T18dU+60hMXINkh9D1QUjRMJjItzoCHPYm86SfgMKErz0/O8T7V6QT7Z7b2nzPY8Diof\n +dTZa3grknqmJJC9PPjSf9qRNTrQFPHXPi3XKRaMPoIU43CqDKFrQoki15E/vTtOEvsu\n B4pA==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1777210819; x=1777815619;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=wkmJsSnzSIeu5aRXxhdaCCtrL9SrqbsTI14aS+J1vKY=;\n b=cfsDnxRnsm3TQx+xOkEX43l7flsOqzMLCi1GhMNIm5WtNdGFmDDoPoSjmfHXd02mrt\n sz5AV4gmkiOdvd7kYApKrGjDY6yQTRPqKaJIwpVfZGJ027sEqV5cDo1qEqeD5TeQCp59\n 7rprqOhr76VwnR5aWZr/QMRNjxVtsSvmNp0h2IYP9WgEzf9clfa9PZfKvAQE3yxeE0/K\n 3xwC4VUL34Ob8/54IIx2OUGoTWKmVtGRfysoi4UBrMOwlh54GTN3/Hyv3iMn1kgsrAc+\n wjLhg/atdTV1ed6O/Cme0ChzOX+A5B0Eo3hH02HBBsvc66ev81Qm4K2ra2nNHHjGef9C\n efqw==","X-Gm-Message-State":"AOJu0YzARY2uMFtdVQuGMypY2JTcO4dFlaE0KnP5HPQCquKf9ysgZlni\n 0qeyvAk2+5ghW1xv+4nm6vGsxiKM7WA6fq0ybhKa3XQF0qF4azwDKC1TyV+YgnOlAB2LfI6jUho\n wQwJ2eX8=","X-Gm-Gg":"AeBDietCUVYmzTzpgyCCXQOfo1YBsUkNpzYig0piZKVylSCOky9aylTNEV1sgLFYRq4\n X71TMZsmCzwUQCSZ0pC+W0DLICloufpAPgLBoSX6qG4j/KC7lTExxyk3MyvfF0PB24OR0GMtXTM\n E+m9RcTThWfraj/NjWpzV2ZWahm+ME4L3MEPhp1mj2XLVg9+HLdttn/zDf0tcHQZZn3AFE23A7U\n vQHuNKMnndaIpxGHpyY0FqwVHMBJoSjRp6uR3fJbKEAXWB66F43iahEpASGElVogZZ5rO4roctY\n HO7971cgxolVei9NpFdVyvfxTvlkIpa/Bs9WXyGuN6tzOeWWJoLJXJMR2wYzBZn0RypC4Pj4pwk\n DS23v1usJA5Ab8WyiWlXtmM1yOHX87wIhVq8lmoiSa5/cevm2hLBjLGOsa20XYdUc5syFvqDsvb\n i5YXp+hIayy0WJgM3VGltk1B9rmGcijm9U83bzfLoGQ1oLVeeRBYQ=","X-Received":"by 2002:a17:903:3910:b0:2b7:88f9:9c28 with SMTP id\n d9443c01a7336-2b788f9a0c6mr204799165ad.5.1777210819079;\n Sun, 26 Apr 2026 06:40:19 -0700 (PDT)","From":"Richard Henderson ","To":"qemu-devel@nongnu.org","Cc":"qemu-arm@nongnu.org,\n\tqemu-s390x@nongnu.org","Subject":"[PATCH 04/84] fpu: Drop parts_default_nan","Date":"Sun, 26 Apr 2026 23:38:41 +1000","Message-ID":"<20260426134002.865628-5-richard.henderson@linaro.org>","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"<20260426134002.865628-1-richard.henderson@linaro.org>","References":"<20260426134002.865628-1-richard.henderson@linaro.org>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2607:f8b0:4864:20::632;\n envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Use parts{64,128}_default_nan at each call site.\n\nSigned-off-by: Richard Henderson \n---\n fpu/softfloat.c | 23 +++++++++++------------\n fpu/softfloat-parts.c.inc | 24 ++++++++++++------------\n 2 files changed, 23 insertions(+), 24 deletions(-)","diff":"diff --git a/fpu/softfloat.c b/fpu/softfloat.c\nindex 4876a8bb27..76c1d4e38a 100644\n--- a/fpu/softfloat.c\n+++ b/fpu/softfloat.c\n@@ -779,7 +779,6 @@ static float128 QEMU_FLATTEN float128_pack_raw(const FloatParts128 *p)\n FloatParts128 *: parts128_##NAME, \\\n FloatParts256 *: parts256_##NAME)\n \n-#define parts_default_nan(P, S) PARTS_GENERIC_64_128(default_nan, P)(P, S)\n #define parts_silence_nan(P, S) PARTS_GENERIC_64_128(silence_nan, P)(P, S)\n \n static void parts64_return_nan(FloatParts64 *a, float_status *s);\n@@ -3156,7 +3155,7 @@ float32 floatx80_to_float32(floatx80 a, float_status *s)\n if (floatx80_unpack_canonical(&p128, a, s)) {\n parts_float_to_float_narrow(&p64, &p128, s);\n } else {\n- parts_default_nan(&p64, s);\n+ parts64_default_nan(&p64, s);\n }\n return float32_round_pack_canonical(&p64, s);\n }\n@@ -3169,7 +3168,7 @@ float64 floatx80_to_float64(floatx80 a, float_status *s)\n if (floatx80_unpack_canonical(&p128, a, s)) {\n parts_float_to_float_narrow(&p64, &p128, s);\n } else {\n- parts_default_nan(&p64, s);\n+ parts64_default_nan(&p64, s);\n }\n return float64_round_pack_canonical(&p64, s);\n }\n@@ -3181,7 +3180,7 @@ float128 floatx80_to_float128(floatx80 a, float_status *s)\n if (floatx80_unpack_canonical(&p, a, s)) {\n parts_float_to_float(&p, s);\n } else {\n- parts_default_nan(&p, s);\n+ parts128_default_nan(&p, s);\n }\n return float128_round_pack_canonical(&p, s);\n }\n@@ -3486,7 +3485,7 @@ static int32_t floatx80_to_int32_scalbn(floatx80 a, FloatRoundMode rmode,\n FloatParts128 p;\n \n if (!floatx80_unpack_canonical(&p, a, s)) {\n- parts_default_nan(&p, s);\n+ parts128_default_nan(&p, s);\n }\n return parts_float_to_sint(&p, rmode, scale, INT32_MIN, INT32_MAX, s);\n }\n@@ -3497,7 +3496,7 @@ static int64_t floatx80_to_int64_scalbn(floatx80 a, FloatRoundMode rmode,\n FloatParts128 p;\n \n if (!floatx80_unpack_canonical(&p, a, s)) {\n- parts_default_nan(&p, s);\n+ parts128_default_nan(&p, s);\n }\n return parts_float_to_sint(&p, rmode, scale, INT64_MIN, INT64_MAX, s);\n }\n@@ -4984,7 +4983,7 @@ float16 float16_default_nan(float_status *status)\n {\n FloatParts64 p;\n \n- parts_default_nan(&p, status);\n+ parts64_default_nan(&p, status);\n p.frac >>= float16_params.frac_shift;\n return float16_pack_raw(&p);\n }\n@@ -4993,7 +4992,7 @@ float32 float32_default_nan(float_status *status)\n {\n FloatParts64 p;\n \n- parts_default_nan(&p, status);\n+ parts64_default_nan(&p, status);\n p.frac >>= float32_params.frac_shift;\n return float32_pack_raw(&p);\n }\n@@ -5002,7 +5001,7 @@ float64 float64_default_nan(float_status *status)\n {\n FloatParts64 p;\n \n- parts_default_nan(&p, status);\n+ parts64_default_nan(&p, status);\n p.frac >>= float64_params.frac_shift;\n return float64_pack_raw(&p);\n }\n@@ -5011,7 +5010,7 @@ float128 float128_default_nan(float_status *status)\n {\n FloatParts128 p;\n \n- parts_default_nan(&p, status);\n+ parts128_default_nan(&p, status);\n frac_shr(&p, float128_params.frac_shift);\n return float128_pack_raw(&p);\n }\n@@ -5020,7 +5019,7 @@ bfloat16 bfloat16_default_nan(float_status *status)\n {\n FloatParts64 p;\n \n- parts_default_nan(&p, status);\n+ parts64_default_nan(&p, status);\n p.frac >>= bfloat16_params.frac_shift;\n return bfloat16_pack_raw(&p);\n }\n@@ -5537,7 +5536,7 @@ static void parts_s390_divide_to_integer(FloatParts64 *a, FloatParts64 *b,\n *n = *r;\n *cc = 1;\n } else if (a->cls == float_class_inf || b->cls == float_class_zero) {\n- parts_default_nan(r, status);\n+ parts64_default_nan(r, status);\n *n = *r;\n *cc = 1;\n status->float_exception_flags |= float_flag_invalid;\ndiff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc\nindex 948eb7bd6a..37ce731101 100644\n--- a/fpu/softfloat-parts.c.inc\n+++ b/fpu/softfloat-parts.c.inc\n@@ -21,14 +21,14 @@ static void partsN(return_nan)(FloatPartsN *a, float_status *s)\n case float_class_snan:\n float_raise(float_flag_invalid | float_flag_invalid_snan, s);\n if (s->default_nan_mode) {\n- parts_default_nan(a, s);\n+ partsN(default_nan)(a, s);\n } else {\n parts_silence_nan(a, s);\n }\n break;\n case float_class_qnan:\n if (s->default_nan_mode) {\n- parts_default_nan(a, s);\n+ partsN(default_nan)(a, s);\n }\n break;\n default:\n@@ -49,7 +49,7 @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,\n }\n \n if (s->default_nan_mode) {\n- parts_default_nan(a, s);\n+ partsN(default_nan)(a, s);\n return a;\n }\n \n@@ -184,7 +184,7 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,\n return ret;\n \n default_nan:\n- parts_default_nan(a, s);\n+ partsN(default_nan)(a, s);\n return a;\n }\n \n@@ -281,7 +281,7 @@ static void partsN(uncanon_e4m3_overflow)(FloatPartsN *p, float_status *s,\n p->exp = fmt->exp_max;\n p->frac_hi = E4M3_NORMAL_FRAC_MAX;\n } else {\n- parts_default_nan(p, s);\n+ partsN(default_nan)(p, s);\n }\n }\n \n@@ -568,7 +568,7 @@ static FloatPartsN *partsN(addsub)(FloatPartsN *a, FloatPartsN *b,\n }\n /* Inf - Inf */\n float_raise(float_flag_invalid | float_flag_invalid_isi, s);\n- parts_default_nan(a, s);\n+ partsN(default_nan)(a, s);\n return a;\n }\n } else {\n@@ -641,7 +641,7 @@ static FloatPartsN *partsN(mul)(FloatPartsN *a, FloatPartsN *b,\n /* Inf * Zero == NaN */\n if (unlikely(ab_mask == float_cmask_infzero)) {\n float_raise(float_flag_invalid | float_flag_invalid_imz, s);\n- parts_default_nan(a, s);\n+ partsN(default_nan)(a, s);\n return a;\n }\n \n@@ -796,7 +796,7 @@ static FloatPartsN *partsN(muladd_scalbn)(FloatPartsN *a, FloatPartsN *b,\n goto finish_sign;\n \n d_nan:\n- parts_default_nan(a, s);\n+ partsN(default_nan)(a, s);\n return a;\n }\n \n@@ -864,7 +864,7 @@ static FloatPartsN *partsN(div)(FloatPartsN *a, FloatPartsN *b,\n return a;\n \n d_nan:\n- parts_default_nan(a, s);\n+ partsN(default_nan)(a, s);\n return a;\n }\n \n@@ -896,7 +896,7 @@ static FloatPartsN *partsN(modrem)(FloatPartsN *a, FloatPartsN *b,\n /* Inf % N; N % 0 */\n if (a->cls == float_class_inf || b->cls == float_class_zero) {\n float_raise(float_flag_invalid, s);\n- parts_default_nan(a, s);\n+ partsN(default_nan)(a, s);\n return a;\n }\n \n@@ -1118,7 +1118,7 @@ static void partsN(sqrt)(FloatPartsN *a, float_status *status,\n \n d_nan:\n float_raise(float_flag_invalid | float_flag_invalid_sqrt, status);\n- parts_default_nan(a, status);\n+ partsN(default_nan)(a, status);\n }\n \n /*\n@@ -1879,5 +1879,5 @@ static void partsN(log2)(FloatPartsN *a, float_status *s, const FloatFmt *fmt)\n \n d_nan:\n float_raise(float_flag_invalid, s);\n- parts_default_nan(a, s);\n+ partsN(default_nan)(a, s);\n }\n","prefixes":["04/84"]}