{"id":2228259,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2228259/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20260423-add-ethernet-support-for-genio-520-720-v1-8-47ca918e0017@baylibre.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.1/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260423-add-ethernet-support-for-genio-520-720-v1-8-47ca918e0017@baylibre.com>","date":"2026-04-23T13:25:59","name":"[8/9] arm: dts: mt8189: Add ethernet support for Genio 520/720 boards","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"8389e7580975ec49fc4425a8629b98459d338f77","submitter":{"id":84831,"url":"http://patchwork.ozlabs.org/api/1.1/people/84831/?format=json","name":"Julien Stephan","email":"jstephan@baylibre.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20260423-add-ethernet-support-for-genio-520-720-v1-8-47ca918e0017@baylibre.com/mbox/","series":[{"id":501460,"url":"http://patchwork.ozlabs.org/api/1.1/series/501460/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=501460","date":"2026-04-23T13:25:57","name":"Add ethernet support for genio 520/720 EVK boards","version":1,"mbox":"http://patchwork.ozlabs.org/series/501460/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2228259/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2228259/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=baylibre-com.20251104.gappssmtp.com\n header.i=@baylibre-com.20251104.gappssmtp.com header.a=rsa-sha256\n header.s=20251104 header.b=YhHATot6;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; 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charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","Message-Id":"\n <20260423-add-ethernet-support-for-genio-520-720-v1-8-47ca918e0017@baylibre.com>","References":"\n <20260423-add-ethernet-support-for-genio-520-720-v1-0-47ca918e0017@baylibre.com>","In-Reply-To":"\n <20260423-add-ethernet-support-for-genio-520-720-v1-0-47ca918e0017@baylibre.com>","To":"u-boot@lists.denx.de","Cc":"GSS_MTK_Uboot_upstream ,\n Jerome Forissier , Tom Rini ,\n Christian Marangi ,\n Robert Marko , Simon Glass ,\n Yao Zi , Quentin Schulz ,\n Mikhail Kshevetskiy ,\n Marek Vasut ,\n \"Lucien.Jheng\" ,\n Weijie Gao ,\n Romain Gantois ,\n Siddharth Vadapalli ,\n Yanqing Wang , Beiyan Yun ,\n Ryder Lee ,\n Chunfeng Yun ,\n Igor Belwon ,\n David Lechner ,\n Neil Armstrong ,\n Kory Maincent ,\n Ilias Apalodimas ,\n Kuan-Wei Chiu ,\n Raymond Mao , Peng Fan ,\n Stefan Roese ,\n Philip Molloy ,\n fanyi zhang , Jonas Karlman ,\n Kever Yang ,\n Marek Vasut ,\n Patrick Delaunay ,\n Heiko Stuebner ,\n Samuel Holland ,\n Christophe Roullier ,\n Patrice Chotard ,\n Chris-QJ Chen ,\n Macpaul Lin ,\n Sam Protsenko ,\n Michael Trimarchi ,\n Sky Huang ,\n Leo Yu-Chi Liang ,\n Tommy Shih ,\n Kevin-KW Huang ,\n Julien Stephan ","X-Mailer":"b4 0.14.3","X-Mailman-Approved-At":"Sat, 25 Apr 2026 20:02:44 +0200","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.39","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"},"content":"Add Ethernet support for MediaTek MT8189-based Genio 520 and Genio 720\ndevelopment boards.\n\nThe ethernet interface is disabled by default in the SoC dtsi and\nenabled in the board-specific configuration with proper PHY settings.\n\nThe ethernet related nodes are not part of current dt submission on the\nkernel [1] and come from downstream u-boot. When switching to\nOF_UPSTREAM we should add them back.\n\n[1]: https://lore.kernel.org/all/20251203-add-mediatek-genio-520-720-evk-v1-3-df794b2a30ae@collabora.com/\n\nSigned-off-by: Julien Stephan \n---\n arch/arm/dts/mt8189.dtsi | 77 ++++++++++++++++++++++++++++++++\n arch/arm/dts/mt8371-genio-common.dtsi | 83 +++++++++++++++++++++++++++++++++++\n 2 files changed, 160 insertions(+)","diff":"diff --git a/arch/arm/dts/mt8189.dtsi b/arch/arm/dts/mt8189.dtsi\nindex d246be63293..f6272d5c807 100644\n--- a/arch/arm/dts/mt8189.dtsi\n+++ b/arch/arm/dts/mt8189.dtsi\n@@ -240,6 +240,83 @@\n \t\t\t#reset-cells = <1>;\n \t\t};\n \n+\t\teth: ethernet@1101a000 {\n+\t\t\tcompatible = \"mediatek,mt8189-gmac\", \"snps,dwmac-5.10a\";\n+\t\t\treg = <0 0x1101a000 0 0x4000>;\n+\t\t\tinterrupts = ;\n+\t\t\tinterrupt-names = \"macirq\";\n+\t\t\tclock-names = \"mac_main\",\n+\t\t\t\t \"ptp_ref\";\n+\t\t\tclocks = <&topckgen_clk CLK_TOP_ETH_250M_SEL>,\n+\t\t\t\t <&topckgen_clk CLK_TOP_ETH_62P4M_PTP_SEL>;\n+\t\t\tassigned-clocks = <&topckgen_clk CLK_TOP_ETH_250M_SEL>,\n+\t\t\t\t\t <&topckgen_clk CLK_TOP_ETH_62P4M_PTP_SEL>,\n+\t\t\t\t\t <&topckgen_clk CLK_TOP_ETH_50M_RMII_SEL>;\n+\t\t\tassigned-clock-parents = <&topckgen_clk CLK_TOP_ETHPLL_D2>,\n+\t\t\t\t\t\t <&topckgen_clk CLK_TOP_ETHPLL_D8>,\n+\t\t\t\t\t\t <&topckgen_clk CLK_TOP_ETHPLL_D10>;\n+\t\t\tmediatek,pericfg = <&pericfg_ao_clk>;\n+\t\t\tsnps,axi-config = <&stmmac_axi_setup>;\n+\t\t\tsnps,mtl-rx-config = <&mtl_rx_setup>;\n+\t\t\tsnps,mtl-tx-config = <&mtl_tx_setup>;\n+\t\t\tsnps,txpbl = <16>;\n+\t\t\tsnps,rxpbl = <16>;\n+\t\t\tclk-csr = <4>;\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\tstmmac_axi_setup: stmmac-axi-config {\n+\t\t\t\tsnps,wr-osr-lmt = <0x7>;\n+\t\t\t\tsnps,rd-osr-lmt = <0x7>;\n+\t\t\t\tsnps,blen = <0 0 0 0 16 8 4>;\n+\t\t\t};\n+\n+\t\t\tmtl_rx_setup: rx-queues-config {\n+\t\t\t\tsnps,rx-queues-to-use = <4>;\n+\t\t\t\tsnps,rx-sched-sp;\n+\t\t\t\tqueue0 {\n+\t\t\t\t\tsnps,dcb-algorithm;\n+\t\t\t\t\tsnps,map-to-dma-channel = <0x0>;\n+\t\t\t\t};\n+\t\t\t\tqueue1 {\n+\t\t\t\t\tsnps,dcb-algorithm;\n+\t\t\t\t\tsnps,map-to-dma-channel = <0x0>;\n+\t\t\t\t};\n+\t\t\t\tqueue2 {\n+\t\t\t\t\tsnps,dcb-algorithm;\n+\t\t\t\t\tsnps,map-to-dma-channel = <0x0>;\n+\t\t\t\t};\n+\t\t\t\tqueue3 {\n+\t\t\t\t\tsnps,dcb-algorithm;\n+\t\t\t\t\tsnps,map-to-dma-channel = <0x0>;\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tmtl_tx_setup: tx-queues-config {\n+\t\t\t\tsnps,tx-queues-to-use = <4>;\n+\t\t\t\tsnps,tx-sched-wrr;\n+\t\t\t\tqueue0 {\n+\t\t\t\t\tsnps,weight = <0x10>;\n+\t\t\t\t\tsnps,dcb-algorithm;\n+\t\t\t\t\tsnps,priority = <0x0>;\n+\t\t\t\t};\n+\t\t\t\tqueue1 {\n+\t\t\t\t\tsnps,weight = <0x11>;\n+\t\t\t\t\tsnps,dcb-algorithm;\n+\t\t\t\t\tsnps,priority = <0x1>;\n+\t\t\t\t};\n+\t\t\t\tqueue2 {\n+\t\t\t\t\tsnps,weight = <0x12>;\n+\t\t\t\t\tsnps,dcb-algorithm;\n+\t\t\t\t\tsnps,priority = <0x2>;\n+\t\t\t\t};\n+\t\t\t\tqueue3 {\n+\t\t\t\t\tsnps,weight = <0x13>;\n+\t\t\t\t\tsnps,dcb-algorithm;\n+\t\t\t\t\tsnps,priority = <0x3>;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\n \t\ttopckgen_clk: clock-controller@10000000 {\n \t\t\tcompatible = \"mediatek,mt8189-topckgen\", \"syscon\";\n \t\t\treg = <0 0x10000000 0 0x1000>;\ndiff --git a/arch/arm/dts/mt8371-genio-common.dtsi b/arch/arm/dts/mt8371-genio-common.dtsi\nindex 58322193aef..e91a4b74c53 100644\n--- a/arch/arm/dts/mt8371-genio-common.dtsi\n+++ b/arch/arm/dts/mt8371-genio-common.dtsi\n@@ -236,8 +236,91 @@\n \t\t\tbias-pull-up;\n \t\t};\n \t};\n+\n+\teth_default_pins: eth-default-pins {\n+\t\ttxd-pins {\n+\t\t\tpinmux = ,\n+\t\t\t\t ,\n+\t\t\t\t ,\n+\t\t\t\t ;\n+\t\t\tdrive-strength = ;\n+\t\t};\n+\t\tcc-pins {\n+\t\t\tpinmux = ,\n+\t\t\t\t ,\n+\t\t\t\t ,\n+\t\t\t\t ;\n+\t\t\tdrive-strength = ;\n+\t\t};\n+\t\trxd-pins {\n+\t\t\tpinmux = ,\n+\t\t\t\t ,\n+\t\t\t\t ,\n+\t\t\t\t ;\n+\t\t\tdrive-strength = ;\n+\t\t};\n+\t\tmdio-pins {\n+\t\t\tpinmux = ,\n+\t\t\t\t ;\n+\t\t\tdrive-strength = ;\n+\t\t\tinput-enable;\n+\t\t};\n+\t\tpower-pins {\n+\t\t\tpinmux = ,\n+\t\t\t\t ;\n+\t\t\toutput-high;\n+\t\t};\n+\t};\n+\n+\teth_sleep_pins: eth-sleep-pins {\n+\t\ttxd-pins {\n+\t\t\tpinmux = ,\n+\t\t\t\t ,\n+\t\t\t\t ,\n+\t\t\t\t ;\n+\t\t};\n+\t\tcc-pins {\n+\t\t\tpinmux = ,\n+\t\t\t\t ,\n+\t\t\t\t ,\n+\t\t\t\t ;\n+\t\t};\n+\t\trxd-pins {\n+\t\t\tpinmux = ,\n+\t\t\t\t ,\n+\t\t\t\t ,\n+\t\t\t\t ;\n+\t\t};\n+\t\tmdio-pins {\n+\t\t\tpinmux = ,\n+\t\t\t\t ;\n+\t\t\tinput-disable;\n+\t\t\tbias-disable;\n+\t\t};\n+\t};\n };\n \n &pmic {\n \tinterrupts-extended = <&pio 194 IRQ_TYPE_LEVEL_HIGH>;\n };\n+\n+ð {\n+\t/*\n+\t * TX clock is provided by MAC\n+\t */\n+\tphy-mode = \"rgmii-rxid\";\n+\tphy-handle = <&phy>;\n+\tpinctrl-names = \"default\", \"sleep\";\n+\tpinctrl-0 = <ð_default_pins>;\n+\tpinctrl-1 = <ð_sleep_pins>;\n+\tstatus = \"okay\";\n+\tmdio {\n+\t\tcompatible = \"snps,dwmac-mdio\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tphy: phy@0 {\n+\t\t\tcompatible = \"ethernet-phy-idc0ff.0421\";\n+\t\t\treg = <0>;\n+\t\t};\n+\t};\n+};\n","prefixes":["8/9"]}