{"id":2228242,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2228242/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20260425-imx8m-of-upstream-v1-3-07527be92e5d@nxp.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.1/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260425-imx8m-of-upstream-v1-3-07527be92e5d@nxp.com>","date":"2026-04-25T00:36:55","name":"[03/13] imx8mq: pico: Switch OF_UPSTREAM","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"43f6374141fb48fc657474987ecc85b04bfbd7d1","submitter":{"id":80723,"url":"http://patchwork.ozlabs.org/api/1.1/people/80723/?format=json","name":"Peng Fan (OSS)","email":"peng.fan@oss.nxp.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20260425-imx8m-of-upstream-v1-3-07527be92e5d@nxp.com/mbox/","series":[{"id":501451,"url":"http://patchwork.ozlabs.org/api/1.1/series/501451/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=501451","date":"2026-04-25T00:37:04","name":"iMX8M: Covert to OF_UPSTREAM","version":1,"mbox":"http://patchwork.ozlabs.org/series/501451/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2228242/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2228242/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com\n header.a=rsa-sha256 header.s=selector1-NXP1-onmicrosoft-com\n header.b=qAjC8f9S;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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phobos.denx.de","X-Virus-Status":"Clean"},"content":"From: Peng Fan \n\narch/arm/dts/imx8mq-pico-pi.dts is almost same as upstream Linux dts,\nso switch to OF_UPSTREAM by dropping the U-Boot copy of the dts,\nenabling OF_UPSTREAM and updating CONFIG_DEFAULT_DEVICE_TREE.\n\nSigned-off-by: Peng Fan \n---\n arch/arm/dts/Makefile | 1 -\n arch/arm/dts/imx8mq-pico-pi.dts | 418 ----------------------------------------\n arch/arm/mach-imx/imx8m/Kconfig | 1 +\n configs/pico-imx8mq_defconfig | 2 +-\n 4 files changed, 2 insertions(+), 420 deletions(-)","diff":"diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile\nindex 4564544bc00..019928af9df 100644\n--- a/arch/arm/dts/Makefile\n+++ b/arch/arm/dts/Makefile\n@@ -889,7 +889,6 @@ dtb-$(CONFIG_ARCH_IMX8M) += \\\n \timx8mp-dhcom-picoitx.dtb \\\n \timx8mp-icore-mx8mp-edimm2.2.dtb \\\n \timx8mp-msc-sm2s.dtb \\\n-\timx8mq-pico-pi.dtb \\\n \timx8mq-kontron-pitx-imx8m.dtb \\\n \timx8mq-librem5-r4.dtb\n \ndiff --git a/arch/arm/dts/imx8mq-pico-pi.dts b/arch/arm/dts/imx8mq-pico-pi.dts\ndeleted file mode 100644\nindex 89cbec5c41b..00000000000\n--- a/arch/arm/dts/imx8mq-pico-pi.dts\n+++ /dev/null\n@@ -1,418 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0+\n-/*\n- * Copyright 2018 Wandboard, Org.\n- * Copyright 2017 NXP\n- *\n- * Author: Richard Hu \n- */\n-\n-/dts-v1/;\n-\n-#include \"imx8mq.dtsi\"\n-#include \n-\n-/ {\n-\tmodel = \"TechNexion PICO-PI-8M\";\n-\tcompatible = \"technexion,pico-pi-imx8m\", \"fsl,imx8mq\";\n-\n-\tchosen {\n-\t\tstdout-path = &uart1;\n-\t};\n-\n-\tpmic_osc: clock-pmic {\n-\t\tcompatible = \"fixed-clock\";\n-\t\t#clock-cells = <0>;\n-\t\tclock-frequency = <32768>;\n-\t\tclock-output-names = \"pmic_osc\";\n-\t};\n-\n-\treg_usb_otg_vbus: regulator-usb-otg-vbus {\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pinctrl_otg_vbus>;\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tregulator-name = \"usb_otg_vbus\";\n-\t\tregulator-min-microvolt = <5000000>;\n-\t\tregulator-max-microvolt = <5000000>;\n-\t\tgpio = <&gpio3 14 GPIO_ACTIVE_LOW>;\n-\t};\n-};\n-\n-&fec1 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_fec1 &pinctrl_enet_3v3>;\n-\tphy-mode = \"rgmii-id\";\n-\tphy-handle = <ðphy0>;\n-\tfsl,magic-packet;\n-\tstatus = \"okay\";\n-\n-\tmdio {\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\n-\t\tethphy0: ethernet-phy@1 {\n-\t\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n-\t\t\treg = <1>;\n-\t\t};\n-\t};\n-};\n-\n-&i2c1 {\n-\tclock-frequency = <100000>;\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_i2c1>;\n-\tstatus = \"okay\";\n-\n-\tpmic: pmic@4b {\n-\t\treg = <0x4b>;\n-\t\tcompatible = \"rohm,bd71837\";\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pinctrl_pmic>;\n-\t\tclocks = <&pmic_osc>;\n-\t\tclock-names = \"osc\";\n-\t\tclock-output-names = \"pmic_clk\";\n-\t\tinterrupt-parent = <&gpio1>;\n-\t\tinterrupts = <3 IRQ_TYPE_LEVEL_LOW>;\n-\t\tinterrupt-names = \"irq\";\n-\n-\t\tregulators {\n-\t\t\tbuck1: BUCK1 {\n-\t\t\t\tregulator-name = \"buck1\";\n-\t\t\t\tregulator-min-microvolt = <700000>;\n-\t\t\t\tregulator-max-microvolt = <1300000>;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-ramp-delay = <1250>;\n-\t\t\t\trohm,dvs-run-voltage = <900000>;\n-\t\t\t\trohm,dvs-idle-voltage = <850000>;\n-\t\t\t\trohm,dvs-suspend-voltage = <800000>;\n-\t\t\t};\n-\n-\t\t\tbuck2: BUCK2 {\n-\t\t\t\tregulator-name = \"buck2\";\n-\t\t\t\tregulator-min-microvolt = <700000>;\n-\t\t\t\tregulator-max-microvolt = <1300000>;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-ramp-delay = <1250>;\n-\t\t\t\trohm,dvs-run-voltage = <1000000>;\n-\t\t\t\trohm,dvs-idle-voltage = <900000>;\n-\t\t\t};\n-\n-\t\t\tbuck3: BUCK3 {\n-\t\t\t\tregulator-name = \"buck3\";\n-\t\t\t\tregulator-min-microvolt = <700000>;\n-\t\t\t\tregulator-max-microvolt = <1300000>;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\trohm,dvs-run-voltage = <1000000>;\n-\t\t\t};\n-\n-\t\t\tbuck4: BUCK4 {\n-\t\t\t\tregulator-name = \"buck4\";\n-\t\t\t\tregulator-min-microvolt = <700000>;\n-\t\t\t\tregulator-max-microvolt = <1300000>;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\trohm,dvs-run-voltage = <1000000>;\n-\t\t\t};\n-\n-\t\t\tbuck5: BUCK5 {\n-\t\t\t\tregulator-name = \"buck5\";\n-\t\t\t\tregulator-min-microvolt = <700000>;\n-\t\t\t\tregulator-max-microvolt = <1350000>;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t};\n-\n-\t\t\tbuck6: BUCK6 {\n-\t\t\t\tregulator-name = \"buck6\";\n-\t\t\t\tregulator-min-microvolt = <3000000>;\n-\t\t\t\tregulator-max-microvolt = <3300000>;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t};\n-\n-\t\t\tbuck7: BUCK7 {\n-\t\t\t\tregulator-name = \"buck7\";\n-\t\t\t\tregulator-min-microvolt = <1605000>;\n-\t\t\t\tregulator-max-microvolt = <1995000>;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t};\n-\n-\t\t\tbuck8: BUCK8 {\n-\t\t\t\tregulator-name = \"buck8\";\n-\t\t\t\tregulator-min-microvolt = <800000>;\n-\t\t\t\tregulator-max-microvolt = <1400000>;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t};\n-\n-\t\t\tldo1: LDO1 {\n-\t\t\t\tregulator-name = \"ldo1\";\n-\t\t\t\tregulator-min-microvolt = <3000000>;\n-\t\t\t\tregulator-max-microvolt = <3300000>;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-always-on;\n-\t\t\t};\n-\n-\t\t\tldo2: LDO2 {\n-\t\t\t\tregulator-name = \"ldo2\";\n-\t\t\t\tregulator-min-microvolt = <900000>;\n-\t\t\t\tregulator-max-microvolt = <900000>;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-always-on;\n-\t\t\t};\n-\n-\t\t\tldo3: LDO3 {\n-\t\t\t\tregulator-name = \"ldo3\";\n-\t\t\t\tregulator-min-microvolt = <1800000>;\n-\t\t\t\tregulator-max-microvolt = <3300000>;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t};\n-\n-\t\t\tldo4: LDO4 {\n-\t\t\t\tregulator-name = \"ldo4\";\n-\t\t\t\tregulator-min-microvolt = <900000>;\n-\t\t\t\tregulator-max-microvolt = <1800000>;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t};\n-\n-\t\t\tldo5: LDO5 {\n-\t\t\t\tregulator-name = \"ldo5\";\n-\t\t\t\tregulator-min-microvolt = <1800000>;\n-\t\t\t\tregulator-max-microvolt = <3300000>;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t};\n-\n-\t\t\tldo6: LDO6 {\n-\t\t\t\tregulator-name = \"ldo6\";\n-\t\t\t\tregulator-min-microvolt = <900000>;\n-\t\t\t\tregulator-max-microvolt = <1800000>;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t};\n-\n-\t\t\tldo7: LDO7 {\n-\t\t\t\tregulator-name = \"ldo7\";\n-\t\t\t\tregulator-min-microvolt = <1800000>;\n-\t\t\t\tregulator-max-microvolt = <3300000>;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t};\n-\t\t};\n-\t};\n-};\n-\n-&i2c2 {\n-\tclock-frequency = <100000>;\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_i2c2>;\n-\tstatus = \"okay\";\n-};\n-\n-&uart1 { /* console */\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_uart1>;\n-\tstatus = \"okay\";\n-};\n-\n-&usdhc1 {\n-\tassigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;\n-\tassigned-clock-rates = <400000000>;\n-\tpinctrl-names = \"default\", \"state_100mhz\", \"state_200mhz\";\n-\tpinctrl-0 = <&pinctrl_usdhc1>;\n-\tpinctrl-1 = <&pinctrl_usdhc1_100mhz>;\n-\tpinctrl-2 = <&pinctrl_usdhc1_200mhz>;\n-\tbus-width = <8>;\n-\tnon-removable;\n-\tstatus = \"okay\";\n-};\n-\n-&usdhc2 {\n-\tassigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;\n-\tassigned-clock-rates = <200000000>;\n-\tpinctrl-names = \"default\", \"state_100mhz\", \"state_200mhz\";\n-\tpinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;\n-\tpinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;\n-\tpinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;\n-\tbus-width = <4>;\n-\tcd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;\n-\tstatus = \"okay\";\n-};\n-\n-&usb3_phy0 {\n-\tstatus = \"okay\";\n-};\n-\n-&usb3_phy1 {\n-\tstatus = \"okay\";\n-};\n-\n-&usb_dwc3_1 {\n-\tdr_mode = \"host\";\n-\tstatus = \"okay\";\n-};\n-\n-&wdog1 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_wdog>;\n-\tfsl,ext-reset-output;\n-\tstatus = \"okay\";\n-};\n-\n-&iomuxc {\n-\tpinctrl_enet_3v3: enet3v3grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0\t0x19\n-\t\t>;\n-\t};\n-\n-\tpinctrl_fec1: fec1grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MQ_IOMUXC_ENET_MDC_ENET1_MDC\t\t0x3\n-\t\t\tMX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO\t0x23\n-\t\t\tMX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3\t0x1f\n-\t\t\tMX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2\t0x1f\n-\t\t\tMX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1\t0x1f\n-\t\t\tMX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0\t0x1f\n-\t\t\tMX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3\t0x91\n-\t\t\tMX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2\t0x91\n-\t\t\tMX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1\t0x91\n-\t\t\tMX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0\t0x91\n-\t\t\tMX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC\t0x1f\n-\t\t\tMX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC\t0x91\n-\t\t\tMX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL\t0x91\n-\t\t\tMX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL\t0x1f\n-\t\t\tMX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9\t0x19\n-\t\t>;\n-\t};\n-\n-\tpinctrl_i2c1: i2c1grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL\t\t\t0x4000007f\n-\t\t\tMX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA\t\t\t0x4000007f\n-\t\t>;\n-\t};\n-\n-\tpinctrl_i2c2: i2c2grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL\t\t\t0x4000007f\n-\t\t\tMX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA\t\t\t0x4000007f\n-\t\t>;\n-\t};\n-\n-\tpinctrl_otg_vbus: otgvbusgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14\t\t0x19 /* USB OTG VBUS Enable */\n-\t\t>;\n-\t};\n-\n-\tpinctrl_pmic: pmicirqgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3\t0x41\n-\t\t>;\n-\t};\n-\n-\tpinctrl_uart1: uart1grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX\t\t0x49\n-\t\t\tMX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX\t\t0x49\n-\t\t>;\n-\t};\n-\n-\tpinctrl_uart2: uart2grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX\t\t0x49\n-\t\t\tMX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX\t\t0x49\n-\t\t\tMX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B\t\t0x49\n-\t\t\tMX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B\t\t0x49\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc1: usdhc1grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK\t\t\t0x83\n-\t\t\tMX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD\t\t\t0xc3\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0\t\t0xc3\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1\t\t0xc3\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2\t\t0xc3\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3\t\t0xc3\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4\t\t0xc3\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5\t\t0xc3\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6\t\t0xc3\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7\t\t0xc3\n-\t\t\tMX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE\t\t0x83\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK\t\t\t0x85\n-\t\t\tMX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD\t\t\t0xc5\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0\t\t0xc5\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1\t\t0xc5\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2\t\t0xc5\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3\t\t0xc5\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4\t\t0xc5\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5\t\t0xc5\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6\t\t0xc5\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7\t\t0xc5\n-\t\t\tMX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE\t\t0x85\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK\t\t\t0x87\n-\t\t\tMX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD\t\t\t0xc7\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0\t\t0xc7\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1\t\t0xc7\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2\t\t0xc7\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3\t\t0xc7\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4\t\t0xc7\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5\t\t0xc7\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6\t\t0xc7\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7\t\t0xc7\n-\t\t\tMX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE\t\t0x87\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc2_gpio: usdhc2gpiogrp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12\t0x41\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc2: usdhc2grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK\t\t\t0x83\n-\t\t\tMX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD\t\t\t0xc3\n-\t\t\tMX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0\t\t0xc3\n-\t\t\tMX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1\t\t0xc3\n-\t\t\tMX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2\t\t0xc3\n-\t\t\tMX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3\t\t0xc3\n-\t\t\tMX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT\t\t0xc1\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK\t\t\t0x85\n-\t\t\tMX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD\t\t\t0xc5\n-\t\t\tMX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0\t\t0xc5\n-\t\t\tMX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1\t\t0xc5\n-\t\t\tMX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2\t\t0xc5\n-\t\t\tMX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3\t\t0xc5\n-\t\t\tMX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT\t\t0xc1\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK\t\t\t0x87\n-\t\t\tMX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD\t\t\t0xc7\n-\t\t\tMX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0\t\t0xc7\n-\t\t\tMX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1\t\t0xc7\n-\t\t\tMX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2\t\t0xc7\n-\t\t\tMX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3\t\t0xc7\n-\t\t\tMX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT\t\t0xc1\n-\t\t>;\n-\t};\n-\n-\tpinctrl_wdog: wdoggrp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6\n-\t\t>;\n-\t};\n-};\ndiff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig\nindex ef1146cd7f6..6b5903104a5 100644\n--- a/arch/arm/mach-imx/imx8m/Kconfig\n+++ b/arch/arm/mach-imx/imx8m/Kconfig\n@@ -310,6 +310,7 @@ config TARGET_PICO_IMX8MQ\n \tbool \"Support Technexion Pico iMX8MQ\"\n \tselect IMX8MQ\n \tselect IMX8M_LPDDR4\n+\timply OF_UPSTREAM\n \n config TARGET_IMX8MN_VAR_SOM\n \tbool \"Variscite imx8mn_var_som\"\ndiff --git a/configs/pico-imx8mq_defconfig b/configs/pico-imx8mq_defconfig\nindex 2567c5b4715..66fb671c2c6 100644\n--- a/configs/pico-imx8mq_defconfig\n+++ b/configs/pico-imx8mq_defconfig\n@@ -11,7 +11,7 @@ CONFIG_SYS_I2C_MXC_I2C1=y\n CONFIG_SYS_I2C_MXC_I2C2=y\n CONFIG_SYS_I2C_MXC_I2C3=y\n CONFIG_DM_GPIO=y\n-CONFIG_DEFAULT_DEVICE_TREE=\"imx8mq-pico-pi\"\n+CONFIG_DEFAULT_DEVICE_TREE=\"freescale/imx8mq-pico-pi\"\n CONFIG_TARGET_PICO_IMX8MQ=y\n CONFIG_DM_RESET=y\n CONFIG_SYS_MONITOR_LEN=524288\n","prefixes":["03/13"]}