{"id":2228213,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2228213/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20260425-imx8m-of-upstream-v1-2-07527be92e5d@nxp.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.1/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260425-imx8m-of-upstream-v1-2-07527be92e5d@nxp.com>","date":"2026-04-25T00:36:54","name":"[02/13] imx8mq: phanbell: Switch OF_UPSTREAM","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"00729597a19e46ffff07cfa2d5b76e4f33bb5b72","submitter":{"id":80723,"url":"http://patchwork.ozlabs.org/api/1.1/people/80723/?format=json","name":"Peng Fan (OSS)","email":"peng.fan@oss.nxp.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20260425-imx8m-of-upstream-v1-2-07527be92e5d@nxp.com/mbox/","series":[{"id":501451,"url":"http://patchwork.ozlabs.org/api/1.1/series/501451/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=501451","date":"2026-04-25T00:37:04","name":"iMX8M: Covert to OF_UPSTREAM","version":1,"mbox":"http://patchwork.ozlabs.org/series/501451/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2228213/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2228213/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com\n header.a=rsa-sha256 header.s=selector1-NXP1-onmicrosoft-com\n header.b=qBedsfs9;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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phobos.denx.de","X-Virus-Status":"Clean"},"content":"From: Peng Fan \n\narch/arm/dts/imx8mq-phanbell.dts is almost same as upstream Linux dts,\nso switch to OF_UPSTREAM by dropping the U-Boot copy of the dts,\nenabling OF_UPSTREAM and updating CONFIG_DEFAULT_DEVICE_TREE.\n\nSigned-off-by: Peng Fan \n---\n arch/arm/dts/Makefile | 1 -\n arch/arm/dts/imx8mq-phanbell.dts | 481 --------------------------------------\n arch/arm/mach-imx/imx8m/Kconfig | 1 +\n configs/imx8mq_phanbell_defconfig | 2 +-\n 4 files changed, 2 insertions(+), 483 deletions(-)","diff":"diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile\nindex 68ca3b0ad02..4564544bc00 100644\n--- a/arch/arm/dts/Makefile\n+++ b/arch/arm/dts/Makefile\n@@ -879,7 +879,6 @@ dtb-$(CONFIG_ARCH_IMX8M) += \\\n \timx8mm-mx8menlo.dtb \\\n \timx8mm-phg.dtb \\\n \timx8mq-cm.dtb \\\n-\timx8mq-phanbell.dtb \\\n \timx8mp-data-modul-edm-sbc.dtb \\\n \timx8mp-dhcom-som-overlay-rev100.dtbo \\\n \timx8mp-dhcom-som-overlay-eth1xfast.dtbo \\\ndiff --git a/arch/arm/dts/imx8mq-phanbell.dts b/arch/arm/dts/imx8mq-phanbell.dts\ndeleted file mode 100644\nindex a3b9d615a3b..00000000000\n--- a/arch/arm/dts/imx8mq-phanbell.dts\n+++ /dev/null\n@@ -1,481 +0,0 @@\n-// SPDX-License-Identifier: (GPL-2.0 OR MIT)\n-/*\n- * Copyright 2017-2019 NXP\n- */\n-\n-/dts-v1/;\n-\n-#include \"imx8mq.dtsi\"\n-#include \n-\n-/ {\n-\tmodel = \"Google i.MX8MQ Phanbell\";\n-\tcompatible = \"google,imx8mq-phanbell\", \"fsl,imx8mq\";\n-\n-\tchosen {\n-\t\tstdout-path = &uart1;\n-\t};\n-\n-\tmemory@40000000 {\n-\t\tdevice_type = \"memory\";\n-\t\treg = <0x00000000 0x40000000 0 0x40000000>;\n-\t};\n-\n-\tpmic_osc: clock-pmic {\n-\t\tcompatible = \"fixed-clock\";\n-\t\t#clock-cells = <0>;\n-\t\tclock-frequency = <32768>;\n-\t\tclock-output-names = \"pmic_osc\";\n-\t};\n-\n-\treg_usdhc2_vmmc: regulator-usdhc2-vmmc {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tregulator-name = \"VSD_3V3\";\n-\t\tregulator-min-microvolt = <3300000>;\n-\t\tregulator-max-microvolt = <3300000>;\n-\t\tgpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;\n-\t\tenable-active-high;\n-\t};\n-\n-\tfan: gpio-fan {\n-\t\tcompatible = \"gpio-fan\";\n-\t\tgpio-fan,speed-map = <0 0 8600 1>;\n-\t\tgpios = <&gpio3 5 GPIO_ACTIVE_HIGH>;\n-\t\t#cooling-cells = <2>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pinctrl_gpio_fan>;\n-\t\tstatus = \"okay\";\n-\t};\n-};\n-\n-&A53_0 {\n-\tcpu-supply = <&buck2>;\n-};\n-\n-&A53_1 {\n-\tcpu-supply = <&buck2>;\n-};\n-\n-&A53_2 {\n-\tcpu-supply = <&buck2>;\n-};\n-\n-&A53_3 {\n-\tcpu-supply = <&buck2>;\n-};\n-\n-&cpu_thermal {\n-\ttrips {\n-\t\tcpu_alert0: trip0 {\n-\t\t\ttemperature = <75000>;\n-\t\t\thysteresis = <2000>;\n-\t\t\ttype = \"passive\";\n-\t\t};\n-\n-\t\tcpu_alert1: trip1 {\n-\t\t\ttemperature = <80000>;\n-\t\t\thysteresis = <2000>;\n-\t\t\ttype = \"passive\";\n-\t\t};\n-\n-\t\tcpu_crit0: trip3 {\n-\t\t\ttemperature = <90000>;\n-\t\t\thysteresis = <2000>;\n-\t\t\ttype = \"critical\";\n-\t\t};\n-\n-\t\tfan_toggle0: trip4 {\n-\t\t\ttemperature = <65000>;\n-\t\t\thysteresis = <10000>;\n-\t\t\ttype = \"active\";\n-\t\t};\n-\t};\n-\n-\tcooling-maps {\n-\t\tmap0 {\n-\t\t\ttrip = <&cpu_alert0>;\n-\t\t\tcooling-device =\n-\t\t\t<&A53_0 0 1>; /* Exclude highest OPP */\n-\t\t};\n-\n-\t\tmap1 {\n-\t\t\ttrip = <&cpu_alert1>;\n-\t\t\tcooling-device =\n-\t\t\t<&A53_0 0 2>; /* Exclude two highest OPPs */\n-\t\t};\n-\n-\t\tmap4 {\n-\t\t\ttrip = <&fan_toggle0>;\n-\t\t\tcooling-device = <&fan 0 1>;\n-\t\t};\n-\t};\n-};\n-\n-&i2c1 {\n-\tclock-frequency = <400000>;\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_i2c1>;\n-\tstatus = \"okay\";\n-\n-\tpmic: pmic@4b {\n-\t\tcompatible = \"rohm,bd71837\";\n-\t\treg = <0x4b>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pinctrl_pmic>;\n-\t\t#clock-cells = <0>;\n-\t\tclocks = <&pmic_osc>;\n-\t\tclock-output-names = \"pmic_clk\";\n-\t\tinterrupt-parent = <&gpio1>;\n-\t\tinterrupts = <3 IRQ_TYPE_LEVEL_LOW>;\n-\n-\t\tregulators {\n-\t\t\tbuck1: BUCK1 {\n-\t\t\t\tregulator-name = \"buck1\";\n-\t\t\t\tregulator-min-microvolt = <700000>;\n-\t\t\t\tregulator-max-microvolt = <1300000>;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-ramp-delay = <1250>;\n-\t\t\t\trohm,dvs-run-voltage = <900000>;\n-\t\t\t\trohm,dvs-idle-voltage = <900000>;\n-\t\t\t\trohm,dvs-suspend-voltage = <800000>;\n-\t\t\t};\n-\n-\t\t\tbuck2: BUCK2 {\n-\t\t\t\tregulator-name = \"buck2\";\n-\t\t\t\tregulator-min-microvolt = <850000>;\n-\t\t\t\tregulator-max-microvolt = <1000000>;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-always-on;\n-\t\t\t\trohm,dvs-run-voltage = <1000000>;\n-\t\t\t\trohm,dvs-idle-voltage = <900000>;\n-\t\t\t};\n-\n-\t\t\tbuck3: BUCK3 {\n-\t\t\t\tregulator-name = \"buck3\";\n-\t\t\t\tregulator-min-microvolt = <700000>;\n-\t\t\t\tregulator-max-microvolt = <1300000>;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\trohm,dvs-run-voltage = <900000>;\n-\t\t\t};\n-\n-\t\t\tbuck4: BUCK4 {\n-\t\t\t\tregulator-name = \"buck4\";\n-\t\t\t\tregulator-min-microvolt = <700000>;\n-\t\t\t\tregulator-max-microvolt = <1300000>;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-always-on;\n-\t\t\t\trohm,dvs-run-voltage = <900000>;\n-\t\t\t};\n-\n-\t\t\tbuck5: BUCK5 {\n-\t\t\t\tregulator-name = \"buck5\";\n-\t\t\t\tregulator-min-microvolt = <700000>;\n-\t\t\t\tregulator-max-microvolt = <1350000>;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-always-on;\n-\t\t\t};\n-\n-\t\t\tbuck6: BUCK6 {\n-\t\t\t\tregulator-name = \"buck6\";\n-\t\t\t\tregulator-min-microvolt = <3000000>;\n-\t\t\t\tregulator-max-microvolt = <3300000>;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-always-on;\n-\t\t\t};\n-\n-\t\t\tbuck7: BUCK7 {\n-\t\t\t\tregulator-name = \"buck7\";\n-\t\t\t\tregulator-min-microvolt = <1605000>;\n-\t\t\t\tregulator-max-microvolt = <1995000>;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-always-on;\n-\t\t\t};\n-\n-\t\t\tbuck8: BUCK8 {\n-\t\t\t\tregulator-name = \"buck8\";\n-\t\t\t\tregulator-min-microvolt = <800000>;\n-\t\t\t\tregulator-max-microvolt = <1400000>;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-always-on;\n-\t\t\t};\n-\n-\t\t\tldo1: LDO1 {\n-\t\t\t\tregulator-name = \"ldo1\";\n-\t\t\t\tregulator-min-microvolt = <3000000>;\n-\t\t\t\tregulator-max-microvolt = <3300000>;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-always-on;\n-\t\t\t};\n-\n-\t\t\tldo2: LDO2 {\n-\t\t\t\tregulator-name = \"ldo2\";\n-\t\t\t\tregulator-min-microvolt = <900000>;\n-\t\t\t\tregulator-max-microvolt = <900000>;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-always-on;\n-\t\t\t};\n-\n-\t\t\tldo3: LDO3 {\n-\t\t\t\tregulator-name = \"ldo3\";\n-\t\t\t\tregulator-min-microvolt = <1800000>;\n-\t\t\t\tregulator-max-microvolt = <3300000>;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-always-on;\n-\t\t\t};\n-\n-\t\t\tldo4: LDO4 {\n-\t\t\t\tregulator-name = \"ldo4\";\n-\t\t\t\tregulator-min-microvolt = <900000>;\n-\t\t\t\tregulator-max-microvolt = <1800000>;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-always-on;\n-\t\t\t};\n-\n-\t\t\tldo5: LDO5 {\n-\t\t\t\tregulator-name = \"ldo5\";\n-\t\t\t\tregulator-min-microvolt = <1800000>;\n-\t\t\t\tregulator-max-microvolt = <3300000>;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-always-on;\n-\t\t\t};\n-\n-\t\t\tldo6: LDO6 {\n-\t\t\t\tregulator-name = \"ldo6\";\n-\t\t\t\tregulator-min-microvolt = <900000>;\n-\t\t\t\tregulator-max-microvolt = <1800000>;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-always-on;\n-\t\t\t};\n-\n-\t\t\tldo7: LDO7 {\n-\t\t\t\tregulator-name = \"ldo7\";\n-\t\t\t\tregulator-min-microvolt = <1800000>;\n-\t\t\t\tregulator-max-microvolt = <3300000>;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-always-on;\n-\t\t\t};\n-\t\t};\n-\t};\n-};\n-\n-&fec1 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_fec1>;\n-\tphy-mode = \"rgmii-id\";\n-\tphy-handle = <ðphy0>;\n-\tfsl,magic-packet;\n-\tstatus = \"okay\";\n-\n-\tmdio {\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\t\tethphy0: ethernet-phy@0 {\n-\t\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n-\t\t\treg = <0>;\n-\t\t\treset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;\n-\t\t\treset-assert-us = <10000>;\n-\t\t\treset-deassert-us = <50000>;\n-\t\t};\n-\t};\n-};\n-\n-&uart1 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_uart1>;\n-\tstatus = \"okay\";\n-};\n-\n-&usdhc1 {\n-\tpinctrl-names = \"default\", \"state_100mhz\", \"state_200mhz\";\n-\tpinctrl-0 = <&pinctrl_usdhc1>;\n-\tpinctrl-1 = <&pinctrl_usdhc1_100mhz>;\n-\tpinctrl-2 = <&pinctrl_usdhc1_200mhz>;\n-\tbus-width = <8>;\n-\tnon-removable;\n-\tstatus = \"okay\";\n-};\n-\n-&usdhc2 {\n-\tpinctrl-names = \"default\", \"state_100mhz\", \"state_200mhz\";\n-\tpinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;\n-\tpinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;\n-\tpinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;\n-\tbus-width = <4>;\n-\tcd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;\n-\tvmmc-supply = <®_usdhc2_vmmc>;\n-\tstatus = \"okay\";\n-};\n-\n-&usb3_phy0 {\n-\tstatus = \"okay\";\n-};\n-\n-&usb_dwc3_0 {\n-\tdr_mode = \"otg\";\n-\tstatus = \"okay\";\n-};\n-\n-&usb3_phy1 {\n-\tstatus = \"okay\";\n-};\n-\n-&usb_dwc3_1 {\n-\tdr_mode = \"host\";\n-\tstatus = \"okay\";\n-};\n-\n-&wdog1 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_wdog>;\n-\tfsl,ext-reset-output;\n-\tstatus = \"okay\";\n-};\n-\n-&iomuxc {\n-\tpinctrl_fec1: fec1grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MQ_IOMUXC_ENET_MDC_ENET1_MDC\t\t\t0x3\n-\t\t\tMX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO\t\t0x23\n-\t\t\tMX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3\t\t0x1f\n-\t\t\tMX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2\t\t0x1f\n-\t\t\tMX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1\t\t0x1f\n-\t\t\tMX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0\t\t0x1f\n-\t\t\tMX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3\t\t0x91\n-\t\t\tMX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2\t\t0x91\n-\t\t\tMX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1\t\t0x91\n-\t\t\tMX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0\t\t0x91\n-\t\t\tMX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC\t\t0x1f\n-\t\t\tMX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC\t\t0x91\n-\t\t\tMX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL\t0x91\n-\t\t\tMX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL\t0x1f\n-\t\t\tMX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9\t\t0x19\n-\t\t>;\n-\t};\n-\n-\tpinctrl_gpio_fan: gpiofangrp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5\t\t\t0x16\n-\t\t>;\n-\t};\n-\n-\tpinctrl_i2c1: i2c1grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL\t\t\t0x4000007f\n-\t\t\tMX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA\t\t\t0x4000007f\n-\t\t>;\n-\t};\n-\n-\tpinctrl_pmic: pmicirqgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3\t0x41\n-\t\t>;\n-\t};\n-\n-\tpinctrl_uart1: uart1grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX\t\t0x49\n-\t\t\tMX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX\t\t0x49\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc1: usdhc1grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK\t\t\t0x83\n-\t\t\tMX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD\t\t\t0xc3\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0\t\t0xc3\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1\t\t0xc3\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2\t\t0xc3\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3\t\t0xc3\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4\t\t0xc3\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5\t\t0xc3\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6\t\t0xc3\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7\t\t0xc3\n-\t\t\tMX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE\t\t0x83\n-\t\t\tMX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B\t\t0xc1\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK\t\t\t0x85\n-\t\t\tMX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD\t\t\t0xc5\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0\t\t0xc5\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1\t\t0xc5\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2\t\t0xc5\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3\t\t0xc5\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4\t\t0xc5\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5\t\t0xc5\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6\t\t0xc5\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7\t\t0xc5\n-\t\t\tMX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE\t\t0x85\n-\t\t\tMX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B\t\t0xc1\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK\t\t\t0x87\n-\t\t\tMX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD\t\t\t0xc7\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0\t\t0xc7\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1\t\t0xc7\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2\t\t0xc7\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3\t\t0xc7\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4\t\t0xc7\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5\t\t0xc7\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6\t\t0xc7\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7\t\t0xc7\n-\t\t\tMX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE\t\t0x87\n-\t\t\tMX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B\t\t0xc1\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc2_gpio: usdhc2gpiogrp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12\t0x41\n-\t\t\tMX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19\t0x41\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc2: usdhc2grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK\t\t\t0x83\n-\t\t\tMX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD\t\t\t0xc3\n-\t\t\tMX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0\t\t0xc3\n-\t\t\tMX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1\t\t0xc3\n-\t\t\tMX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2\t\t0xc3\n-\t\t\tMX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3\t\t0xc3\n-\t\t\tMX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT\t\t0xc1\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK\t\t\t0x85\n-\t\t\tMX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD\t\t\t0xc5\n-\t\t\tMX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0\t\t0xc5\n-\t\t\tMX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1\t\t0xc5\n-\t\t\tMX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2\t\t0xc5\n-\t\t\tMX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3\t\t0xc5\n-\t\t\tMX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT\t\t0xc1\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK\t\t\t0x87\n-\t\t\tMX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD\t\t\t0xc7\n-\t\t\tMX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0\t\t0xc7\n-\t\t\tMX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1\t\t0xc7\n-\t\t\tMX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2\t\t0xc7\n-\t\t\tMX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3\t\t0xc7\n-\t\t\tMX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT\t\t0xc1\n-\t\t>;\n-\t};\n-\n-\tpinctrl_wdog: wdoggrp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6\n-\t\t>;\n-\t};\n-};\ndiff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig\nindex 40b5de47cfb..ef1146cd7f6 100644\n--- a/arch/arm/mach-imx/imx8m/Kconfig\n+++ b/arch/arm/mach-imx/imx8m/Kconfig\n@@ -79,6 +79,7 @@ config TARGET_IMX8MQ_PHANBELL\n \tbool \"imx8mq_phanbell\"\n \tselect IMX8MQ\n \tselect IMX8M_LPDDR4\n+\timply OF_UPSTREAM\n \n config TARGET_IMX8MQ_REFORM2\n \tbool \"imx8mq_reform2\"\ndiff --git a/configs/imx8mq_phanbell_defconfig b/configs/imx8mq_phanbell_defconfig\nindex 07354a78629..8c68e4fcebd 100644\n--- a/configs/imx8mq_phanbell_defconfig\n+++ b/configs/imx8mq_phanbell_defconfig\n@@ -8,7 +8,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y\n CONFIG_ENV_SIZE=0x1000\n CONFIG_ENV_OFFSET=0x400000\n CONFIG_DM_GPIO=y\n-CONFIG_DEFAULT_DEVICE_TREE=\"imx8mq-phanbell\"\n+CONFIG_DEFAULT_DEVICE_TREE=\"freescale/imx8mq-phanbell\"\n CONFIG_TARGET_IMX8MQ_PHANBELL=y\n CONFIG_DM_RESET=y\n CONFIG_SYS_MONITOR_LEN=524288\n","prefixes":["02/13"]}