{"id":2228199,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2228199/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20260425-imx8m-of-upstream-v1-11-07527be92e5d@nxp.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.1/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260425-imx8m-of-upstream-v1-11-07527be92e5d@nxp.com>","date":"2026-04-25T00:37:03","name":"[11/13] imx8mp: dhcom-drc02/picoitx: Switch to OF_UPSTREAM","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"5c8a94da2b06db530fd0e143a873027e37b54d3b","submitter":{"id":80723,"url":"http://patchwork.ozlabs.org/api/1.1/people/80723/?format=json","name":"Peng Fan (OSS)","email":"peng.fan@oss.nxp.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20260425-imx8m-of-upstream-v1-11-07527be92e5d@nxp.com/mbox/","series":[{"id":501451,"url":"http://patchwork.ozlabs.org/api/1.1/series/501451/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=501451","date":"2026-04-25T00:37:04","name":"iMX8M: Covert to OF_UPSTREAM","version":1,"mbox":"http://patchwork.ozlabs.org/series/501451/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2228199/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2228199/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com\n header.a=rsa-sha256 header.s=selector1-NXP1-onmicrosoft-com\n header.b=ejfElEyW;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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phobos.denx.de","X-Virus-Status":"Clean"},"content":"From: Peng Fan \n\nThe arch/arm/dts/imx8mp-dhcom-drc02.dts,imx8mp-dhcom-picoitx.dts are\nalmost same as the ones in dts/upstream, so switch the board to\nOF_UPSTREAM by dropping copies and selecting OF_UPSTREAM.\n\nSigned-off-by: Peng Fan \n---\n arch/arm/dts/Makefile | 2 -\n arch/arm/dts/imx8mp-dhcom-drc02.dts | 230 -------\n arch/arm/dts/imx8mp-dhcom-picoitx.dts | 152 -----\n arch/arm/dts/imx8mp-dhcom-som.dtsi | 1153 --------------------------------\n configs/imx8mp_dhcom_drc02_defconfig | 3 +-\n configs/imx8mp_dhcom_picoitx_defconfig | 3 +-\n 6 files changed, 4 insertions(+), 1539 deletions(-)","diff":"diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile\nindex aa9437ecb43..434bcbfef32 100644\n--- a/arch/arm/dts/Makefile\n+++ b/arch/arm/dts/Makefile\n@@ -880,9 +880,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \\\n \timx8mp-dhcom-som-overlay-eth1xfast.dtbo \\\n \timx8mp-dhcom-som-overlay-eth2xfast.dtbo \\\n \timx8mp-dhcom-pdk-overlay-eth2xfast.dtbo \\\n-\timx8mp-dhcom-drc02.dtb \\\n \timx8mp-dhcom-pdk3-overlay-rev100.dtbo \\\n-\timx8mp-dhcom-picoitx.dtb \\\n \timx8mp-icore-mx8mp-edimm2.2.dtb \\\n \timx8mp-msc-sm2s.dtb\n \ndiff --git a/arch/arm/dts/imx8mp-dhcom-drc02.dts b/arch/arm/dts/imx8mp-dhcom-drc02.dts\ndeleted file mode 100644\nindex b3ab6e94508..00000000000\n--- a/arch/arm/dts/imx8mp-dhcom-drc02.dts\n+++ /dev/null\n@@ -1,230 +0,0 @@\n-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n-/*\n- * Copyright (C) 2024 Marek Vasut \n- *\n- * DHCOM iMX8MP variant:\n- * DHCM-iMX8ML8-C160-R204-F1638-SPI16-E2-CAN2-RTC-I-01D2\n- * DHCOM PCB number: 660-100 or newer\n- * DRC02 PCB number: 568-100 or newer\n- */\n-\n-/dts-v1/;\n-\n-#include \n-#include \n-#include \"imx8mp-dhcom-som.dtsi\"\n-\n-/ {\n-\tmodel = \"DH electronics i.MX8M Plus DHCOM on DRC02\";\n-\tcompatible = \"dh,imx8mp-dhcom-drc02\", \"dh,imx8mp-dhcom-som\",\n-\t\t \"fsl,imx8mp\";\n-\n-\tchosen {\n-\t\tstdout-path = &uart1;\n-\t};\n-};\n-\n-&eqos {\t/* First ethernet */\n-\tpinctrl-0 = <&pinctrl_eqos_rmii>;\n-\tphy-handle = <ðphy0f>;\n-\tphy-mode = \"rmii\";\n-\n-\tassigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,\n-\t\t\t\t <&clk IMX8MP_SYS_PLL2_100M>,\n-\t\t\t\t <&clk IMX8MP_SYS_PLL2_50M>;\n-\tassigned-clock-rates = <0>, <100000000>, <50000000>;\n-};\n-\n-ðphy0g {\t/* Micrel KSZ9131RNXI */\n-\tstatus = \"disabled\";\n-};\n-\n-ðphy0f {\t/* SMSC LAN8740Ai */\n-\tstatus = \"okay\";\n-};\n-\n-&fec {\t/* Second ethernet */\n-\tpinctrl-0 = <&pinctrl_fec_rmii>;\n-\tphy-handle = <ðphy1f>;\n-\tphy-mode = \"rmii\";\n-\tstatus = \"okay\";\n-\n-\tassigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,\n-\t\t\t\t <&clk IMX8MP_SYS_PLL2_100M>,\n-\t\t\t\t <&clk IMX8MP_SYS_PLL2_50M>,\n-\t\t\t\t <&clk IMX8MP_SYS_PLL2_50M>;\n-\tassigned-clock-rates = <0>, <100000000>, <50000000>, <0>;\n-};\n-\n-ðphy1f {\t/* SMSC LAN8740Ai */\n-\tstatus = \"okay\";\n-};\n-\n-&flexcan1 {\n-\tstatus = \"okay\";\n-};\n-\n-&flexcan2 {\n-\tstatus = \"okay\";\n-};\n-\n-&gpio1 {\n-\tgpio-line-names =\n-\t\t\"DRC02-In1\", \"\", \"\", \"\", \"\", \"DHCOM-I\", \"DRC02-HW2\", \"DRC02-HW0\",\n-\t\t\"DHCOM-B\", \"DHCOM-A\", \"\", \"DHCOM-H\", \"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\";\n-\n-\t/*\n-\t * NOTE: On DRC02, the RS485_RX_En is controlled by a separate\n-\t * GPIO line, however the i.MX8 UART driver assumes RX happens\n-\t * during TX anyway and that it only controls drive enable DE\n-\t * line. Hence, the RX is always enabled here.\n-\t */\n-\trs485-rx-en-hog {\n-\t\tgpio-hog;\n-\t\tgpios = <13 0>; /* GPIO Q */\n-\t\tline-name = \"rs485-rx-en\";\n-\t\toutput-low;\n-\t};\n-};\n-\n-&gpio2 {\n-\tgpio-line-names =\n-\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n-\t\t\"DHCOM-O\", \"DHCOM-N\", \"\", \"SOM-HW1\", \"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\", \"DRC02-In2\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\";\n-};\n-\n-&gpio3 {\n-\tgpio-line-names =\n-\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"SOM-HW0\", \"\",\n-\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"SOM-MEM0\", \"SOM-MEM1\",\n-\t\t\"SOM-MEM2\", \"SOM-HW2\", \"\", \"\", \"\", \"\", \"\", \"\";\n-};\n-\n-&gpio4 {\n-\tgpio-line-names =\n-\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"SOM-HW1\", \"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"DRC02-Out2\", \"\", \"\", \"\", \"\";\n-};\n-\n-&gpio5 {\n-\tgpio-line-names =\n-\t\t\"\", \"\", \"DHCOM-C\", \"\", \"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"DHCOM-E\", \"DRC02-Out1\",\n-\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\";\n-};\n-\n-&i2c3 {\n-\t/* Resistive touch controller not populated on this one SoM variant. */\n-\ttouchscreen@49 {\n-\t\tstatus = \"disabled\";\n-\t};\n-};\n-\n-&pcie_phy {\n-\tstatus = \"disabled\";\n-};\n-\n-&pcie {\n-\tstatus = \"disabled\";\n-};\n-\n-/* Console UART */\n-&pinctrl_uart1 {\n-\tfsl,pins = <\n-\t\t/* No pull-ups on DRC02, enable in-SoC pull-ups */\n-\t\tMX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX\t\t0x149\n-\t\tMX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX\t\t0x149\n-\t>;\n-};\n-\n-&pinctrl_uart3 {\n-\tfsl,pins = <\n-\t\t/* No pull-ups on DRC02, enable in-SoC pull-ups */\n-\t\tMX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX\t\t0x149\n-\t\tMX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX\t\t0x149\n-\t>;\n-};\n-\n-&uart1 {\n-\t/*\n-\t * Due to the use of CAN2 the signals for CAN2 Tx and Rx are routed to\n-\t * DHCOM UART1 RTS/CTS pins. Therefore this UART have to use DHCOM GPIOs\n-\t * for RTS/CTS. So configure DHCOM GPIO I as RTS and GPIO M as CTS.\n-\t */\n-\t/delete-property/ uart-has-rtscts;\n-\tcts-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; /* GPIO M */\n-\tpinctrl-0 = <&pinctrl_uart1 &pinctrl_dhcom_i &pinctrl_dhcom_m>;\n-\tpinctrl-names = \"default\";\n-\trts-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; /* GPIO I */\n-};\n-\n-&uart3 {\n-\t/*\n-\t * On DRC02 this UART is used as RS485 interface and RS485_TX_En is\n-\t * controlled by DHCOM GPIO P. So remove RTS/CTS pins and the property\n-\t * uart-has-rtscts from this UART and add the DHCOM GPIO P pin via\n-\t * rts-gpios. The RS485_RX_En is controlled by DHCOM GPIO Q, see gpio1\n-\t * node above.\n-\t */\n-\t/delete-property/ uart-has-rtscts;\n-\tlinux,rs485-enabled-at-boot-time;\n-\tpinctrl-0 = <&pinctrl_uart3 &pinctrl_dhcom_p &pinctrl_dhcom_q>;\n-\tpinctrl-names = \"default\";\n-\trts-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; /* GPIO P */\n-};\n-\n-/* No WiFi/BT chipset on this SoM variant. */\n-&uart2 {\n-\tbluetooth {\n-\t\tstatus = \"disabled\";\n-\t};\n-};\n-\n-/* USB_OTG port is not routed out on DRC02. */\n-&usb3_0 {\n-\tstatus = \"disabled\";\n-};\n-\n-&usb_dwc3_0 {\n-\tstatus = \"disabled\";\n-};\n-\n-/* USB_HOST port has USB Hub connected to it, PWR/OC pins are unused */\n-&usb3_1 {\n-\tfsl,disable-port-power-control;\n-\tfsl,permanently-attached;\n-};\n-\n-&usb_dwc3_1 {\n-\tdr_mode = \"host\";\n-\tmaximum-speed = \"high-speed\";\n-};\n-\n-/* No WiFi/BT chipset on this SoM variant. */\n-&usdhc1 {\n-\tstatus = \"disabled\";\n-};\n-\n-&iomuxc {\n-\t/*\n-\t * GPIO I is connected to UART1_RTS\n-\t * GPIO M is connected to UART1_CTS\n-\t * GPIO P is connected to RS485_TX_En\n-\t * GPIO Q is connected to RS485_RX_En\n-\t */\n-\tpinctrl-0 = <&pinctrl_hog_base\n-\t\t &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c\n-\t\t &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f\n-\t\t &pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_j\n-\t\t &pinctrl_dhcom_k &pinctrl_dhcom_l &pinctrl_dhcom_n\n-\t\t &pinctrl_dhcom_o &pinctrl_dhcom_r &pinctrl_dhcom_s\n-\t\t &pinctrl_dhcom_int>;\n-};\ndiff --git a/arch/arm/dts/imx8mp-dhcom-picoitx.dts b/arch/arm/dts/imx8mp-dhcom-picoitx.dts\ndeleted file mode 100644\nindex 285aaa5b6c0..00000000000\n--- a/arch/arm/dts/imx8mp-dhcom-picoitx.dts\n+++ /dev/null\n@@ -1,152 +0,0 @@\n-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n-/*\n- * Copyright (C) 2023-2024 Marek Vasut \n- *\n- * DHCOM iMX8MP variant:\n- * DHCM-iMX8ML8-C160-R204-F1638-SPI16-E-SD-RTC-T-RGB-I-01D2\n- * DHCOM PCB number: 660-200 or newer\n- * PicoITX PCB number: 487-600 or newer\n- */\n-\n-/dts-v1/;\n-\n-#include \n-#include \"imx8mp-dhcom-som.dtsi\"\n-\n-/ {\n-\tmodel = \"DH electronics i.MX8M Plus DHCOM PicoITX\";\n-\tcompatible = \"dh,imx8mp-dhcom-picoitx\", \"dh,imx8mp-dhcom-som\",\n-\t\t \"fsl,imx8mp\";\n-\n-\tchosen {\n-\t\tstdout-path = &uart1;\n-\t};\n-\n-\tled {\n-\t\tcompatible = \"gpio-leds\";\n-\n-\t\tled-0 {\n-\t\t\tcolor = ;\n-\t\t\tdefault-state = \"off\";\n-\t\t\tfunction = LED_FUNCTION_INDICATOR;\n-\t\t\tgpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; /* GPIO I */\n-\t\t\tpinctrl-0 = <&pinctrl_dhcom_i>;\n-\t\t\tpinctrl-names = \"default\";\n-\t\t};\n-\t};\n-};\n-\n-&eqos {\t/* First ethernet */\n-\tpinctrl-0 = <&pinctrl_eqos_rmii>;\n-\tphy-handle = <ðphy0f>;\n-\tphy-mode = \"rmii\";\n-\n-\tassigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,\n-\t\t\t\t <&clk IMX8MP_SYS_PLL2_100M>,\n-\t\t\t\t <&clk IMX8MP_SYS_PLL2_50M>;\n-\tassigned-clock-rates = <0>, <100000000>, <50000000>;\n-};\n-\n-ðphy0g {\t/* Micrel KSZ9131RNXI */\n-\tstatus = \"disabled\";\n-};\n-\n-ðphy0f {\t/* SMSC LAN8740Ai */\n-\tstatus = \"okay\";\n-};\n-\n-&fec {\n-\tstatus = \"disabled\";\n-};\n-\n-&flexcan1 {\n-\tstatus = \"okay\";\n-};\n-\n-&gpio1 {\n-\tgpio-line-names =\n-\t\t\"DHCOM-G\", \"\", \"\", \"\",\n-\t\t\"\", \"DHCOM-I\", \"PicoITX-HW0\", \"PicoITX-HW2\",\n-\t\t\"DHCOM-B\", \"DHCOM-A\", \"\", \"DHCOM-H\", \"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\";\n-};\n-\n-&gpio2 {\n-\tgpio-line-names =\n-\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"PicoITX-HW1\", \"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\", \"DHCOM-INT\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\";\n-};\n-\n-&gpio4 {\n-\tgpio-line-names =\n-\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"SOM-HW1\", \"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"PicoITX-Out2\", \"\", \"\", \"\", \"\";\n-};\n-\n-&gpio5 {\n-\tgpio-line-names =\n-\t\t\"\", \"\", \"PicoITX-In2\", \"\", \"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"PicoITX-In1\", \"PicoITX-Out1\",\n-\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\";\n-};\n-\n-/* No HS connector on this SoM variant, so no HDMI, PCIe and only USB HS. */\n-&pcie_phy {\n-\tstatus = \"disabled\";\n-};\n-\n-&pcie {\n-\tstatus = \"disabled\";\n-};\n-\n-/* No WiFi/BT chipset on this SoM variant. */\n-&uart2 {\n-\tbluetooth {\n-\t\tstatus = \"disabled\";\n-\t};\n-};\n-\n-/* USB_OTG port is not routed out on PicoITX. */\n-&usb3_0 {\n-\tstatus = \"disabled\";\n-};\n-\n-&usb_dwc3_0 {\n-\tstatus = \"disabled\";\n-};\n-\n-&usb3_1 {\n-\tfsl,over-current-active-low;\n-};\n-\n-&usb_dwc3_1 {\n-\tdr_mode = \"host\";\n-\tmaximum-speed = \"high-speed\";\n-};\n-\n-/* No WiFi/BT chipset on this SoM variant. */\n-&usdhc1 {\n-\tstatus = \"disabled\";\n-};\n-\n-&iomuxc {\n-\t/*\n-\t * The following DHCOM GPIOs are used on this board.\n-\t * Therefore, they have been removed from the list below.\n-\t * I: yellow led\n-\t */\n-\tpinctrl-0 = <&pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c\n-\t\t &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f\n-\t\t &pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_j\n-\t\t &pinctrl_dhcom_k &pinctrl_dhcom_l &pinctrl_dhcom_m\n-\t\t &pinctrl_dhcom_n &pinctrl_dhcom_o &pinctrl_dhcom_p\n-\t\t &pinctrl_dhcom_q &pinctrl_dhcom_r &pinctrl_dhcom_s\n-\t\t &pinctrl_dhcom_int>;\n-};\ndiff --git a/arch/arm/dts/imx8mp-dhcom-som.dtsi b/arch/arm/dts/imx8mp-dhcom-som.dtsi\ndeleted file mode 100644\nindex c1ca3805737..00000000000\n--- a/arch/arm/dts/imx8mp-dhcom-som.dtsi\n+++ /dev/null\n@@ -1,1153 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0\n-/*\n- * Copyright (C) 2021-2022 Marek Vasut \n- */\n-\n-#include \"imx8mp.dtsi\"\n-\n-/ {\n-\tmodel = \"DH electronics i.MX8M Plus DHCOM SoM\";\n-\tcompatible = \"dh,imx8mp-dhcom-som\", \"fsl,imx8mp\";\n-\n-\taliases {\n-\t\tethernet0 = &eqos;\n-\t\tethernet1 = &fec;\n-\t\trtc0 = &rv3032;\n-\t\trtc1 = &snvs_rtc;\n-\t\tspi0 = &flexspi;\n-\t};\n-\n-\tmemory@40000000 {\n-\t\tdevice_type = \"memory\";\n-\t\t/* Memory size 512 MiB..8 GiB will be filled by U-Boot */\n-\t\treg = <0x0 0x40000000 0 0x08000000>;\n-\t};\n-\n-\treg_eth_vio: regulator-eth-vio {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tgpio = <&ioexp 2 GPIO_ACTIVE_LOW>;\n-\t\tregulator-always-on;\n-\t\tregulator-boot-on;\n-\t\tregulator-min-microvolt = <3300000>;\n-\t\tregulator-max-microvolt = <3300000>;\n-\t\tregulator-name = \"eth_vio\";\n-\t\tvin-supply = <&buck4>;\n-\t};\n-\n-\treg_usdhc2_vmmc: regulator-usdhc2-vmmc {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tenable-active-high;\n-\t\tgpio = <&gpio2 19 0>; /* SD2_RESET */\n-\t\toff-on-delay-us = <12000>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pinctrl_usdhc2_vmmc>;\n-\t\tregulator-max-microvolt = <3300000>;\n-\t\tregulator-min-microvolt = <3300000>;\n-\t\tregulator-name = \"VDD_3V3_SD\";\n-\t\tstartup-delay-us = <100>;\n-\t\tvin-supply = <&buck4>;\n-\t};\n-\n-\treg_vdd_3p3v_awo: regulator-vdd-3p3v-awo {\t/* VDD_3V3_AWO */\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tregulator-always-on;\n-\t\tregulator-min-microvolt = <3300000>;\n-\t\tregulator-max-microvolt = <3300000>;\n-\t\tregulator-name = \"VDD_3P3V_AWO\";\n-\t};\n-};\n-\n-&A53_0 {\n-\tcpu-supply = <&buck2>;\n-};\n-\n-&A53_1 {\n-\tcpu-supply = <&buck2>;\n-};\n-\n-&A53_2 {\n-\tcpu-supply = <&buck2>;\n-};\n-\n-&A53_3 {\n-\tcpu-supply = <&buck2>;\n-};\n-\n-&ecspi1 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_ecspi1>;\n-\tcs-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;\n-\tstatus = \"disabled\";\n-};\n-\n-&ecspi2 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_ecspi2>;\n-\tcs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;\n-\tstatus = \"disabled\";\n-};\n-\n-&eqos {\t/* First ethernet */\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_eqos_rgmii>;\n-\tphy-handle = <ðphy0g>;\n-\tphy-mode = \"rgmii-id\";\n-\tstatus = \"okay\";\n-\n-\tmdio {\n-\t\tcompatible = \"snps,dwmac-mdio\";\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\n-\t\t/* Up to one of these two PHYs may be populated. */\n-\t\tethphy0f: ethernet-phy@1 { /* SMSC LAN8740Ai */\n-\t\t\tcompatible = \"ethernet-phy-id0007.c110\",\n-\t\t\t\t \"ethernet-phy-ieee802.3-c22\";\n-\t\t\tinterrupt-parent = <&gpio3>;\n-\t\t\tinterrupts = <19 IRQ_TYPE_LEVEL_LOW>;\n-\t\t\tpinctrl-0 = <&pinctrl_ethphy0>;\n-\t\t\tpinctrl-names = \"default\";\n-\t\t\treg = <1>;\n-\t\t\treset-assert-us = <1000>;\n-\t\t\treset-deassert-us = <1000>;\n-\t\t\treset-gpios = <&ioexp 4 GPIO_ACTIVE_LOW>;\n-\t\t\t/* Non-default PHY population option. */\n-\t\t\tstatus = \"disabled\";\n-\t\t};\n-\n-\t\tethphy0g: ethernet-phy@5 { /* Micrel KSZ9131RNXI */\n-\t\t\tcompatible = \"ethernet-phy-id0022.1642\",\n-\t\t\t\t \"ethernet-phy-ieee802.3-c22\";\n-\t\t\tinterrupt-parent = <&gpio3>;\n-\t\t\tinterrupts = <19 IRQ_TYPE_LEVEL_LOW>;\n-\t\t\tmicrel,led-mode = <0>;\n-\t\t\tpinctrl-0 = <&pinctrl_ethphy0>;\n-\t\t\tpinctrl-names = \"default\";\n-\t\t\treg = <5>;\n-\t\t\treset-assert-us = <1000>;\n-\t\t\treset-deassert-us = <1000>;\n-\t\t\treset-gpios = <&ioexp 4 GPIO_ACTIVE_LOW>;\n-\t\t\t/* Default PHY population option. */\n-\t\t\tstatus = \"okay\";\n-\t\t};\n-\t};\n-};\n-\n-&fec {\t/* Second ethernet */\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_fec_rmii>;\n-\tphy-handle = <ðphy1f>;\n-\tphy-mode = \"rmii\";\n-\tfsl,magic-packet;\n-\tstatus = \"okay\";\n-\n-\tmdio {\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\n-\t\t/* Up to one PHY may be populated. */\n-\t\tethphy1f: ethernet-phy@2 { /* SMSC LAN8740Ai */\n-\t\t\tcompatible = \"ethernet-phy-id0007.c110\",\n-\t\t\t\t \"ethernet-phy-ieee802.3-c22\";\n-\t\t\tinterrupt-parent = <&gpio4>;\n-\t\t\tinterrupts = <3 IRQ_TYPE_LEVEL_LOW>;\n-\t\t\tpinctrl-0 = <&pinctrl_ethphy1>;\n-\t\t\tpinctrl-names = \"default\";\n-\t\t\treg = <2>;\n-\t\t\treset-assert-us = <1000>;\n-\t\t\treset-deassert-us = <1000>;\n-\t\t\treset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;\n-\t\t\t/* Non-default PHY population option. */\n-\t\t\tstatus = \"disabled\";\n-\t\t};\n-\t};\n-};\n-\n-&flexcan1 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_flexcan1>;\n-\tstatus = \"disabled\";\n-};\n-\n-&flexcan2 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_flexcan2>;\n-\tstatus = \"disabled\";\n-};\n-\n-&flexspi {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_flexspi>;\n-\tstatus = \"okay\";\n-\n-\tflash@0 {\t/* W25Q128JWPIM */\n-\t\tcompatible = \"jedec,spi-nor\";\n-\t\treg = <0>;\n-\t\tspi-max-frequency = <80000000>;\n-\t\tspi-tx-bus-width = <4>;\n-\t\tspi-rx-bus-width = <4>;\n-\t};\n-};\n-\n-&gpio1 {\n-\tgpio-line-names =\n-\t\t\"DHCOM-G\", \"\", \"\", \"\", \"\", \"DHCOM-I\", \"DHCOM-J\", \"DHCOM-L\",\n-\t\t\"DHCOM-B\", \"DHCOM-A\", \"\", \"DHCOM-H\", \"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\";\n-};\n-\n-&gpio2 {\n-\tgpio-line-names =\n-\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"DHCOM-K\", \"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\", \"DHCOM-INT\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\";\n-};\n-\n-&gpio3 {\n-\tgpio-line-names =\n-\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"SOM-HW0\", \"\",\n-\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"SOM-MEM0\", \"SOM-MEM1\",\n-\t\t\"SOM-MEM2\", \"SOM-HW2\", \"\", \"\", \"\", \"\", \"\", \"\";\n-};\n-\n-&gpio4 {\n-\tgpio-line-names =\n-\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"SOM-HW1\", \"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"DHCOM-D\", \"\", \"\", \"\", \"\";\n-};\n-\n-&gpio5 {\n-\tgpio-line-names =\n-\t\t\"\", \"\", \"DHCOM-C\", \"\", \"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"DHCOM-E\", \"DHCOM-F\",\n-\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\";\n-};\n-\n-&i2c3 {\n-\tclock-frequency = <100000>;\n-\tpinctrl-names = \"default\", \"gpio\";\n-\tpinctrl-0 = <&pinctrl_i2c3>;\n-\tpinctrl-1 = <&pinctrl_i2c3_gpio>;\n-\tscl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n-\tsda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n-\tstatus = \"okay\";\n-\n-\tpmic: pmic@25 {\n-\t\tcompatible = \"nxp,pca9450c\";\n-\t\treg = <0x25>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pinctrl_pmic>;\n-\t\tinterrupt-parent = <&gpio1>;\n-\t\tinterrupts = <3 IRQ_TYPE_LEVEL_LOW>;\n-\n-\t\t/*\n-\t\t * i.MX 8M Plus Data Sheet for Consumer Products\n-\t\t * 3.1.4 Operating ranges\n-\t\t * MIMX8ML8CVNKZAB\n-\t\t */\n-\t\tregulators {\n-\t\t\tbuck1: BUCK1 {\t/* VDD_SOC (dual-phase with BUCK3) */\n-\t\t\t\tregulator-compatible = \"BUCK1\";\n-\t\t\t\tregulator-min-microvolt = <850000>;\n-\t\t\t\tregulator-max-microvolt = <1000000>;\n-\t\t\t\tregulator-ramp-delay = <3125>;\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t};\n-\n-\t\t\tbuck2: BUCK2 {\t/* VDD_ARM */\n-\t\t\t\tregulator-compatible = \"BUCK2\";\n-\t\t\t\tregulator-min-microvolt = <850000>;\n-\t\t\t\tregulator-max-microvolt = <1000000>;\n-\t\t\t\tregulator-ramp-delay = <3125>;\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t};\n-\n-\t\t\tbuck4: BUCK4 {\t/* VDD_3V3 */\n-\t\t\t\tregulator-compatible = \"BUCK4\";\n-\t\t\t\tregulator-min-microvolt = <3300000>;\n-\t\t\t\tregulator-max-microvolt = <3300000>;\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t};\n-\n-\t\t\tbuck5: BUCK5 {\t/* VDD_1V8 */\n-\t\t\t\tregulator-compatible = \"BUCK5\";\n-\t\t\t\tregulator-min-microvolt = <1800000>;\n-\t\t\t\tregulator-max-microvolt = <1800000>;\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t};\n-\n-\t\t\tbuck6: BUCK6 {\t/* NVCC_DRAM_1V1 */\n-\t\t\t\tregulator-compatible = \"BUCK6\";\n-\t\t\t\tregulator-min-microvolt = <1100000>;\n-\t\t\t\tregulator-max-microvolt = <1100000>;\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t};\n-\n-\t\t\tldo1: LDO1 {\t/* NVCC_SNVS_1V8 */\n-\t\t\t\tregulator-compatible = \"LDO1\";\n-\t\t\t\tregulator-min-microvolt = <1800000>;\n-\t\t\t\tregulator-max-microvolt = <1800000>;\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t};\n-\n-\t\t\tldo3: LDO3 {\t/* VDDA_1V8 */\n-\t\t\t\tregulator-compatible = \"LDO3\";\n-\t\t\t\tregulator-min-microvolt = <1800000>;\n-\t\t\t\tregulator-max-microvolt = <1800000>;\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t};\n-\n-\t\t\tldo4: LDO4 {\t/* PMIC_LDO4 */\n-\t\t\t\tregulator-compatible = \"LDO4\";\n-\t\t\t\tregulator-min-microvolt = <3300000>;\n-\t\t\t\tregulator-max-microvolt = <3300000>;\n-\t\t\t};\n-\n-\t\t\tldo5: LDO5 {\t/* NVCC_SD2 */\n-\t\t\t\tregulator-compatible = \"LDO5\";\n-\t\t\t\tregulator-min-microvolt = <1800000>;\n-\t\t\t\tregulator-max-microvolt = <3300000>;\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-\tadc@48 {\n-\t\tcompatible = \"ti,ads1015\";\n-\t\treg = <0x48>;\n-\t\tinterrupts-extended = <&ioexp 7 IRQ_TYPE_EDGE_FALLING>;\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\n-\t\tchannel@0 {\t/* Voltage over AIN0 and AIN1. */\n-\t\t\treg = <0>;\n-\t\t};\n-\n-\t\tchannel@1 {\t/* Voltage over AIN0 and AIN3. */\n-\t\t\treg = <1>;\n-\t\t};\n-\n-\t\tchannel@2 {\t/* Voltage over AIN1 and AIN3. */\n-\t\t\treg = <2>;\n-\t\t};\n-\n-\t\tchannel@3 {\t/* Voltage over AIN2 and AIN3. */\n-\t\t\treg = <3>;\n-\t\t};\n-\n-\t\tchannel@4 {\t/* Voltage over AIN0 and GND. */\n-\t\t\treg = <4>;\n-\t\t};\n-\n-\t\tchannel@5 {\t/* Voltage over AIN1 and GND. */\n-\t\t\treg = <5>;\n-\t\t};\n-\n-\t\tchannel@6 {\t/* Voltage over AIN2 and GND. */\n-\t\t\treg = <6>;\n-\t\t};\n-\n-\t\tchannel@7 {\t/* Voltage over AIN3 and GND. */\n-\t\t\treg = <7>;\n-\t\t};\n-\t};\n-\n-\ttouchscreen@49 {\n-\t\tcompatible = \"ti,tsc2004\";\n-\t\treg = <0x49>;\n-\t\tinterrupts-extended = <&gpio4 0 IRQ_TYPE_EDGE_FALLING>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pinctrl_touch>;\n-\t\tvio-supply = <&buck4>;\n-\t};\n-\n-\teeprom0: eeprom@50 {\t/* EEPROM with EQoS MAC address */\n-\t\tcompatible = \"atmel,24c32\";\t/* M24C32-D */\n-\t\tpagesize = <32>;\n-\t\treg = <0x50>;\n-\t};\n-\n-\trv3032: rtc@51 {\n-\t\tcompatible = \"microcrystal,rv3032\";\n-\t\treg = <0x51>;\n-\t\tinterrupts-extended = <&ioexp 3 IRQ_TYPE_EDGE_FALLING>;\n-\t};\n-\n-\teeprom1: eeprom@53 {\t/* EEPROM with FEC MAC address */\n-\t\tcompatible = \"atmel,24c32\";\t/* M24C32-D */\n-\t\tpagesize = <32>;\n-\t\treg = <0x53>;\n-\t};\n-\n-\teeprom0wl: eeprom@58 {\n-\t\tcompatible = \"atmel,24c32d-wl\";\t/* M24C32-D WL page of 0x50 */\n-\t\tpagesize = <32>;\n-\t\treg = <0x58>;\n-\t};\n-\n-\teeprom1wl: eeprom@5b {\n-\t\tcompatible = \"atmel,24c32d-wl\";\t/* M24C32-D WL page of 0x53 */\n-\t\tpagesize = <32>;\n-\t\treg = <0x5b>;\n-\t};\n-\n-\tioexp: gpio@74 {\n-\t\tcompatible = \"nxp,pca9539\";\n-\t\treg = <0x74>;\n-\t\tgpio-controller;\n-\t\t#gpio-cells = <2>;\n-\t\tinterrupts-extended = <&gpio3 20 IRQ_TYPE_LEVEL_LOW>;\n-\t\tinterrupt-controller;\n-\t\t#interrupt-cells = <2>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pinctrl_ioexp>;\n-\n-\t\tgpio-line-names =\n-\t\t\t\"BT_REG_EN\", \"WL_REG_EN\", \"VIO_SWITCHED_#EN\", \"RTC_#INT\",\n-\t\t\t\"ENET_QOS_#RST\", \"RGB_OSZ_ENABLE\", \"USB1_ID\", \"ADC_ALTER_RDY\",\n-\t\t\t\"DHCOM-W\", \"DHCOM-V\", \"DHCOM-U\", \"DHCOM-T\",\n-\t\t\t\"BT_HOST_WAKE\", \"BT_DEV_WAKE\", \"\", \"\";\n-\t};\n-};\n-\n-&i2c4 {\n-\tclock-frequency = <100000>;\n-\tpinctrl-names = \"default\", \"gpio\";\n-\tpinctrl-0 = <&pinctrl_i2c4>;\n-\tpinctrl-1 = <&pinctrl_i2c4_gpio>;\n-\tscl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n-\tsda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n-\tstatus = \"okay\";\n-};\n-\n-&i2c5 {\t/* HDMI EDID bus */\n-\tclock-frequency = <100000>;\n-\tpinctrl-names = \"default\", \"gpio\";\n-\tpinctrl-0 = <&pinctrl_i2c5>;\n-\tpinctrl-1 = <&pinctrl_i2c5_gpio>;\n-\tscl-gpios = <&gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n-\tsda-gpios = <&gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n-\tstatus = \"okay\";\n-};\n-\n-&pwm1 {\n-\tpinctrl-0 = <&pinctrl_pwm1>;\n-\tpinctrl-names = \"default\";\n-\tstatus = \"disabled\";\n-};\n-\n-&uart1 {\n-\t/* CA53 console */\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_uart1>;\n-\tstatus = \"okay\";\n-};\n-\n-&uart2 {\n-\t/* Bluetooth */\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_uart2>;\n-\tuart-has-rtscts;\n-\tstatus = \"okay\";\n-\n-\t/*\n-\t * PLL1 at 80 MHz supplies UART2 root with 80 MHz clock,\n-\t * which with 16x oversampling yields 5 Mbdps baud base,\n-\t * which can be well divided by 5/4 to achieve 4 Mbdps,\n-\t * which is exactly the maximum rate supported by muRata\n-\t * 2AE bluetooth UART.\n-\t */\n-\tassigned-clocks = <&clk IMX8MP_CLK_UART2>;\n-\tassigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;\n-\tassigned-clock-rates = <80000000>;\n-\n-\tbluetooth {\n-\t\tcompatible = \"cypress,cyw4373a0-bt\";\n-\t\tshutdown-gpios = <&ioexp 0 GPIO_ACTIVE_HIGH>;\n-\t\tmax-speed = <4000000>;\n-\t};\n-};\n-\n-&uart3 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_uart3>;\n-\tuart-has-rtscts;\n-\tstatus = \"okay\";\n-};\n-\n-&uart4 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_uart4>;\n-\tstatus = \"okay\";\n-};\n-\n-&usb3_phy0 {\n-\tstatus = \"okay\";\n-};\n-\n-&usb3_0 {\n-\tstatus = \"okay\";\n-};\n-\n-&usb_dwc3_0 {\n-\tdr_mode = \"otg\";\n-\tstatus = \"okay\";\n-};\n-\n-&usb3_phy1 {\n-\tstatus = \"okay\";\n-};\n-\n-&usb3_1 {\n-\tstatus = \"okay\";\n-};\n-\n-&usb_dwc3_1 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_usb1_vbus>;\n-\tdr_mode = \"host\";\n-\tstatus = \"okay\";\n-};\n-\n-/* SDIO WiFi */\n-&usdhc1 {\n-\tpinctrl-names = \"default\", \"state_100mhz\", \"state_200mhz\";\n-\tpinctrl-0 = <&pinctrl_usdhc1>;\n-\tpinctrl-1 = <&pinctrl_usdhc1_100mhz>;\n-\tpinctrl-2 = <&pinctrl_usdhc1_200mhz>;\n-\tvmmc-supply = <&buck4>;\n-\tbus-width = <4>;\n-\tnon-removable;\n-\tcap-power-off-card;\n-\tkeep-power-in-suspend;\n-\tstatus = \"okay\";\n-\n-\t#address-cells = <1>;\n-\t#size-cells = <0>;\n-\n-\tbrcmf: bcrmf@1 {\t/* muRata 2AE */\n-\t\treg = <1>;\n-\t\tcompatible = \"cypress,cyw4373-fmac\", \"brcm,bcm4329-fmac\";\n-\t\t/*\n-\t\t * The \"host-wake\" interrupt output is by default not\n-\t\t * connected to the SoC, but can be connected on to\n-\t\t * SoC pin on the carrier board.\n-\t\t */\n-\t\treset-gpios = <&ioexp 1 GPIO_ACTIVE_LOW>;\n-\t};\n-};\n-\n-/* SD slot */\n-&usdhc2 {\n-\tpinctrl-names = \"default\", \"state_100mhz\", \"state_200mhz\";\n-\tpinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;\n-\tpinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;\n-\tpinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;\n-\tcd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;\n-\tvmmc-supply = <®_usdhc2_vmmc>;\n-\tbus-width = <4>;\n-\tstatus = \"okay\";\n-};\n-\n-/* eMMC */\n-&usdhc3 {\n-\tpinctrl-names = \"default\", \"state_100mhz\", \"state_200mhz\";\n-\tpinctrl-0 = <&pinctrl_usdhc3>;\n-\tpinctrl-1 = <&pinctrl_usdhc3_100mhz>;\n-\tpinctrl-2 = <&pinctrl_usdhc3_200mhz>;\n-\tvmmc-supply = <&buck4>;\n-\tvqmmc-supply = <&buck5>;\n-\tbus-width = <8>;\n-\tnon-removable;\n-\tstatus = \"okay\";\n-};\n-\n-&wdog1 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_wdog>;\n-\tfsl,ext-reset-output;\n-\tstatus = \"okay\";\n-};\n-\n-&iomuxc {\n-\tpinctrl-0 = <&pinctrl_hog_base\n-\t\t &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c\n-\t\t &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f\n-\t\t &pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_i\n-\t\t &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l\n-\t\t &pinctrl_dhcom_m &pinctrl_dhcom_n &pinctrl_dhcom_o\n-\t\t &pinctrl_dhcom_p &pinctrl_dhcom_q &pinctrl_dhcom_r\n-\t\t &pinctrl_dhcom_s &pinctrl_dhcom_int>;\n-\tpinctrl-names = \"default\";\n-\n-\tpinctrl_dhcom_a: dhcom-a-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* ENET_QOS_EVENT0-OUT */\n-\t\t\tMX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09\t\t0x2\n-\t\t>;\n-\t};\n-\n-\tpinctrl_dhcom_b: dhcom-b-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* ENET_QOS_EVENT0-IN */\n-\t\t\tMX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08\t\t0x2\n-\t\t>;\n-\t};\n-\n-\tpinctrl_dhcom_c: dhcom-c-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* GPIO_C */\n-\t\t\tMX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02\t\t0x2\n-\t\t>;\n-\t};\n-\n-\tpinctrl_dhcom_d: dhcom-d-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* GPIO_D */\n-\t\t\tMX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27\t\t0x2\n-\t\t>;\n-\t};\n-\n-\tpinctrl_dhcom_e: dhcom-e-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* GPIO_E */\n-\t\t\tMX8MP_IOMUXC_UART1_RXD__GPIO5_IO22\t\t0x2\n-\t\t>;\n-\t};\n-\n-\tpinctrl_dhcom_f: dhcom-f-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* GPIO_F */\n-\t\t\tMX8MP_IOMUXC_UART1_TXD__GPIO5_IO23\t\t0x2\n-\t\t>;\n-\t};\n-\n-\tpinctrl_dhcom_g: dhcom-g-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* GPIO_G */\n-\t\t\tMX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00\t\t0x2\n-\t\t>;\n-\t};\n-\n-\tpinctrl_dhcom_h: dhcom-h-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* GPIO_H */\n-\t\t\tMX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11\t\t0x2\n-\t\t>;\n-\t};\n-\n-\tpinctrl_dhcom_i: dhcom-i-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* CSI1_SYNC */\n-\t\t\tMX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05\t\t0x2\n-\t\t>;\n-\t};\n-\n-\tpinctrl_dhcom_j: dhcom-j-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* CSIx_#RST */\n-\t\t\tMX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06\t\t0x2\n-\t\t>;\n-\t};\n-\n-\tpinctrl_dhcom_k: dhcom-k-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* CSIx_PWDN */\n-\t\t\tMX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11\t\t0x2\n-\t\t>;\n-\t};\n-\n-\tpinctrl_dhcom_l: dhcom-l-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* CSI2_SYNC */\n-\t\t\tMX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07\t\t0x2\n-\t\t>;\n-\t};\n-\n-\tpinctrl_dhcom_m: dhcom-m-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* CSIx_MCLK */\n-\t\t\tMX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05\t\t0x2\n-\t\t>;\n-\t};\n-\n-\tpinctrl_dhcom_n: dhcom-n-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* CSI2_D3- */\n-\t\t\tMX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09\t\t0x2\n-\t\t>;\n-\t};\n-\n-\tpinctrl_dhcom_o: dhcom-o-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* CSI2_D3+ */\n-\t\t\tMX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08\t\t0x2\n-\t\t>;\n-\t};\n-\n-\tpinctrl_dhcom_p: dhcom-p-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* CSI2_D2- */\n-\t\t\tMX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10\t\t0x2\n-\t\t>;\n-\t};\n-\n-\tpinctrl_dhcom_q: dhcom-q-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* CSI2_D2+ */\n-\t\t\tMX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13\t\t0x2\n-\t\t>;\n-\t};\n-\n-\tpinctrl_dhcom_r: dhcom-r-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* CSI2_D1- */\n-\t\t\tMX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12\t\t0x2\n-\t\t>;\n-\t};\n-\n-\tpinctrl_dhcom_s: dhcom-s-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* CSI2_D1+ */\n-\t\t\tMX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10\t\t0x2\n-\t\t>;\n-\t};\n-\n-\tpinctrl_dhcom_int: dhcom-int-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* INT_HIGHEST_PRIO */\n-\t\t\tMX8MP_IOMUXC_SD2_WP__GPIO2_IO20\t\t\t0x2\n-\t\t>;\n-\t};\n-\n-\tpinctrl_hog_base: dhcom-hog-base-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* GPIOs for memory coding */\n-\t\t\tMX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22\t\t0x40000080\n-\t\t\tMX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23\t\t0x40000080\n-\t\t\tMX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24\t\t0x40000080\n-\t\t\t/* GPIOs for hardware coding */\n-\t\t\tMX8MP_IOMUXC_NAND_DQS__GPIO3_IO14\t\t0x40000080\n-\t\t\tMX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19\t\t0x40000080\n-\t\t\tMX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25\t\t0x40000080\n-\t\t>;\n-\t};\n-\n-\tpinctrl_ecspi1: dhcom-ecspi1-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_I2C1_SCL__ECSPI1_SCLK\t\t0x44\n-\t\t\tMX8MP_IOMUXC_I2C1_SDA__ECSPI1_MOSI\t\t0x44\n-\t\t\tMX8MP_IOMUXC_I2C2_SCL__ECSPI1_MISO\t\t0x44\n-\t\t\tMX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17\t\t0x40\n-\t\t>;\n-\t};\n-\n-\tpinctrl_ecspi2: dhcom-ecspi2-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK\t\t0x44\n-\t\t\tMX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI\t\t0x44\n-\t\t\tMX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO\t\t0x44\n-\t\t\tMX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13\t\t0x40\n-\t\t>;\n-\t};\n-\n-\tpinctrl_eqos_rgmii: dhcom-eqos-rgmii-grp {\t/* RGMII */\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC\t\t0x3\n-\t\t\tMX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO\t\t0x3\n-\t\t\tMX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL\t0x1f\n-\t\t\tMX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK\t0x1f\n-\t\t\tMX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0\t0x1f\n-\t\t\tMX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1\t0x1f\n-\t\t\tMX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2\t0x1f\n-\t\t\tMX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3\t0x1f\n-\t\t\tMX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK\t0x91\n-\t\t\tMX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL\t0x91\n-\t\t\tMX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0\t0x91\n-\t\t\tMX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1\t0x91\n-\t\t\tMX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2\t0x91\n-\t\t\tMX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3\t0x91\n-\t\t>;\n-\t};\n-\n-\tpinctrl_eqos_rmii: dhcom-eqos-rmii-grp {\t/* RMII */\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC\t\t0x3\n-\t\t\tMX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO\t\t0x3\n-\t\t\tMX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL\t0x1f\n-\t\t\tMX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0\t0x1f\n-\t\t\tMX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1\t0x1f\n-\t\t\tMX8MP_IOMUXC_ENET_RXC__ENET_QOS_RX_ER\t\t0x1f\n-\t\t\tMX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL\t0x91\n-\t\t\tMX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0\t0x91\n-\t\t\tMX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1\t0x91\n-\t\t\t/* Clock */\n-\t\t\tMX8MP_IOMUXC_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK\t0x4000001f\n-\t\t>;\n-\t};\n-\n-\tpinctrl_ethphy0: dhcom-ethphy0-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* ENET_QOS_#INT Interrupt */\n-\t\t\tMX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19\t\t0x22\n-\t\t>;\n-\t};\n-\n-\tpinctrl_ethphy1: dhcom-ethphy1-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* ENET1_#RST Reset */\n-\t\t\tMX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02\t\t0x11\n-\t\t\t/* ENET1_#INT Interrupt */\n-\t\t\tMX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03\t\t0x11\n-\t\t>;\n-\t};\n-\n-\tpinctrl_fec_rgmii: dhcom-fec-rgmii-grp {\t/* RGMII */\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK\t\t0x1f\n-\t\t\tMX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC\t\t0x3\n-\t\t\tMX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO\t\t0x3\n-\t\t\tMX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0\t\t0x91\n-\t\t\tMX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1\t\t0x91\n-\t\t\tMX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2\t\t0x91\n-\t\t\tMX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3\t\t0x91\n-\t\t\tMX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC\t\t0x91\n-\t\t\tMX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL\t0x91\n-\t\t\tMX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0\t\t0x1f\n-\t\t\tMX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1\t\t0x1f\n-\t\t\tMX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2\t\t0x1f\n-\t\t\tMX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3\t\t0x1f\n-\t\t\tMX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL\t0x1f\n-\t\t\tMX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC\t\t0x1f\n-\t\t\tMX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER\t\t0x1f\n-\t\t>;\n-\t};\n-\n-\tpinctrl_fec_rmii: dhcom-fec-rmii-grp {\t/* RMII */\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC\t\t0x3\n-\t\t\tMX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO\t\t0x3\n-\t\t\tMX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0\t\t0x91\n-\t\t\tMX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1\t\t0x91\n-\t\t\tMX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL\t0x91\n-\t\t\tMX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER\t\t0x91\n-\t\t\tMX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0\t\t0x1f\n-\t\t\tMX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1\t\t0x1f\n-\t\t\tMX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL\t0x1f\n-\t\t\t/* Clock */\n-\t\t\tMX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK\t\t0x4000001f\n-\t\t>;\n-\t};\n-\n-\tpinctrl_flexcan1: dhcom-flexcan1-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_SPDIF_RX__CAN1_RX\t\t\t0x154\n-\t\t\tMX8MP_IOMUXC_SPDIF_TX__CAN1_TX\t\t\t0x154\n-\t\t>;\n-\t};\n-\n-\tpinctrl_flexcan2: dhcom-flexcan2-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_UART3_RXD__CAN2_TX\t\t\t0x154\n-\t\t\tMX8MP_IOMUXC_UART3_TXD__CAN2_RX\t\t\t0x154\n-\t\t>;\n-\t};\n-\n-\tpinctrl_flexspi: dhcom-flexspi-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK\t\t0x1c2\n-\t\t\tMX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B\t0x82\n-\t\t\tMX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00\t0x82\n-\t\t\tMX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01\t0x82\n-\t\t\tMX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02\t0x82\n-\t\t\tMX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03\t0x82\n-\t\t>;\n-\t};\n-\n-\tpinctrl_hdmi: dhcom-hdmi-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC\t\t0x154\n-\t\t\tMX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD\t\t0x154\n-\t\t>;\n-\t};\n-\n-\tpinctrl_i2c3: dhcom-i2c3-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_I2C3_SCL__I2C3_SCL\t\t\t0x40000084\n-\t\t\tMX8MP_IOMUXC_I2C3_SDA__I2C3_SDA\t\t\t0x40000084\n-\t\t>;\n-\t};\n-\n-\tpinctrl_i2c3_gpio: dhcom-i2c3-gpio-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18\t\t0x84\n-\t\t\tMX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19\t\t0x84\n-\t\t>;\n-\t};\n-\n-\tpinctrl_i2c4: dhcom-i2c4-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_I2C4_SCL__I2C4_SCL\t\t\t0x40000084\n-\t\t\tMX8MP_IOMUXC_I2C4_SDA__I2C4_SDA\t\t\t0x40000084\n-\t\t>;\n-\t};\n-\n-\tpinctrl_i2c4_gpio: dhcom-i2c4-gpio-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20\t\t0x84\n-\t\t\tMX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21\t\t0x84\n-\t\t>;\n-\t};\n-\n-\tpinctrl_i2c5: dhcom-i2c5-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL\t\t0x40000084\n-\t\t\tMX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA\t\t0x40000084\n-\t\t>;\n-\t};\n-\n-\tpinctrl_i2c5_gpio: dhcom-i2c5-gpio-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26\t\t0x84\n-\t\t\tMX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27\t\t0x84\n-\t\t>;\n-\t};\n-\n-\tpinctrl_ioexp: dhcom-ioexp-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* #GPIO_EXP_INT */\n-\t\t\tMX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20\t\t0x22\n-\t\t>;\n-\t};\n-\n-\tpinctrl_pmic: dhcom-pmic-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* PMIC_nINT */\n-\t\t\tMX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03\t\t0x40000090\n-\t\t>;\n-\t};\n-\n-\tpinctrl_pwm1: dhcom-pwm1-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT\t\t0x6\n-\t\t>;\n-\t};\n-\n-\tpinctrl_tc9595: dhcom-tc9595-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* RESET_DSIBRIDGE */\n-\t\t\tMX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01\t\t0x40000146\n-\t\t\t/* DSI-CONV_INT Interrupt */\n-\t\t\tMX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21\t\t0x141\n-\t\t>;\n-\t};\n-\n-\tpinctrl_sai3: dhcom-sai3-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC\t0xd6\n-\t\t\tMX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK\t0xd6\n-\t\t\tMX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00\t0xd6\n-\t\t\tMX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00\t0xd6\n-\t\t>;\n-\t};\n-\n-\tpinctrl_touch: dhcom-touch-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* #TOUCH_INT */\n-\t\t\tMX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00\t\t0x40000080\n-\t\t>;\n-\t};\n-\n-\tpinctrl_uart1: dhcom-uart1-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* Console UART */\n-\t\t\tMX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX\t\t0x49\n-\t\t\tMX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX\t\t0x49\n-\t\t\tMX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS\t\t0x49\n-\t\t\tMX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS\t\t0x49\n-\t\t>;\n-\t};\n-\n-\tpinctrl_uart2: dhcom-uart2-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* Bluetooth UART */\n-\t\t\tMX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX\t\t0x49\n-\t\t\tMX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX\t\t0x49\n-\t\t\tMX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS\t\t0x49\n-\t\t\tMX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS\t\t0x49\n-\t\t>;\n-\t};\n-\n-\tpinctrl_uart3: dhcom-uart3-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX\t\t0x49\n-\t\t\tMX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX\t\t0x49\n-\t\t\tMX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS\t\t0x49\n-\t\t\tMX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS\t\t0x49\n-\t\t>;\n-\t};\n-\n-\tpinctrl_uart4: dhcom-uart4-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX\t\t0x49\n-\t\t\tMX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX\t\t0x49\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usb1_vbus: dhcom-usb1-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR\t\t0x6\n-\t\t\tMX8MP_IOMUXC_GPIO1_IO15__USB2_OTG_OC\t\t0x80\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc1: dhcom-usdhc1-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_SD1_CLK__USDHC1_CLK\t\t0x190\n-\t\t\tMX8MP_IOMUXC_SD1_CMD__USDHC1_CMD\t\t0x1d0\n-\t\t\tMX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0\t\t0x1d0\n-\t\t\tMX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1\t\t0x1d0\n-\t\t\tMX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2\t\t0x1d0\n-\t\t\tMX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3\t\t0x1d0\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc1_100mhz: dhcom-usdhc1-100mhz-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_SD1_CLK__USDHC1_CLK\t\t0x194\n-\t\t\tMX8MP_IOMUXC_SD1_CMD__USDHC1_CMD\t\t0x1d4\n-\t\t\tMX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0\t\t0x1d4\n-\t\t\tMX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1\t\t0x1d4\n-\t\t\tMX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2\t\t0x1d4\n-\t\t\tMX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3\t\t0x1d4\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc1_200mhz: dhcom-usdhc1-200mhz-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_SD1_CLK__USDHC1_CLK\t\t0x196\n-\t\t\tMX8MP_IOMUXC_SD1_CMD__USDHC1_CMD\t\t0x1d6\n-\t\t\tMX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0\t\t0x1d6\n-\t\t\tMX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1\t\t0x1d6\n-\t\t\tMX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2\t\t0x1d6\n-\t\t\tMX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3\t\t0x1d6\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc2: dhcom-usdhc2-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_SD2_CLK__USDHC2_CLK\t\t0x190\n-\t\t\tMX8MP_IOMUXC_SD2_CMD__USDHC2_CMD\t\t0x1d0\n-\t\t\tMX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0\t\t0x1d0\n-\t\t\tMX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1\t\t0x1d0\n-\t\t\tMX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2\t\t0x1d0\n-\t\t\tMX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3\t\t0x1d0\n-\t\t\tMX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT\t\t0xc1\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc2_100mhz: dhcom-usdhc2-100mhz-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_SD2_CLK__USDHC2_CLK\t\t0x194\n-\t\t\tMX8MP_IOMUXC_SD2_CMD__USDHC2_CMD\t\t0x1d4\n-\t\t\tMX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0\t\t0x1d4\n-\t\t\tMX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1\t\t0x1d4\n-\t\t\tMX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2\t\t0x1d4\n-\t\t\tMX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3\t\t0x1d4\n-\t\t\tMX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT\t\t0xc1\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc2_200mhz: dhcom-usdhc2-200mhz-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_SD2_CLK__USDHC2_CLK\t\t0x196\n-\t\t\tMX8MP_IOMUXC_SD2_CMD__USDHC2_CMD\t\t0x1d6\n-\t\t\tMX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0\t\t0x1d6\n-\t\t\tMX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1\t\t0x1d6\n-\t\t\tMX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2\t\t0x1d6\n-\t\t\tMX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3\t\t0x1d6\n-\t\t\tMX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT\t\t0xc1\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc2_vmmc: dhcom-usdhc2-vmmc-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19\t\t0x20\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc2_gpio: dhcom-usdhc2-gpio-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12\t\t0x40000080\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc3: dhcom-usdhc3-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK\t\t0x190\n-\t\t\tMX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD\t\t0x1d0\n-\t\t\tMX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0\t\t0x1d0\n-\t\t\tMX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1\t\t0x1d0\n-\t\t\tMX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2\t\t0x1d0\n-\t\t\tMX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3\t\t0x1d0\n-\t\t\tMX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4\t\t0x1d0\n-\t\t\tMX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5\t\t0x1d0\n-\t\t\tMX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6\t\t0x1d0\n-\t\t\tMX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7\t\t0x1d0\n-\t\t\tMX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE\t\t0x190\n-\t\t\tMX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B\t0x141\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc3_100mhz: dhcom-usdhc3-100mhz-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK\t\t0x194\n-\t\t\tMX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD\t\t0x1d4\n-\t\t\tMX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0\t\t0x1d4\n-\t\t\tMX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1\t\t0x1d4\n-\t\t\tMX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2\t\t0x1d4\n-\t\t\tMX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3\t\t0x1d4\n-\t\t\tMX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4\t\t0x1d4\n-\t\t\tMX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5\t\t0x1d4\n-\t\t\tMX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6\t\t0x1d4\n-\t\t\tMX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7\t\t0x1d4\n-\t\t\tMX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE\t\t0x194\n-\t\t\tMX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B\t0x141\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc3_200mhz: dhcom-usdhc3-200mhz-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK\t\t0x196\n-\t\t\tMX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD\t\t0x1d6\n-\t\t\tMX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0\t\t0x1d6\n-\t\t\tMX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1\t\t0x1d6\n-\t\t\tMX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2\t\t0x1d6\n-\t\t\tMX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3\t\t0x1d6\n-\t\t\tMX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4\t\t0x1d6\n-\t\t\tMX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5\t\t0x1d6\n-\t\t\tMX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6\t\t0x1d6\n-\t\t\tMX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7\t\t0x1d6\n-\t\t\tMX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE\t\t0x196\n-\t\t\tMX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B\t0x141\n-\t\t>;\n-\t};\n-\n-\tpinctrl_wdog: dhcom-wdog-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B\t\t0xc6\n-\t\t>;\n-\t};\n-};\ndiff --git a/configs/imx8mp_dhcom_drc02_defconfig b/configs/imx8mp_dhcom_drc02_defconfig\nindex c43839cecf5..82de0eb391a 100644\n--- a/configs/imx8mp_dhcom_drc02_defconfig\n+++ b/configs/imx8mp_dhcom_drc02_defconfig\n@@ -2,6 +2,7 @@\n \n CONFIG_ARM=y\n CONFIG_ARCH_IMX8M=y\n-CONFIG_DEFAULT_DEVICE_TREE=\"imx8mp-dhcom-drc02\"\n+CONFIG_DEFAULT_DEVICE_TREE=\"freescale/imx8mp-dhcom-drc02\"\n CONFIG_DEFAULT_FDT_FILE=\"imx8mp-dhcom-drc02.dtb\"\n+CONFIG_OF_UPSTREAM=y\n CONFIG_PREBOOT=\"\"\ndiff --git a/configs/imx8mp_dhcom_picoitx_defconfig b/configs/imx8mp_dhcom_picoitx_defconfig\nindex 99cd5f279dc..2442e260f9f 100644\n--- a/configs/imx8mp_dhcom_picoitx_defconfig\n+++ b/configs/imx8mp_dhcom_picoitx_defconfig\n@@ -2,6 +2,7 @@\n \n CONFIG_ARM=y\n CONFIG_ARCH_IMX8M=y\n-CONFIG_DEFAULT_DEVICE_TREE=\"imx8mp-dhcom-picoitx\"\n+CONFIG_DEFAULT_DEVICE_TREE=\"freescale/imx8mp-dhcom-picoitx\"\n CONFIG_DEFAULT_FDT_FILE=\"imx8mp-dhcom-picoitx.dtb\"\n+CONFIG_OF_UPSTREAM=y\n CONFIG_PREBOOT=\"\"\n","prefixes":["11/13"]}