{"id":2228198,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2228198/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20260425-imx8m-of-upstream-v1-10-07527be92e5d@nxp.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.1/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260425-imx8m-of-upstream-v1-10-07527be92e5d@nxp.com>","date":"2026-04-25T00:37:02","name":"[10/13] imx8mm: icore-mx8mm: Switch to OF_UPSTREAM","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"7e66a2967b9a83b7e72d5d89f5d19e2f9cae3cde","submitter":{"id":80723,"url":"http://patchwork.ozlabs.org/api/1.1/people/80723/?format=json","name":"Peng Fan (OSS)","email":"peng.fan@oss.nxp.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20260425-imx8m-of-upstream-v1-10-07527be92e5d@nxp.com/mbox/","series":[{"id":501451,"url":"http://patchwork.ozlabs.org/api/1.1/series/501451/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=501451","date":"2026-04-25T00:37:04","name":"iMX8M: Covert to OF_UPSTREAM","version":1,"mbox":"http://patchwork.ozlabs.org/series/501451/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2228198/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2228198/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com\n header.a=rsa-sha256 header.s=selector1-NXP1-onmicrosoft-com\n header.b=VH3NQFEf;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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phobos.denx.de","X-Virus-Status":"Clean"},"content":"From: Peng Fan \n\narch/arm/dts[imx8mm-icore-mx8mm-ctouch2.dts,imx8mm-icore-mx8mm-edimm2.2.dts]\nare same as the one in dts/upstream, so drop the copy and switch to\nOF_UPSTREAM by updating config and selecting OF_UPSTREAM.\n\nSigned-off-by: Peng Fan \n---\n arch/arm/dts/Makefile | 2 -\n arch/arm/dts/imx8mm-icore-mx8mm-ctouch2.dts | 96 -----------\n arch/arm/dts/imx8mm-icore-mx8mm-edimm2.2.dts | 96 -----------\n arch/arm/dts/imx8mm-icore-mx8mm.dtsi | 232 --------------------------\n arch/arm/mach-imx/imx8m/Kconfig | 1 +\n configs/imx8mm-icore-mx8mm-ctouch2_defconfig | 2 +-\n configs/imx8mm-icore-mx8mm-edimm2.2_defconfig | 2 +-\n 7 files changed, 3 insertions(+), 428 deletions(-)","diff":"diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile\nindex 8656100fea2..aa9437ecb43 100644\n--- a/arch/arm/dts/Makefile\n+++ b/arch/arm/dts/Makefile\n@@ -873,8 +873,6 @@ dtb-$(CONFIG_ARCH_IMX8) += \\\n \timx8-capricorn-cxg3.dtb \\\n \n dtb-$(CONFIG_ARCH_IMX8M) += \\\n-\timx8mm-icore-mx8mm-ctouch2.dtb \\\n-\timx8mm-icore-mx8mm-edimm2.2.dtb \\\n \timx8mm-phg.dtb \\\n \timx8mq-cm.dtb \\\n \timx8mp-data-modul-edm-sbc.dtb \\\ndiff --git a/arch/arm/dts/imx8mm-icore-mx8mm-ctouch2.dts b/arch/arm/dts/imx8mm-icore-mx8mm-ctouch2.dts\ndeleted file mode 100644\nindex 50274540284..00000000000\n--- a/arch/arm/dts/imx8mm-icore-mx8mm-ctouch2.dts\n+++ /dev/null\n@@ -1,96 +0,0 @@\n-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n-/*\n- * Copyright (c) 2019 NXP\n- * Copyright (c) 2019 Engicam srl\n- * Copyright (c) 2020 Amarula Solutions(India)\n- */\n-\n-/dts-v1/;\n-#include \"imx8mm.dtsi\"\n-#include \"imx8mm-icore-mx8mm.dtsi\"\n-\n-/ {\n-\tmodel = \"Engicam i.Core MX8M Mini C.TOUCH 2.0\";\n-\tcompatible = \"engicam,icore-mx8mm-ctouch2\", \"engicam,icore-mx8mm\",\n-\t\t \"fsl,imx8mm\";\n-\n-\tchosen {\n-\t\tstdout-path = &uart2;\n-\t};\n-};\n-\n-&fec1 {\n-\tstatus = \"okay\";\n-};\n-\n-&i2c2 {\n-\tclock-frequency = <400000>;\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_i2c2>;\n-\tstatus = \"okay\";\n-};\n-\n-&i2c4 {\n-\tclock-frequency = <100000>;\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_i2c4>;\n-\tstatus = \"okay\";\n-};\n-\n-&iomuxc {\n-\tpinctrl_i2c2: i2c2grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MM_IOMUXC_I2C2_SCL_I2C2_SCL\t\t0x400001c3\n-\t\t\tMX8MM_IOMUXC_I2C2_SDA_I2C2_SDA\t\t0x400001c3\n-\t\t>;\n-\t};\n-\n-\tpinctrl_i2c4: i2c4grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MM_IOMUXC_I2C4_SCL_I2C4_SCL\t\t0x400001c3\n-\t\t\tMX8MM_IOMUXC_I2C4_SDA_I2C4_SDA\t\t0x400001c3\n-\t\t>;\n-\t};\n-\n-\tpinctrl_uart2: uart2grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX\t0x140\n-\t\t\tMX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX\t0x140\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc1_gpio: usdhc1gpiogrp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6\t0x41\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc1: usdhc1grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MM_IOMUXC_SD1_CLK_USDHC1_CLK\t\t0x190\n-\t\t\tMX8MM_IOMUXC_SD1_CMD_USDHC1_CMD\t\t0x1d0\n-\t\t\tMX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0\t0x1d0\n-\t\t\tMX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1\t0x1d0\n-\t\t\tMX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2\t0x1d0\n-\t\t\tMX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3\t0x1d0\n-\t\t>;\n-\t};\n-};\n-\n-&uart2 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_uart2>;\n-\tstatus = \"okay\";\n-};\n-\n-/* SD */\n-&usdhc1 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;\n-\tcd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;\n-\tmax-frequency = <50000000>;\n-\tbus-width = <4>;\n-\tno-1-8-v;\n-\tkeep-power-in-suspend;\n-\tstatus = \"okay\";\n-};\ndiff --git a/arch/arm/dts/imx8mm-icore-mx8mm-edimm2.2.dts b/arch/arm/dts/imx8mm-icore-mx8mm-edimm2.2.dts\ndeleted file mode 100644\nindex ddac8bc7ae6..00000000000\n--- a/arch/arm/dts/imx8mm-icore-mx8mm-edimm2.2.dts\n+++ /dev/null\n@@ -1,96 +0,0 @@\n-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n-/*\n- * Copyright (c) 2019 NXP\n- * Copyright (c) 2019 Engicam srl\n- * Copyright (c) 2020 Amarula Solutions(India)\n- */\n-\n-/dts-v1/;\n-#include \"imx8mm.dtsi\"\n-#include \"imx8mm-icore-mx8mm.dtsi\"\n-\n-/ {\n-\tmodel = \"Engicam i.Core MX8M Mini EDIMM2.2 Starter Kit\";\n-\tcompatible = \"engicam,icore-mx8mm-edimm2.2\", \"engicam,icore-mx8mm\",\n-\t\t \"fsl,imx8mm\";\n-\n-\tchosen {\n-\t\tstdout-path = &uart2;\n-\t};\n-};\n-\n-&fec1 {\n-\tstatus = \"okay\";\n-};\n-\n-&i2c2 {\n-\tclock-frequency = <400000>;\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_i2c2>;\n-\tstatus = \"okay\";\n-};\n-\n-&i2c4 {\n-\tclock-frequency = <100000>;\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_i2c4>;\n-\tstatus = \"okay\";\n-};\n-\n-&iomuxc {\n-\tpinctrl_i2c2: i2c2grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MM_IOMUXC_I2C2_SCL_I2C2_SCL\t\t0x400001c3\n-\t\t\tMX8MM_IOMUXC_I2C2_SDA_I2C2_SDA\t\t0x400001c3\n-\t\t>;\n-\t};\n-\n-\tpinctrl_i2c4: i2c4grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MM_IOMUXC_I2C4_SCL_I2C4_SCL\t\t0x400001c3\n-\t\t\tMX8MM_IOMUXC_I2C4_SDA_I2C4_SDA\t\t0x400001c3\n-\t\t>;\n-\t};\n-\n-\tpinctrl_uart2: uart2grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX\t0x140\n-\t\t\tMX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX\t0x140\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc1_gpio: usdhc1gpiogrp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6\t0x41\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc1: usdhc1grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MM_IOMUXC_SD1_CLK_USDHC1_CLK\t\t0x190\n-\t\t\tMX8MM_IOMUXC_SD1_CMD_USDHC1_CMD\t\t0x1d0\n-\t\t\tMX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0\t0x1d0\n-\t\t\tMX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1\t0x1d0\n-\t\t\tMX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2\t0x1d0\n-\t\t\tMX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3\t0x1d0\n-\t\t>;\n-\t};\n-};\n-\n-&uart2 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_uart2>;\n-\tstatus = \"okay\";\n-};\n-\n-/* SD */\n-&usdhc1 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;\n-\tcd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;\n-\tmax-frequency = <50000000>;\n-\tbus-width = <4>;\n-\tno-1-8-v;\n-\tkeep-power-in-suspend;\n-\tstatus = \"okay\";\n-};\ndiff --git a/arch/arm/dts/imx8mm-icore-mx8mm.dtsi b/arch/arm/dts/imx8mm-icore-mx8mm.dtsi\ndeleted file mode 100644\nindex def7bb5d37c..00000000000\n--- a/arch/arm/dts/imx8mm-icore-mx8mm.dtsi\n+++ /dev/null\n@@ -1,232 +0,0 @@\n-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n-/*\n- * Copyright (c) 2018 NXP\n- * Copyright (c) 2019 Engicam srl\n- * Copyright (c) 2020 Amarula Solutions(India)\n- */\n-\n-/ {\n-\tcompatible = \"engicam,icore-mx8mm\", \"fsl,imx8mm\";\n-};\n-\n-&A53_0 {\n-\tcpu-supply = <®_buck4>;\n-};\n-\n-&A53_1 {\n-\tcpu-supply = <®_buck4>;\n-};\n-\n-&A53_2 {\n-\tcpu-supply = <®_buck4>;\n-};\n-\n-&A53_3 {\n-\tcpu-supply = <®_buck4>;\n-};\n-\n-&fec1 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_fec1>;\n-\tphy-mode = \"rgmii-id\";\n-\tphy-handle = <ðphy>;\n-\n-\tmdio {\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\n-\t\tethphy: ethernet-phy@3 {\n-\t\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n-\t\t\treg = <3>;\n-\t\t\treset-gpios = <&gpio3 7 GPIO_ACTIVE_LOW>;\n-\t\t\treset-assert-us = <10000>;\n-\t\t};\n-\t};\n-};\n-\n-&i2c1 {\n-\tclock-frequency = <400000>;\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_i2c1>;\n-\tstatus = \"okay\";\n-\n-\tpmic@8 {\n-\t\tcompatible = \"nxp,pf8121a\";\n-\t\treg = <0x08>;\n-\n-\t\tregulators {\n-\t\t\treg_ldo1: ldo1 {\n-\t\t\t\tregulator-min-microvolt = <1500000>;\n-\t\t\t\tregulator-max-microvolt = <5000000>;\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t};\n-\n-\t\t\treg_ldo2: ldo2 {\n-\t\t\t\tregulator-min-microvolt = <1500000>;\n-\t\t\t\tregulator-max-microvolt = <5000000>;\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t};\n-\n-\t\t\treg_ldo3: ldo3 {\n-\t\t\t\tregulator-min-microvolt = <1500000>;\n-\t\t\t\tregulator-max-microvolt = <5000000>;\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t};\n-\n-\t\t\treg_ldo4: ldo4 {\n-\t\t\t\tregulator-min-microvolt = <1500000>;\n-\t\t\t\tregulator-max-microvolt = <5000000>;\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t};\n-\n-\t\t\treg_buck1: buck1 {\n-\t\t\t\tregulator-min-microvolt = <400000>;\n-\t\t\t\tregulator-max-microvolt = <1800000>;\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t};\n-\n-\t\t\treg_buck2: buck2 {\n-\t\t\t\tregulator-min-microvolt = <400000>;\n-\t\t\t\tregulator-max-microvolt = <1800000>;\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t};\n-\n-\t\t\treg_buck3: buck3 {\n-\t\t\t\tregulator-min-microvolt = <400000>;\n-\t\t\t\tregulator-max-microvolt = <1800000>;\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t};\n-\n-\t\t\treg_buck4: buck4 {\n-\t\t\t\tregulator-min-microvolt = <400000>;\n-\t\t\t\tregulator-max-microvolt = <1800000>;\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t};\n-\n-\t\t\treg_buck5: buck5 {\n-\t\t\t\tregulator-min-microvolt = <400000>;\n-\t\t\t\tregulator-max-microvolt = <1800000>;\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t};\n-\n-\t\t\treg_buck6: buck6 {\n-\t\t\t\tregulator-min-microvolt = <400000>;\n-\t\t\t\tregulator-max-microvolt = <1800000>;\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t};\n-\n-\t\t\treg_buck7: buck7 {\n-\t\t\t\tregulator-min-microvolt = <3300000>;\n-\t\t\t\tregulator-max-microvolt = <3300000>;\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t};\n-\n-\t\t\treg_vsnvs: vsnvs {\n-\t\t\t\tregulator-min-microvolt = <1800000>;\n-\t\t\t\tregulator-max-microvolt = <3300000>;\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t};\n-\t\t};\n-\t};\n-};\n-\n-&iomuxc {\n-\tpinctrl_fec1: fec1grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MM_IOMUXC_ENET_MDC_ENET1_MDC\t\t\t0x3\n-\t\t\tMX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO\t\t0x3\n-\t\t\tMX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3\t\t0x1f\n-\t\t\tMX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2\t\t0x1f\n-\t\t\tMX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1\t\t0x1f\n-\t\t\tMX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0\t\t0x1f\n-\t\t\tMX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3\t\t0x91\n-\t\t\tMX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2\t\t0x91\n-\t\t\tMX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1\t\t0x91\n-\t\t\tMX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0\t\t0x91\n-\t\t\tMX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC\t\t0x1f\n-\t\t\tMX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC\t\t0x91\n-\t\t\tMX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL\t0x91\n-\t\t\tMX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL\t0x1f\n-\t\t\tMX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7\t\t0x19\n-\t\t>;\n-\t};\n-\n-\tpinctrl_i2c1: i2c1grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MM_IOMUXC_I2C1_SCL_I2C1_SCL\t\t0x400001c3\n-\t\t\tMX8MM_IOMUXC_I2C1_SDA_I2C1_SDA\t\t0x400001c3\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc3: usdhc3grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190\n-\t\t\tMX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0\n-\t\t\tMX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0\n-\t\t\tMX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0\n-\t\t\tMX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0\n-\t\t\tMX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0\n-\t\t\tMX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0\n-\t\t\tMX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0\n-\t\t\tMX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0\n-\t\t\tMX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0\n-\t\t\tMX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0\n-\t\t\tMX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194\n-\t\t\tMX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4\n-\t\t\tMX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4\n-\t\t\tMX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4\n-\t\t\tMX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4\n-\t\t\tMX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4\n-\t\t\tMX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4\n-\t\t\tMX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4\n-\t\t\tMX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4\n-\t\t\tMX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4\n-\t\t\tMX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196\n-\t\t\tMX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6\n-\t\t\tMX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6\n-\t\t\tMX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6\n-\t\t\tMX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6\n-\t\t\tMX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6\n-\t\t\tMX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6\n-\t\t\tMX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6\n-\t\t\tMX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6\n-\t\t\tMX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6\n-\t\t\tMX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196\n-\t\t>;\n-\t};\n-};\n-\n-/* eMMC */\n-&usdhc3 {\n-\tpinctrl-names = \"default\", \"state_100mhz\", \"state_200mhz\";\n-\tpinctrl-0 = <&pinctrl_usdhc3>;\n-\tpinctrl-1 = <&pinctrl_usdhc3_100mhz>;\n-\tpinctrl-2 = <&pinctrl_usdhc3_200mhz>;\n-\tbus-width = <8>;\n-\tnon-removable;\n-\tstatus = \"okay\";\n-};\ndiff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig\nindex db138a8da34..00b5963b30e 100644\n--- a/arch/arm/mach-imx/imx8m/Kconfig\n+++ b/arch/arm/mach-imx/imx8m/Kconfig\n@@ -115,6 +115,7 @@ config TARGET_IMX8MM_ICORE_MX8MM\n \tselect IMX8MM\n \tselect SUPPORT_SPL\n \tselect IMX8M_LPDDR4\n+\timply OF_UPSTREAM\n \thelp\n \t i.Core MX8M Mini is an EDIMM SOM based on NXP i.MX8MM.\n \ndiff --git a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig\nindex 544fcbf5d68..537eb496a3e 100644\n--- a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig\n+++ b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig\n@@ -8,7 +8,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y\n CONFIG_ENV_SIZE=0x1000\n CONFIG_ENV_OFFSET=0x400000\n CONFIG_DM_GPIO=y\n-CONFIG_DEFAULT_DEVICE_TREE=\"imx8mm-icore-mx8mm-ctouch2\"\n+CONFIG_DEFAULT_DEVICE_TREE=\"freescale/imx8mm-icore-mx8mm-ctouch2\"\n CONFIG_TARGET_IMX8MM_ICORE_MX8MM=y\n CONFIG_SYS_MONITOR_LEN=524288\n CONFIG_SPL_MMC=y\ndiff --git a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig\nindex c27bdaa15d1..db90657c2bd 100644\n--- a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig\n+++ b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig\n@@ -8,7 +8,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y\n CONFIG_ENV_SIZE=0x1000\n CONFIG_ENV_OFFSET=0x400000\n CONFIG_DM_GPIO=y\n-CONFIG_DEFAULT_DEVICE_TREE=\"imx8mm-icore-mx8mm-edimm2.2\"\n+CONFIG_DEFAULT_DEVICE_TREE=\"freescale/imx8mm-icore-mx8mm-edimm2.2\"\n CONFIG_TARGET_IMX8MM_ICORE_MX8MM=y\n CONFIG_SYS_MONITOR_LEN=524288\n CONFIG_SPL_MMC=y\n","prefixes":["10/13"]}