{"id":2228190,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2228190/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20260425-imx8m-of-upstream-v1-6-07527be92e5d@nxp.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.1/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260425-imx8m-of-upstream-v1-6-07527be92e5d@nxp.com>","date":"2026-04-25T00:36:58","name":"[06/13] imx8mq: Drop arch/arm/dts/imx8mq.dtsi","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"9b3f48fd9d0faffbb400b3b168d862fff26f084b","submitter":{"id":80723,"url":"http://patchwork.ozlabs.org/api/1.1/people/80723/?format=json","name":"Peng Fan (OSS)","email":"peng.fan@oss.nxp.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20260425-imx8m-of-upstream-v1-6-07527be92e5d@nxp.com/mbox/","series":[{"id":501451,"url":"http://patchwork.ozlabs.org/api/1.1/series/501451/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=501451","date":"2026-04-25T00:37:04","name":"iMX8M: Covert to OF_UPSTREAM","version":1,"mbox":"http://patchwork.ozlabs.org/series/501451/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2228190/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2228190/checks/","tags":{},"headers":{"Return-Path":"<u-boot-bounces@lists.denx.de>","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com\n header.a=rsa-sha256 header.s=selector1-NXP1-onmicrosoft-com\n header.b=wP2848G2;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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Hartmann\" <lukas@mntre.com>,\n Patrick Wildt <patrick@blueri.se>, Ye Li <ye.li@nxp.com>,\n Frieder Schrempf <frieder.schrempf@kontron.de>,\n Benjamin Hahn <B.Hahn@phytec.de>, Alice Guo <alice.guo@nxp.com>,\n Marek Vasut <marek.vasut+renesas@mailbox.org>,\n Marco Franchi <marcofrk@gmail.com>, Alifer Moraes <alifer.wsdm@gmail.com>,\n Angus Ainslie <angus@akkea.ca>, Heiko Thiery <heiko.thiery@gmail.com>,\n Olaf Mandel <o.mandel@menlosystems.com>,\n Jagan Teki <jagan@amarulasolutions.com>,\n Matteo Lisi <matteo.lisi@engicam.com>,\n Manoj Sai <abbaraju.manojsai@amarulasolutions.com>,\n Emanuele Ghidoli <emanuele.ghidoli@toradex.com>,\n Parth Pancholi <parth.pancholi@toradex.com>, Peng Fan <peng.fan@nxp.com>","X-Mailer":"b4 0.14.3","X-ClientProxiedBy":"SI2PR01CA0020.apcprd01.prod.exchangelabs.com\n (2603:1096:4:192::6) To PAXPR04MB8459.eurprd04.prod.outlook.com\n (2603:10a6:102:1da::15)","MIME-Version":"1.0","X-MS-Exchange-MessageSentRepresentingType":"1","X-MS-PublicTrafficType":"Email","X-MS-TrafficTypeDiagnostic":"\n PAXPR04MB8459:EE_|AM8PR04MB7876:EE_|DUZPR04MB9728:EE_|DU4PR04MB10435:EE_","X-MS-Office365-Filtering-Correlation-Id":"d849b790-0990-4890-3a12-08dea25824bd","X-MS-Exchange-SharedMailbox-RoutingAgent-Processed":"True","X-LD-Processed":"686ea1d3-bc2b-4c6f-a92c-d99c5c301635,ExtAddr","X-MS-Exchange-SenderADCheck":"1","X-MS-Exchange-AntiSpam-Relay":"0","X-Microsoft-Antispam":"BCL:0;\n ARA:13230040|7416014|376014|52116014|1800799024|19092799006|366016|56012099003|18002099003|22082099003|38350700014;","X-Microsoft-Antispam-Message-Info":"\n pzgAPyKxQpeUhtDMwYjbvd0f417kBs+/FN5CP3rCJirG7gM/PWeTidSVlWBfuon17MfFN6wwB3a3Q7DougAK3Kssgxgml+sgEWsWxIhD8FTBdcg55hFd9lK7GTvlD649qBz0oQoSD2HfY/XGINq+c68wTGXUElBnf2IummgOGhouDN8oMzQA+nmvJfpG2T/ZVuvn9Lxb11rFvHY0oLpGd9eJY49NfxZKumUALkfadYc7/3kcSoBY3iS36Y/+gBl2kfQWTMZQEkUDQsXeOBdA9tUlXs906sA9fLtAsY6yVE/pqf5P7xfyYRDaBJ5d0+kIObAfk1YNRcxhUvcuIL/YopkXra29JIdieTKuXne0Os7gshKdZLG6GyU1np3qWlNPLfENn+vvLu3F7u2wL17uqirpD1KdRwxLtRG8BC0AmimOvVUPioyQaov+Q9Awnh1xne1onA4lRQf7JNEs++ClnRUUrdsuRrXQKQeFwifsOxBYVoF2WB0ikBoD0elZYfG3wQ6U/DNwwzF2YoStrBbH1LjUULscZtGfcV8NaKBXXhsJUtrmvWQc7E7smrPUZ+R/7nxrocS150iuCDqkE6z7IKHTz+G8WCksXyurpRWYA+ny+Mmv23q1zEQFnrHjRTn7o6/lWgiTh6txhxfoJ8+u3AAGm7tori2KYmFvgrSWJhknz4SglWB7bB051Vh733udnrs57duJ4Lhfuf+fzeRTBIxtTK0IfKRqdlv0mE3ZKc2CCOdw5T6gk1ZncWycLOk4HgYpWCZxD9WQGdVoUC7L7OTjrADb/A4zdhHTaOAgI0M=","X-Forefront-Antispam-Report":"CIP:255.255.255.255; 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No need to keep a copy in arch/arm/dts/, and there\nis very minimal changes compared with the one in dts/upstream, so remove\nthe copy.\n\nSigned-off-by: Peng Fan <peng.fan@nxp.com>\n---\n arch/arm/dts/imx8mq.dtsi | 1615 ----------------------------------------------\n 1 file changed, 1615 deletions(-)","diff":"diff --git a/arch/arm/dts/imx8mq.dtsi b/arch/arm/dts/imx8mq.dtsi\ndeleted file mode 100644\nindex 19eaa523564..00000000000\n--- a/arch/arm/dts/imx8mq.dtsi\n+++ /dev/null\n@@ -1,1615 +0,0 @@\n-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n-/*\n- * Copyright 2017 NXP\n- * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>\n- */\n-\n-#include <dt-bindings/clock/imx8mq-clock.h>\n-#include <dt-bindings/power/imx8mq-power.h>\n-#include <dt-bindings/reset/imx8mq-reset.h>\n-#include <dt-bindings/gpio/gpio.h>\n-#include \"dt-bindings/input/input.h\"\n-#include <dt-bindings/interrupt-controller/arm-gic.h>\n-#include <dt-bindings/thermal/thermal.h>\n-#include <dt-bindings/interconnect/imx8mq.h>\n-#include \"imx8mq-pinfunc.h\"\n-\n-/ {\n-\tinterrupt-parent = <&gpc>;\n-\n-\t#address-cells = <2>;\n-\t#size-cells = <2>;\n-\n-\taliases {\n-\t\tethernet0 = &fec1;\n-\t\tgpio0 = &gpio1;\n-\t\tgpio1 = &gpio2;\n-\t\tgpio2 = &gpio3;\n-\t\tgpio3 = &gpio4;\n-\t\tgpio4 = &gpio5;\n-\t\ti2c0 = &i2c1;\n-\t\ti2c1 = &i2c2;\n-\t\ti2c2 = &i2c3;\n-\t\ti2c3 = &i2c4;\n-\t\tmmc0 = &usdhc1;\n-\t\tmmc1 = &usdhc2;\n-\t\tserial0 = &uart1;\n-\t\tserial1 = &uart2;\n-\t\tserial2 = &uart3;\n-\t\tserial3 = &uart4;\n-\t\tspi0 = &ecspi1;\n-\t\tspi1 = &ecspi2;\n-\t\tspi2 = &ecspi3;\n-\t};\n-\n-\tckil: clock-ckil {\n-\t\tcompatible = \"fixed-clock\";\n-\t\t#clock-cells = <0>;\n-\t\tclock-frequency = <32768>;\n-\t\tclock-output-names = \"ckil\";\n-\t};\n-\n-\tosc_25m: clock-osc-25m {\n-\t\tcompatible = \"fixed-clock\";\n-\t\t#clock-cells = <0>;\n-\t\tclock-frequency = <25000000>;\n-\t\tclock-output-names = \"osc_25m\";\n-\t};\n-\n-\tosc_27m: clock-osc-27m {\n-\t\tcompatible = \"fixed-clock\";\n-\t\t#clock-cells = <0>;\n-\t\tclock-frequency = <27000000>;\n-\t\tclock-output-names = \"osc_27m\";\n-\t};\n-\n-\thdmi_phy_27m: clock-hdmi-phy-27m {\n-\t\tcompatible = \"fixed-clock\";\n-\t\t#clock-cells = <0>;\n-\t\tclock-frequency = <27000000>;\n-\t\tclock-output-names = \"hdmi_phy_27m\";\n-\t};\n-\n-\tclk_ext1: clock-ext1 {\n-\t\tcompatible = \"fixed-clock\";\n-\t\t#clock-cells = <0>;\n-\t\tclock-frequency = <133000000>;\n-\t\tclock-output-names = \"clk_ext1\";\n-\t};\n-\n-\tclk_ext2: clock-ext2 {\n-\t\tcompatible = \"fixed-clock\";\n-\t\t#clock-cells = <0>;\n-\t\tclock-frequency = <133000000>;\n-\t\tclock-output-names = \"clk_ext2\";\n-\t};\n-\n-\tclk_ext3: clock-ext3 {\n-\t\tcompatible = \"fixed-clock\";\n-\t\t#clock-cells = <0>;\n-\t\tclock-frequency = <133000000>;\n-\t\tclock-output-names = \"clk_ext3\";\n-\t};\n-\n-\tclk_ext4: clock-ext4 {\n-\t\tcompatible = \"fixed-clock\";\n-\t\t#clock-cells = <0>;\n-\t\tclock-frequency = <133000000>;\n-\t\tclock-output-names = \"clk_ext4\";\n-\t};\n-\n-\tcpus {\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\n-\t\tA53_0: cpu@0 {\n-\t\t\tdevice_type = \"cpu\";\n-\t\t\tcompatible = \"arm,cortex-a53\";\n-\t\t\treg = <0x0>;\n-\t\t\tclock-latency = <61036>; /* two CLK32 periods */\n-\t\t\tclocks = <&clk IMX8MQ_CLK_ARM>;\n-\t\t\tenable-method = \"psci\";\n-\t\t\ti-cache-size = <0x8000>;\n-\t\t\ti-cache-line-size = <64>;\n-\t\t\ti-cache-sets = <256>;\n-\t\t\td-cache-size = <0x8000>;\n-\t\t\td-cache-line-size = <64>;\n-\t\t\td-cache-sets = <128>;\n-\t\t\tnext-level-cache = <&A53_L2>;\n-\t\t\toperating-points-v2 = <&a53_opp_table>;\n-\t\t\t#cooling-cells = <2>;\n-\t\t\tnvmem-cells = <&cpu_speed_grade>;\n-\t\t\tnvmem-cell-names = \"speed_grade\";\n-\t\t};\n-\n-\t\tA53_1: cpu@1 {\n-\t\t\tdevice_type = \"cpu\";\n-\t\t\tcompatible = \"arm,cortex-a53\";\n-\t\t\treg = <0x1>;\n-\t\t\tclock-latency = <61036>; /* two CLK32 periods */\n-\t\t\tclocks = <&clk IMX8MQ_CLK_ARM>;\n-\t\t\tenable-method = \"psci\";\n-\t\t\ti-cache-size = <0x8000>;\n-\t\t\ti-cache-line-size = <64>;\n-\t\t\ti-cache-sets = <256>;\n-\t\t\td-cache-size = <0x8000>;\n-\t\t\td-cache-line-size = <64>;\n-\t\t\td-cache-sets = <128>;\n-\t\t\tnext-level-cache = <&A53_L2>;\n-\t\t\toperating-points-v2 = <&a53_opp_table>;\n-\t\t\t#cooling-cells = <2>;\n-\t\t};\n-\n-\t\tA53_2: cpu@2 {\n-\t\t\tdevice_type = \"cpu\";\n-\t\t\tcompatible = \"arm,cortex-a53\";\n-\t\t\treg = <0x2>;\n-\t\t\tclock-latency = <61036>; /* two CLK32 periods */\n-\t\t\tclocks = <&clk IMX8MQ_CLK_ARM>;\n-\t\t\tenable-method = \"psci\";\n-\t\t\ti-cache-size = <0x8000>;\n-\t\t\ti-cache-line-size = <64>;\n-\t\t\ti-cache-sets = <256>;\n-\t\t\td-cache-size = <0x8000>;\n-\t\t\td-cache-line-size = <64>;\n-\t\t\td-cache-sets = <128>;\n-\t\t\tnext-level-cache = <&A53_L2>;\n-\t\t\toperating-points-v2 = <&a53_opp_table>;\n-\t\t\t#cooling-cells = <2>;\n-\t\t};\n-\n-\t\tA53_3: cpu@3 {\n-\t\t\tdevice_type = \"cpu\";\n-\t\t\tcompatible = \"arm,cortex-a53\";\n-\t\t\treg = <0x3>;\n-\t\t\tclock-latency = <61036>; /* two CLK32 periods */\n-\t\t\tclocks = <&clk IMX8MQ_CLK_ARM>;\n-\t\t\tenable-method = \"psci\";\n-\t\t\ti-cache-size = <0x8000>;\n-\t\t\ti-cache-line-size = <64>;\n-\t\t\ti-cache-sets = <256>;\n-\t\t\td-cache-size = <0x8000>;\n-\t\t\td-cache-line-size = <64>;\n-\t\t\td-cache-sets = <128>;\n-\t\t\tnext-level-cache = <&A53_L2>;\n-\t\t\toperating-points-v2 = <&a53_opp_table>;\n-\t\t\t#cooling-cells = <2>;\n-\t\t};\n-\n-\t\tA53_L2: l2-cache0 {\n-\t\t\tcompatible = \"cache\";\n-\t\t\tcache-level = <2>;\n-\t\t\tcache-size = <0x100000>;\n-\t\t\tcache-line-size = <64>;\n-\t\t\tcache-sets = <1024>;\n-\t\t};\n-\t};\n-\n-\ta53_opp_table: opp-table {\n-\t\tcompatible = \"operating-points-v2\";\n-\t\topp-shared;\n-\n-\t\topp-800000000 {\n-\t\t\topp-hz = /bits/ 64 <800000000>;\n-\t\t\topp-microvolt = <900000>;\n-\t\t\t/* Industrial only */\n-\t\t\topp-supported-hw = <0xf>, <0x4>;\n-\t\t\tclock-latency-ns = <150000>;\n-\t\t\topp-suspend;\n-\t\t};\n-\n-\t\topp-1000000000 {\n-\t\t\topp-hz = /bits/ 64 <1000000000>;\n-\t\t\topp-microvolt = <900000>;\n-\t\t\t/* Consumer only */\n-\t\t\topp-supported-hw = <0xe>, <0x3>;\n-\t\t\tclock-latency-ns = <150000>;\n-\t\t\topp-suspend;\n-\t\t};\n-\n-\t\topp-1300000000 {\n-\t\t\topp-hz = /bits/ 64 <1300000000>;\n-\t\t\topp-microvolt = <1000000>;\n-\t\t\topp-supported-hw = <0xc>, <0x4>;\n-\t\t\tclock-latency-ns = <150000>;\n-\t\t\topp-suspend;\n-\t\t};\n-\n-\t\topp-1500000000 {\n-\t\t\topp-hz = /bits/ 64 <1500000000>;\n-\t\t\topp-microvolt = <1000000>;\n-\t\t\topp-supported-hw = <0x8>, <0x3>;\n-\t\t\tclock-latency-ns = <150000>;\n-\t\t\topp-suspend;\n-\t\t};\n-\t};\n-\n-\tpmu {\n-\t\tcompatible = \"arm,cortex-a53-pmu\";\n-\t\tinterrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tinterrupt-parent = <&gic>;\n-\t};\n-\n-\tpsci {\n-\t\tcompatible = \"arm,psci-1.0\";\n-\t\tmethod = \"smc\";\n-\t};\n-\n-\tthermal-zones {\n-\t\tcpu_thermal: cpu-thermal {\n-\t\t\tpolling-delay-passive = <250>;\n-\t\t\tpolling-delay = <2000>;\n-\t\t\tthermal-sensors = <&tmu 0>;\n-\n-\t\t\ttrips {\n-\t\t\t\tcpu_alert: cpu-alert {\n-\t\t\t\t\ttemperature = <80000>;\n-\t\t\t\t\thysteresis = <2000>;\n-\t\t\t\t\ttype = \"passive\";\n-\t\t\t\t};\n-\n-\t\t\t\tcpu-crit {\n-\t\t\t\t\ttemperature = <90000>;\n-\t\t\t\t\thysteresis = <2000>;\n-\t\t\t\t\ttype = \"critical\";\n-\t\t\t\t};\n-\t\t\t};\n-\n-\t\t\tcooling-maps {\n-\t\t\t\tmap0 {\n-\t\t\t\t\ttrip = <&cpu_alert>;\n-\t\t\t\t\tcooling-device =\n-\t\t\t\t\t\t<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n-\t\t\t\t\t\t<&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n-\t\t\t\t\t\t<&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n-\t\t\t\t\t\t<&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;\n-\t\t\t\t};\n-\t\t\t};\n-\t\t};\n-\n-\t\tgpu-thermal {\n-\t\t\tpolling-delay-passive = <250>;\n-\t\t\tpolling-delay = <2000>;\n-\t\t\tthermal-sensors = <&tmu 1>;\n-\n-\t\t\ttrips {\n-\t\t\t\tgpu_alert: gpu-alert {\n-\t\t\t\t\ttemperature = <80000>;\n-\t\t\t\t\thysteresis = <2000>;\n-\t\t\t\t\ttype = \"passive\";\n-\t\t\t\t};\n-\n-\t\t\t\tgpu-crit {\n-\t\t\t\t\ttemperature = <90000>;\n-\t\t\t\t\thysteresis = <2000>;\n-\t\t\t\t\ttype = \"critical\";\n-\t\t\t\t};\n-\t\t\t};\n-\n-\t\t\tcooling-maps {\n-\t\t\t\tmap0 {\n-\t\t\t\t\ttrip = <&gpu_alert>;\n-\t\t\t\t\tcooling-device =\n-\t\t\t\t\t\t<&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;\n-\t\t\t\t};\n-\t\t\t};\n-\t\t};\n-\n-\t\tvpu-thermal {\n-\t\t\tpolling-delay-passive = <250>;\n-\t\t\tpolling-delay = <2000>;\n-\t\t\tthermal-sensors = <&tmu 2>;\n-\n-\t\t\ttrips {\n-\t\t\t\tvpu-crit {\n-\t\t\t\t\ttemperature = <90000>;\n-\t\t\t\t\thysteresis = <2000>;\n-\t\t\t\t\ttype = \"critical\";\n-\t\t\t\t};\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-\ttimer {\n-\t\tcompatible = \"arm,armv8-timer\";\n-\t\tinterrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */\n-\t\t             <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */\n-\t\t             <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */\n-\t\t             <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */\n-\t\tinterrupt-parent = <&gic>;\n-\t\tarm,no-tick-in-suspend;\n-\t};\n-\n-\tsoc: soc@0 {\n-\t\tcompatible = \"fsl,imx8mq-soc\", \"simple-bus\";\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <1>;\n-\t\tranges = <0x0 0x0 0x0 0x3e000000>;\n-\t\tdma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;\n-\t\tnvmem-cells = <&imx8mq_uid>;\n-\t\tnvmem-cell-names = \"soc_unique_id\";\n-\n-\t\taips1: bus@30000000 { /* AIPS1 */\n-\t\t\tcompatible = \"fsl,aips-bus\", \"simple-bus\";\n-\t\t\treg = <0x30000000 0x400000>;\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <1>;\n-\t\t\tranges = <0x30000000 0x30000000 0x400000>;\n-\n-\t\t\tsai1: sai@30010000 {\n-\t\t\t\t#sound-dai-cells = <0>;\n-\t\t\t\tcompatible = \"fsl,imx8mq-sai\";\n-\t\t\t\treg = <0x30010000 0x10000>;\n-\t\t\t\tinterrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\tclocks = <&clk IMX8MQ_CLK_SAI1_IPG>,\n-\t\t\t\t         <&clk IMX8MQ_CLK_SAI1_ROOT>,\n-\t\t\t\t         <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;\n-\t\t\t\tclock-names = \"bus\", \"mclk1\", \"mclk2\", \"mclk3\";\n-\t\t\t\tdmas = <&sdma2 8 24 0>, <&sdma1 9 24 0>;\n-\t\t\t\tdma-names = \"rx\", \"tx\";\n-\t\t\t\tstatus = \"disabled\";\n-\t\t\t};\n-\n-\t\t\tsai6: sai@30030000 {\n-\t\t\t\t#sound-dai-cells = <0>;\n-\t\t\t\tcompatible = \"fsl,imx8mq-sai\";\n-\t\t\t\treg = <0x30030000 0x10000>;\n-\t\t\t\tinterrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\tclocks = <&clk IMX8MQ_CLK_SAI6_IPG>,\n-\t\t\t\t         <&clk IMX8MQ_CLK_SAI6_ROOT>,\n-\t\t\t\t         <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;\n-\t\t\t\tclock-names = \"bus\", \"mclk1\", \"mclk2\", \"mclk3\";\n-\t\t\t\tdmas = <&sdma2 4 24 0>, <&sdma2 5 24 0>;\n-\t\t\t\tdma-names = \"rx\", \"tx\";\n-\t\t\t\tstatus = \"disabled\";\n-\t\t\t};\n-\n-\t\t\tsai5: sai@30040000 {\n-\t\t\t\t#sound-dai-cells = <0>;\n-\t\t\t\tcompatible = \"fsl,imx8mq-sai\";\n-\t\t\t\treg = <0x30040000 0x10000>;\n-\t\t\t\tinterrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\tclocks = <&clk IMX8MQ_CLK_SAI5_IPG>,\n-\t\t\t\t         <&clk IMX8MQ_CLK_SAI5_ROOT>,\n-\t\t\t\t         <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;\n-\t\t\t\tclock-names = \"bus\", \"mclk1\", \"mclk2\", \"mclk3\";\n-\t\t\t\tdmas = <&sdma2 2 24 0>, <&sdma2 3 24 0>;\n-\t\t\t\tdma-names = \"rx\", \"tx\";\n-\t\t\t\tstatus = \"disabled\";\n-\t\t\t};\n-\n-\t\t\tsai4: sai@30050000 {\n-\t\t\t\t#sound-dai-cells = <0>;\n-\t\t\t\tcompatible = \"fsl,imx8mq-sai\";\n-\t\t\t\treg = <0x30050000 0x10000>;\n-\t\t\t\tinterrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\tclocks = <&clk IMX8MQ_CLK_SAI4_IPG>,\n-\t\t\t\t         <&clk IMX8MQ_CLK_SAI4_ROOT>,\n-\t\t\t\t         <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;\n-\t\t\t\tclock-names = \"bus\", \"mclk1\", \"mclk2\", \"mclk3\";\n-\t\t\t\tdmas = <&sdma2 0 24 0>, <&sdma2 1 24 0>;\n-\t\t\t\tdma-names = \"rx\", \"tx\";\n-\t\t\t\tstatus = \"disabled\";\n-\t\t\t};\n-\n-\t\t\tgpio1: gpio@30200000 {\n-\t\t\t\tcompatible = \"fsl,imx8mq-gpio\", \"fsl,imx35-gpio\";\n-\t\t\t\treg = <0x30200000 0x10000>;\n-\t\t\t\tinterrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t\t             <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\tclocks = <&clk IMX8MQ_CLK_GPIO1_ROOT>;\n-\t\t\t\tgpio-controller;\n-\t\t\t\t#gpio-cells = <2>;\n-\t\t\t\tinterrupt-controller;\n-\t\t\t\t#interrupt-cells = <2>;\n-\t\t\t\tgpio-ranges = <&iomuxc 0 10 30>;\n-\t\t\t};\n-\n-\t\t\tgpio2: gpio@30210000 {\n-\t\t\t\tcompatible = \"fsl,imx8mq-gpio\", \"fsl,imx35-gpio\";\n-\t\t\t\treg = <0x30210000 0x10000>;\n-\t\t\t\tinterrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t\t             <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\tclocks = <&clk IMX8MQ_CLK_GPIO2_ROOT>;\n-\t\t\t\tgpio-controller;\n-\t\t\t\t#gpio-cells = <2>;\n-\t\t\t\tinterrupt-controller;\n-\t\t\t\t#interrupt-cells = <2>;\n-\t\t\t\tgpio-ranges = <&iomuxc 0 40 21>;\n-\t\t\t};\n-\n-\t\t\tgpio3: gpio@30220000 {\n-\t\t\t\tcompatible = \"fsl,imx8mq-gpio\", \"fsl,imx35-gpio\";\n-\t\t\t\treg = <0x30220000 0x10000>;\n-\t\t\t\tinterrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t\t             <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\tclocks = <&clk IMX8MQ_CLK_GPIO3_ROOT>;\n-\t\t\t\tgpio-controller;\n-\t\t\t\t#gpio-cells = <2>;\n-\t\t\t\tinterrupt-controller;\n-\t\t\t\t#interrupt-cells = <2>;\n-\t\t\t\tgpio-ranges = <&iomuxc 0 61 26>;\n-\t\t\t};\n-\n-\t\t\tgpio4: gpio@30230000 {\n-\t\t\t\tcompatible = \"fsl,imx8mq-gpio\", \"fsl,imx35-gpio\";\n-\t\t\t\treg = <0x30230000 0x10000>;\n-\t\t\t\tinterrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t\t             <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\tclocks = <&clk IMX8MQ_CLK_GPIO4_ROOT>;\n-\t\t\t\tgpio-controller;\n-\t\t\t\t#gpio-cells = <2>;\n-\t\t\t\tinterrupt-controller;\n-\t\t\t\t#interrupt-cells = <2>;\n-\t\t\t\tgpio-ranges = <&iomuxc 0 87 32>;\n-\t\t\t};\n-\n-\t\t\tgpio5: gpio@30240000 {\n-\t\t\t\tcompatible = \"fsl,imx8mq-gpio\", \"fsl,imx35-gpio\";\n-\t\t\t\treg = <0x30240000 0x10000>;\n-\t\t\t\tinterrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t\t             <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\tclocks = <&clk IMX8MQ_CLK_GPIO5_ROOT>;\n-\t\t\t\tgpio-controller;\n-\t\t\t\t#gpio-cells = <2>;\n-\t\t\t\tinterrupt-controller;\n-\t\t\t\t#interrupt-cells = <2>;\n-\t\t\t\tgpio-ranges = <&iomuxc 0 119 30>;\n-\t\t\t};\n-\n-\t\t\ttmu: tmu@30260000 {\n-\t\t\t\tcompatible = \"fsl,imx8mq-tmu\";\n-\t\t\t\treg = <0x30260000 0x10000>;\n-\t\t\t\tinterrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\tclocks = <&clk IMX8MQ_CLK_TMU_ROOT>;\n-\t\t\t\tlittle-endian;\n-\t\t\t\tfsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;\n-\t\t\t\tfsl,tmu-calibration = <0x00000000 0x00000023>,\n-\t\t\t\t\t\t      <0x00000001 0x00000029>,\n-\t\t\t\t\t\t      <0x00000002 0x0000002f>,\n-\t\t\t\t\t\t      <0x00000003 0x00000035>,\n-\t\t\t\t\t\t      <0x00000004 0x0000003d>,\n-\t\t\t\t\t\t      <0x00000005 0x00000043>,\n-\t\t\t\t\t\t      <0x00000006 0x0000004b>,\n-\t\t\t\t\t\t      <0x00000007 0x00000051>,\n-\t\t\t\t\t\t      <0x00000008 0x00000057>,\n-\t\t\t\t\t\t      <0x00000009 0x0000005f>,\n-\t\t\t\t\t\t      <0x0000000a 0x00000067>,\n-\t\t\t\t\t\t      <0x0000000b 0x0000006f>,\n-\n-\t\t\t\t\t\t      <0x00010000 0x0000001b>,\n-\t\t\t\t\t\t      <0x00010001 0x00000023>,\n-\t\t\t\t\t\t      <0x00010002 0x0000002b>,\n-\t\t\t\t\t\t      <0x00010003 0x00000033>,\n-\t\t\t\t\t\t      <0x00010004 0x0000003b>,\n-\t\t\t\t\t\t      <0x00010005 0x00000043>,\n-\t\t\t\t\t\t      <0x00010006 0x0000004b>,\n-\t\t\t\t\t\t      <0x00010007 0x00000055>,\n-\t\t\t\t\t\t      <0x00010008 0x0000005d>,\n-\t\t\t\t\t\t      <0x00010009 0x00000067>,\n-\t\t\t\t\t\t      <0x0001000a 0x00000070>,\n-\n-\t\t\t\t\t\t      <0x00020000 0x00000017>,\n-\t\t\t\t\t\t      <0x00020001 0x00000023>,\n-\t\t\t\t\t\t      <0x00020002 0x0000002d>,\n-\t\t\t\t\t\t      <0x00020003 0x00000037>,\n-\t\t\t\t\t\t      <0x00020004 0x00000041>,\n-\t\t\t\t\t\t      <0x00020005 0x0000004b>,\n-\t\t\t\t\t\t      <0x00020006 0x00000057>,\n-\t\t\t\t\t\t      <0x00020007 0x00000063>,\n-\t\t\t\t\t\t      <0x00020008 0x0000006f>,\n-\n-\t\t\t\t\t\t      <0x00030000 0x00000015>,\n-\t\t\t\t\t\t      <0x00030001 0x00000021>,\n-\t\t\t\t\t\t      <0x00030002 0x0000002d>,\n-\t\t\t\t\t\t      <0x00030003 0x00000039>,\n-\t\t\t\t\t\t      <0x00030004 0x00000045>,\n-\t\t\t\t\t\t      <0x00030005 0x00000053>,\n-\t\t\t\t\t\t      <0x00030006 0x0000005f>,\n-\t\t\t\t\t\t      <0x00030007 0x00000071>;\n-\t\t\t\t#thermal-sensor-cells = <1>;\n-\t\t\t};\n-\n-\t\t\twdog1: watchdog@30280000 {\n-\t\t\t\tcompatible = \"fsl,imx8mq-wdt\", \"fsl,imx21-wdt\";\n-\t\t\t\treg = <0x30280000 0x10000>;\n-\t\t\t\tinterrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\tclocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>;\n-\t\t\t\tstatus = \"disabled\";\n-\t\t\t};\n-\n-\t\t\twdog2: watchdog@30290000 {\n-\t\t\t\tcompatible = \"fsl,imx8mq-wdt\", \"fsl,imx21-wdt\";\n-\t\t\t\treg = <0x30290000 0x10000>;\n-\t\t\t\tinterrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\tclocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>;\n-\t\t\t\tstatus = \"disabled\";\n-\t\t\t};\n-\n-\t\t\twdog3: watchdog@302a0000 {\n-\t\t\t\tcompatible = \"fsl,imx8mq-wdt\", \"fsl,imx21-wdt\";\n-\t\t\t\treg = <0x302a0000 0x10000>;\n-\t\t\t\tinterrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\tclocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>;\n-\t\t\t\tstatus = \"disabled\";\n-\t\t\t};\n-\n-\t\t\tsdma2: dma-controller@302c0000 {\n-\t\t\t\tcompatible = \"fsl,imx8mq-sdma\",\"fsl,imx7d-sdma\";\n-\t\t\t\treg = <0x302c0000 0x10000>;\n-\t\t\t\tinterrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\tclocks = <&clk IMX8MQ_CLK_SDMA2_ROOT>,\n-\t\t\t\t\t <&clk IMX8MQ_CLK_SDMA2_ROOT>;\n-\t\t\t\tclock-names = \"ipg\", \"ahb\";\n-\t\t\t\t#dma-cells = <3>;\n-\t\t\t\tfsl,sdma-ram-script-name = \"imx/sdma/sdma-imx7d.bin\";\n-\t\t\t};\n-\n-\t\t\tlcdif: lcd-controller@30320000 {\n-\t\t\t\tcompatible = \"fsl,imx8mq-lcdif\", \"fsl,imx28-lcdif\";\n-\t\t\t\treg = <0x30320000 0x10000>;\n-\t\t\t\tinterrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\tclocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>;\n-\t\t\t\tclock-names = \"pix\";\n-\t\t\t\tassigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,\n-\t\t\t\t\t\t  <&clk IMX8MQ_VIDEO_PLL1_BYPASS>,\n-\t\t\t\t\t\t  <&clk IMX8MQ_CLK_LCDIF_PIXEL>,\n-\t\t\t\t\t\t  <&clk IMX8MQ_VIDEO_PLL1>;\n-\t\t\t\tassigned-clock-parents = <&clk IMX8MQ_CLK_25M>,\n-\t\t\t\t\t\t  <&clk IMX8MQ_VIDEO_PLL1>,\n-\t\t\t\t\t\t  <&clk IMX8MQ_VIDEO_PLL1_OUT>;\n-\t\t\t\tassigned-clock-rates = <0>, <0>, <0>, <594000000>;\n-\t\t\t\tstatus = \"disabled\";\n-\n-\t\t\t\tport {\n-\t\t\t\t\tlcdif_mipi_dsi: endpoint {\n-\t\t\t\t\t\tremote-endpoint = <&mipi_dsi_lcdif_in>;\n-\t\t\t\t\t};\n-\t\t\t\t};\n-\t\t\t};\n-\n-\t\t\tiomuxc: pinctrl@30330000 {\n-\t\t\t\tcompatible = \"fsl,imx8mq-iomuxc\";\n-\t\t\t\treg = <0x30330000 0x10000>;\n-\t\t\t};\n-\n-\t\t\tiomuxc_gpr: syscon@30340000 {\n-\t\t\t\tcompatible = \"fsl,imx8mq-iomuxc-gpr\", \"fsl,imx6q-iomuxc-gpr\",\n-\t\t\t\t\t     \"syscon\", \"simple-mfd\";\n-\t\t\t\treg = <0x30340000 0x10000>;\n-\n-\t\t\t\tmux: mux-controller {\n-\t\t\t\t\tcompatible = \"mmio-mux\";\n-\t\t\t\t\t#mux-control-cells = <1>;\n-\t\t\t\t\tmux-reg-masks = <0x34 0x00000004>; /* MIPI_MUX_SEL */\n-\t\t\t\t};\n-\t\t\t};\n-\n-\t\t\tocotp: efuse@30350000 {\n-\t\t\t\tcompatible = \"fsl,imx8mq-ocotp\", \"syscon\";\n-\t\t\t\treg = <0x30350000 0x10000>;\n-\t\t\t\tclocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>;\n-\t\t\t\t#address-cells = <1>;\n-\t\t\t\t#size-cells = <1>;\n-\n-\t\t\t\timx8mq_uid: soc-uid@410 {\n-\t\t\t\t\treg = <0x4 0x8>;\n-\t\t\t\t};\n-\n-\t\t\t\tcpu_speed_grade: speed-grade@10 {\n-\t\t\t\t\treg = <0x10 4>;\n-\t\t\t\t};\n-\n-\t\t\t\tfec_mac_address: mac-address@90 {\n-\t\t\t\t\treg = <0x90 6>;\n-\t\t\t\t};\n-\t\t\t};\n-\n-\t\t\tanatop: syscon@30360000 {\n-\t\t\t\tcompatible = \"fsl,imx8mq-anatop\", \"syscon\";\n-\t\t\t\treg = <0x30360000 0x10000>;\n-\t\t\t\tinterrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t};\n-\n-\t\t\tsnvs: snvs@30370000 {\n-\t\t\t\tcompatible = \"fsl,sec-v4.0-mon\", \"syscon\", \"simple-mfd\";\n-\t\t\t\treg = <0x30370000 0x10000>;\n-\n-\t\t\t\tsnvs_rtc: snvs-rtc-lp{\n-\t\t\t\t\tcompatible = \"fsl,sec-v4.0-mon-rtc-lp\";\n-\t\t\t\t\tregmap =<&snvs>;\n-\t\t\t\t\toffset = <0x34>;\n-\t\t\t\t\tinterrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t\t\t\t<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\t\tclocks = <&clk IMX8MQ_CLK_SNVS_ROOT>;\n-\t\t\t\t\tclock-names = \"snvs-rtc\";\n-\t\t\t\t};\n-\n-\t\t\t\tsnvs_pwrkey: snvs-powerkey {\n-\t\t\t\t\tcompatible = \"fsl,sec-v4.0-pwrkey\";\n-\t\t\t\t\tregmap = <&snvs>;\n-\t\t\t\t\tinterrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\t\tclocks = <&clk IMX8MQ_CLK_SNVS_ROOT>;\n-\t\t\t\t\tclock-names = \"snvs-pwrkey\";\n-\t\t\t\t\tlinux,keycode = <KEY_POWER>;\n-\t\t\t\t\twakeup-source;\n-\t\t\t\t\tstatus = \"disabled\";\n-\t\t\t\t};\n-\t\t\t};\n-\n-\t\t\tclk: clock-controller@30380000 {\n-\t\t\t\tcompatible = \"fsl,imx8mq-ccm\";\n-\t\t\t\treg = <0x30380000 0x10000>;\n-\t\t\t\tinterrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t\t             <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\t#clock-cells = <1>;\n-\t\t\t\tclocks = <&ckil>, <&osc_25m>, <&osc_27m>,\n-\t\t\t\t         <&clk_ext1>, <&clk_ext2>,\n-\t\t\t\t         <&clk_ext3>, <&clk_ext4>;\n-\t\t\t\tclock-names = \"ckil\", \"osc_25m\", \"osc_27m\",\n-\t\t\t\t              \"clk_ext1\", \"clk_ext2\",\n-\t\t\t\t              \"clk_ext3\", \"clk_ext4\";\n-\t\t\t\tassigned-clocks = <&clk IMX8MQ_CLK_A53_SRC>,\n-\t\t\t\t\t\t  <&clk IMX8MQ_CLK_A53_CORE>,\n-\t\t\t\t\t\t  <&clk IMX8MQ_CLK_NOC>,\n-\t\t\t\t\t\t  <&clk IMX8MQ_CLK_AUDIO_AHB>,\n-\t\t\t\t\t\t  <&clk IMX8MQ_AUDIO_PLL1_BYPASS>,\n-\t\t\t\t\t\t  <&clk IMX8MQ_AUDIO_PLL2_BYPASS>,\n-\t\t\t\t\t\t  <&clk IMX8MQ_AUDIO_PLL1>,\n-\t\t\t\t\t\t  <&clk IMX8MQ_AUDIO_PLL2>;\n-\t\t\t\tassigned-clock-rates = <0>, <0>,\n-\t\t\t\t\t\t       <800000000>,\n-\t\t\t\t\t\t       <0>,\n-\t\t\t\t\t\t       <0>,\n-\t\t\t\t\t\t       <0>,\n-\t\t\t\t\t\t       <786432000>,\n-\t\t\t\t\t\t       <722534400>;\n-\t\t\t\tassigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>,\n-\t\t\t\t\t\t\t <&clk IMX8MQ_ARM_PLL_OUT>,\n-\t\t\t\t\t\t\t <0>,\n-\t\t\t\t\t\t\t <&clk IMX8MQ_SYS2_PLL_500M>,\n-\t\t\t\t\t\t\t <&clk IMX8MQ_AUDIO_PLL1>,\n-\t\t\t\t\t\t\t <&clk IMX8MQ_AUDIO_PLL2>;\n-\t\t\t};\n-\n-\t\t\tsrc: reset-controller@30390000 {\n-\t\t\t\tcompatible = \"fsl,imx8mq-src\", \"syscon\";\n-\t\t\t\treg = <0x30390000 0x10000>;\n-\t\t\t\tinterrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\t#reset-cells = <1>;\n-\t\t\t};\n-\n-\t\t\tgpc: gpc@303a0000 {\n-\t\t\t\tcompatible = \"fsl,imx8mq-gpc\";\n-\t\t\t\treg = <0x303a0000 0x10000>;\n-\t\t\t\tinterrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\tinterrupt-parent = <&gic>;\n-\t\t\t\tinterrupt-controller;\n-\t\t\t\t#interrupt-cells = <3>;\n-\n-\t\t\t\tpgc {\n-\t\t\t\t\t#address-cells = <1>;\n-\t\t\t\t\t#size-cells = <0>;\n-\n-\t\t\t\t\tpgc_mipi: power-domain@0 {\n-\t\t\t\t\t\t#power-domain-cells = <0>;\n-\t\t\t\t\t\treg = <IMX8M_POWER_DOMAIN_MIPI>;\n-\t\t\t\t\t};\n-\n-\t\t\t\t\t/*\n-\t\t\t\t\t * As per comment in ATF source code:\n-\t\t\t\t\t *\n-\t\t\t\t\t * PCIE1 and PCIE2 share the\n-\t\t\t\t\t * same reset signal, if we\n-\t\t\t\t\t * power down PCIE2, PCIE1\n-\t\t\t\t\t * will be held in reset too.\n-\t\t\t\t\t *\n-\t\t\t\t\t * So instead of creating two\n-\t\t\t\t\t * separate power domains for\n-\t\t\t\t\t * PCIE1 and PCIE2 we create a\n-\t\t\t\t\t * link between both and use\n-\t\t\t\t\t * it as a shared PCIE power\n-\t\t\t\t\t * domain.\n-\t\t\t\t\t */\n-\t\t\t\t\tpgc_pcie: power-domain@1 {\n-\t\t\t\t\t\t#power-domain-cells = <0>;\n-\t\t\t\t\t\treg = <IMX8M_POWER_DOMAIN_PCIE1>;\n-\t\t\t\t\t\tpower-domains = <&pgc_pcie2>;\n-\t\t\t\t\t};\n-\n-\t\t\t\t\tpgc_otg1: power-domain@2 {\n-\t\t\t\t\t\t#power-domain-cells = <0>;\n-\t\t\t\t\t\treg = <IMX8M_POWER_DOMAIN_USB_OTG1>;\n-\t\t\t\t\t};\n-\n-\t\t\t\t\tpgc_otg2: power-domain@3 {\n-\t\t\t\t\t\t#power-domain-cells = <0>;\n-\t\t\t\t\t\treg = <IMX8M_POWER_DOMAIN_USB_OTG2>;\n-\t\t\t\t\t};\n-\n-\t\t\t\t\tpgc_ddr1: power-domain@4 {\n-\t\t\t\t\t\t#power-domain-cells = <0>;\n-\t\t\t\t\t\treg = <IMX8M_POWER_DOMAIN_DDR1>;\n-\t\t\t\t\t};\n-\n-\t\t\t\t\tpgc_gpu: power-domain@5 {\n-\t\t\t\t\t\t#power-domain-cells = <0>;\n-\t\t\t\t\t\treg = <IMX8M_POWER_DOMAIN_GPU>;\n-\t\t\t\t\t\tclocks = <&clk IMX8MQ_CLK_GPU_ROOT>,\n-\t\t\t\t\t\t         <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,\n-\t\t\t\t\t\t\t <&clk IMX8MQ_CLK_GPU_AXI>,\n-\t\t\t\t\t\t         <&clk IMX8MQ_CLK_GPU_AHB>;\n-\t\t\t\t\t};\n-\n-\t\t\t\t\tpgc_vpu: power-domain@6 {\n-\t\t\t\t\t\t#power-domain-cells = <0>;\n-\t\t\t\t\t\treg = <IMX8M_POWER_DOMAIN_VPU>;\n-\t\t\t\t\t\tclocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>,\n-\t\t\t\t\t\t\t <&clk IMX8MQ_CLK_VPU_G1_ROOT>,\n-\t\t\t\t\t\t\t <&clk IMX8MQ_CLK_VPU_G2_ROOT>;\n-\t\t\t\t\t\tassigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,\n-\t\t\t\t\t\t\t\t  <&clk IMX8MQ_CLK_VPU_G2>,\n-\t\t\t\t\t\t\t\t  <&clk IMX8MQ_CLK_VPU_BUS>,\n-\t\t\t\t\t\t\t\t  <&clk IMX8MQ_VPU_PLL_BYPASS>;\n-\t\t\t\t\t\tassigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,\n-\t\t\t\t\t\t\t\t\t <&clk IMX8MQ_VPU_PLL_OUT>,\n-\t\t\t\t\t\t\t\t\t <&clk IMX8MQ_SYS1_PLL_800M>,\n-\t\t\t\t\t\t\t\t\t <&clk IMX8MQ_VPU_PLL>;\n-\t\t\t\t\t\tassigned-clock-rates = <600000000>,\n-\t\t\t\t\t\t\t\t       <600000000>,\n-\t\t\t\t\t\t\t\t       <800000000>,\n-\t\t\t\t\t\t\t\t       <0>;\n-\t\t\t\t\t};\n-\n-\t\t\t\t\tpgc_disp: power-domain@7 {\n-\t\t\t\t\t\t#power-domain-cells = <0>;\n-\t\t\t\t\t\treg = <IMX8M_POWER_DOMAIN_DISP>;\n-\t\t\t\t\t};\n-\n-\t\t\t\t\tpgc_mipi_csi1: power-domain@8 {\n-\t\t\t\t\t\t#power-domain-cells = <0>;\n-\t\t\t\t\t\treg = <IMX8M_POWER_DOMAIN_MIPI_CSI1>;\n-\t\t\t\t\t};\n-\n-\t\t\t\t\tpgc_mipi_csi2: power-domain@9 {\n-\t\t\t\t\t\t#power-domain-cells = <0>;\n-\t\t\t\t\t\treg = <IMX8M_POWER_DOMAIN_MIPI_CSI2>;\n-\t\t\t\t\t};\n-\n-\t\t\t\t\tpgc_pcie2: power-domain@a {\n-\t\t\t\t\t\t#power-domain-cells = <0>;\n-\t\t\t\t\t\treg = <IMX8M_POWER_DOMAIN_PCIE2>;\n-\t\t\t\t\t};\n-\t\t\t\t};\n-\t\t\t};\n-\t\t};\n-\n-\t\taips2: bus@30400000 { /* AIPS2 */\n-\t\t\tcompatible = \"fsl,aips-bus\", \"simple-bus\";\n-\t\t\treg = <0x30400000 0x400000>;\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <1>;\n-\t\t\tranges = <0x30400000 0x30400000 0x400000>;\n-\n-\t\t\tpwm1: pwm@30660000 {\n-\t\t\t\tcompatible = \"fsl,imx8mq-pwm\", \"fsl,imx27-pwm\";\n-\t\t\t\treg = <0x30660000 0x10000>;\n-\t\t\t\tinterrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\tclocks = <&clk IMX8MQ_CLK_PWM1_ROOT>,\n-\t\t\t\t         <&clk IMX8MQ_CLK_PWM1_ROOT>;\n-\t\t\t\tclock-names = \"ipg\", \"per\";\n-\t\t\t\t#pwm-cells = <3>;\n-\t\t\t\tstatus = \"disabled\";\n-\t\t\t};\n-\n-\t\t\tpwm2: pwm@30670000 {\n-\t\t\t\tcompatible = \"fsl,imx8mq-pwm\", \"fsl,imx27-pwm\";\n-\t\t\t\treg = <0x30670000 0x10000>;\n-\t\t\t\tinterrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\tclocks = <&clk IMX8MQ_CLK_PWM2_ROOT>,\n-\t\t\t\t         <&clk IMX8MQ_CLK_PWM2_ROOT>;\n-\t\t\t\tclock-names = \"ipg\", \"per\";\n-\t\t\t\t#pwm-cells = <3>;\n-\t\t\t\tstatus = \"disabled\";\n-\t\t\t};\n-\n-\t\t\tpwm3: pwm@30680000 {\n-\t\t\t\tcompatible = \"fsl,imx8mq-pwm\", \"fsl,imx27-pwm\";\n-\t\t\t\treg = <0x30680000 0x10000>;\n-\t\t\t\tinterrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\tclocks = <&clk IMX8MQ_CLK_PWM3_ROOT>,\n-\t\t\t\t         <&clk IMX8MQ_CLK_PWM3_ROOT>;\n-\t\t\t\tclock-names = \"ipg\", \"per\";\n-\t\t\t\t#pwm-cells = <3>;\n-\t\t\t\tstatus = \"disabled\";\n-\t\t\t};\n-\n-\t\t\tpwm4: pwm@30690000 {\n-\t\t\t\tcompatible = \"fsl,imx8mq-pwm\", \"fsl,imx27-pwm\";\n-\t\t\t\treg = <0x30690000 0x10000>;\n-\t\t\t\tinterrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\tclocks = <&clk IMX8MQ_CLK_PWM4_ROOT>,\n-\t\t\t\t         <&clk IMX8MQ_CLK_PWM4_ROOT>;\n-\t\t\t\tclock-names = \"ipg\", \"per\";\n-\t\t\t\t#pwm-cells = <3>;\n-\t\t\t\tstatus = \"disabled\";\n-\t\t\t};\n-\n-\t\t\tsystem_counter: timer@306a0000 {\n-\t\t\t\tcompatible = \"nxp,sysctr-timer\";\n-\t\t\t\treg = <0x306a0000 0x20000>;\n-\t\t\t\tinterrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\tclocks = <&osc_25m>;\n-\t\t\t\tclock-names = \"per\";\n-\t\t\t};\n-\t\t};\n-\n-\t\taips3: bus@30800000 { /* AIPS3 */\n-\t\t\tcompatible = \"fsl,aips-bus\", \"simple-bus\";\n-\t\t\treg = <0x30800000 0x400000>;\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <1>;\n-\t\t\tranges = <0x30800000 0x30800000 0x400000>,\n-\t\t\t\t <0x08000000 0x08000000 0x10000000>;\n-\n-\t\t\tspdif1: spdif@30810000 {\n-\t\t\t\tcompatible = \"fsl,imx35-spdif\";\n-\t\t\t\treg = <0x30810000 0x10000>;\n-\t\t\t\tinterrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\tclocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */\n-\t\t\t\t\t<&clk IMX8MQ_CLK_25M>, /* rxtx0 */\n-\t\t\t\t\t<&clk IMX8MQ_CLK_SPDIF1>, /* rxtx1 */\n-\t\t\t\t\t<&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */\n-\t\t\t\t\t<&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */\n-\t\t\t\t\t<&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */\n-\t\t\t\t\t<&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */\n-\t\t\t\t\t<&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */\n-\t\t\t\t\t<&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */\n-\t\t\t\t\t<&clk IMX8MQ_CLK_DUMMY>; /* spba */\n-\t\t\t\tclock-names = \"core\", \"rxtx0\",\n-\t\t\t\t\t      \"rxtx1\", \"rxtx2\",\n-\t\t\t\t\t      \"rxtx3\", \"rxtx4\",\n-\t\t\t\t\t      \"rxtx5\", \"rxtx6\",\n-\t\t\t\t\t      \"rxtx7\", \"spba\";\n-\t\t\t\tdmas = <&sdma1 8 18 0>, <&sdma1 9 18 0>;\n-\t\t\t\tdma-names = \"rx\", \"tx\";\n-\t\t\t\tstatus = \"disabled\";\n-\t\t\t};\n-\n-\t\t\tecspi1: spi@30820000 {\n-\t\t\t\t#address-cells = <1>;\n-\t\t\t\t#size-cells = <0>;\n-\t\t\t\tcompatible = \"fsl,imx8mq-ecspi\", \"fsl,imx51-ecspi\";\n-\t\t\t\treg = <0x30820000 0x10000>;\n-\t\t\t\tinterrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\tclocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>,\n-\t\t\t\t\t <&clk IMX8MQ_CLK_ECSPI1_ROOT>;\n-\t\t\t\tclock-names = \"ipg\", \"per\";\n-\t\t\t\tdmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;\n-\t\t\t\tdma-names = \"rx\", \"tx\";\n-\t\t\t\tstatus = \"disabled\";\n-\t\t\t};\n-\n-\t\t\tecspi2: spi@30830000 {\n-\t\t\t\t#address-cells = <1>;\n-\t\t\t\t#size-cells = <0>;\n-\t\t\t\tcompatible = \"fsl,imx8mq-ecspi\", \"fsl,imx51-ecspi\";\n-\t\t\t\treg = <0x30830000 0x10000>;\n-\t\t\t\tinterrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\tclocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>,\n-\t\t\t\t\t <&clk IMX8MQ_CLK_ECSPI2_ROOT>;\n-\t\t\t\tclock-names = \"ipg\", \"per\";\n-\t\t\t\tdmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;\n-\t\t\t\tdma-names = \"rx\", \"tx\";\n-\t\t\t\tstatus = \"disabled\";\n-\t\t\t};\n-\n-\t\t\tecspi3: spi@30840000 {\n-\t\t\t\t#address-cells = <1>;\n-\t\t\t\t#size-cells = <0>;\n-\t\t\t\tcompatible = \"fsl,imx8mq-ecspi\", \"fsl,imx51-ecspi\";\n-\t\t\t\treg = <0x30840000 0x10000>;\n-\t\t\t\tinterrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\tclocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>,\n-\t\t\t\t\t <&clk IMX8MQ_CLK_ECSPI3_ROOT>;\n-\t\t\t\tclock-names = \"ipg\", \"per\";\n-\t\t\t\tdmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;\n-\t\t\t\tdma-names = \"rx\", \"tx\";\n-\t\t\t\tstatus = \"disabled\";\n-\t\t\t};\n-\n-\t\t\tuart1: serial@30860000 {\n-\t\t\t\tcompatible = \"fsl,imx8mq-uart\",\n-\t\t\t\t             \"fsl,imx6q-uart\";\n-\t\t\t\treg = <0x30860000 0x10000>;\n-\t\t\t\tinterrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\tclocks = <&clk IMX8MQ_CLK_UART1_ROOT>,\n-\t\t\t\t         <&clk IMX8MQ_CLK_UART1_ROOT>;\n-\t\t\t\tclock-names = \"ipg\", \"per\";\n-\t\t\t\tstatus = \"disabled\";\n-\t\t\t};\n-\n-\t\t\tuart3: serial@30880000 {\n-\t\t\t\tcompatible = \"fsl,imx8mq-uart\",\n-\t\t\t\t             \"fsl,imx6q-uart\";\n-\t\t\t\treg = <0x30880000 0x10000>;\n-\t\t\t\tinterrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\tclocks = <&clk IMX8MQ_CLK_UART3_ROOT>,\n-\t\t\t\t         <&clk IMX8MQ_CLK_UART3_ROOT>;\n-\t\t\t\tclock-names = \"ipg\", \"per\";\n-\t\t\t\tstatus = \"disabled\";\n-\t\t\t};\n-\n-\t\t\tuart2: serial@30890000 {\n-\t\t\t\tcompatible = \"fsl,imx8mq-uart\",\n-\t\t\t\t             \"fsl,imx6q-uart\";\n-\t\t\t\treg = <0x30890000 0x10000>;\n-\t\t\t\tinterrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\tclocks = <&clk IMX8MQ_CLK_UART2_ROOT>,\n-\t\t\t\t         <&clk IMX8MQ_CLK_UART2_ROOT>;\n-\t\t\t\tclock-names = \"ipg\", \"per\";\n-\t\t\t\tstatus = \"disabled\";\n-\t\t\t};\n-\n-\t\t\tspdif2: spdif@308a0000 {\n-\t\t\t\tcompatible = \"fsl,imx35-spdif\";\n-\t\t\t\treg = <0x308a0000 0x10000>;\n-\t\t\t\tinterrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\tclocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */\n-\t\t\t\t\t<&clk IMX8MQ_CLK_25M>, /* rxtx0 */\n-\t\t\t\t\t<&clk IMX8MQ_CLK_SPDIF2>, /* rxtx1 */\n-\t\t\t\t\t<&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */\n-\t\t\t\t\t<&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */\n-\t\t\t\t\t<&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */\n-\t\t\t\t\t<&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */\n-\t\t\t\t\t<&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */\n-\t\t\t\t\t<&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */\n-\t\t\t\t\t<&clk IMX8MQ_CLK_DUMMY>; /* spba */\n-\t\t\t\tclock-names = \"core\", \"rxtx0\",\n-\t\t\t\t\t      \"rxtx1\", \"rxtx2\",\n-\t\t\t\t\t      \"rxtx3\", \"rxtx4\",\n-\t\t\t\t\t      \"rxtx5\", \"rxtx6\",\n-\t\t\t\t\t      \"rxtx7\", \"spba\";\n-\t\t\t\tdmas = <&sdma1 16 18 0>, <&sdma1 17 18 0>;\n-\t\t\t\tdma-names = \"rx\", \"tx\";\n-\t\t\t\tstatus = \"disabled\";\n-\t\t\t};\n-\n-\t\t\tsai2: sai@308b0000 {\n-\t\t\t\t#sound-dai-cells = <0>;\n-\t\t\t\tcompatible = \"fsl,imx8mq-sai\";\n-\t\t\t\treg = <0x308b0000 0x10000>;\n-\t\t\t\tinterrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\tclocks = <&clk IMX8MQ_CLK_SAI2_IPG>,\n-\t\t\t\t\t <&clk IMX8MQ_CLK_SAI2_ROOT>,\n-\t\t\t\t\t <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;\n-\t\t\t\tclock-names = \"bus\", \"mclk1\", \"mclk2\", \"mclk3\";\n-\t\t\t\tdmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>;\n-\t\t\t\tdma-names = \"rx\", \"tx\";\n-\t\t\t\tstatus = \"disabled\";\n-\t\t\t};\n-\n-\t\t\tsai3: sai@308c0000 {\n-\t\t\t\t#sound-dai-cells = <0>;\n-\t\t\t\tcompatible = \"fsl,imx8mq-sai\";\n-\t\t\t\treg = <0x308c0000 0x10000>;\n-\t\t\t\tinterrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\tclocks = <&clk IMX8MQ_CLK_SAI3_IPG>,\n-\t\t\t\t         <&clk IMX8MQ_CLK_SAI3_ROOT>,\n-\t\t\t\t         <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;\n-\t\t\t\tclock-names = \"bus\", \"mclk1\", \"mclk2\", \"mclk3\";\n-\t\t\t\tdmas = <&sdma1 12 24 0>, <&sdma1 13 24 0>;\n-\t\t\t\tdma-names = \"rx\", \"tx\";\n-\t\t\t\tstatus = \"disabled\";\n-\t\t\t};\n-\n-\t\t\tcrypto: crypto@30900000 {\n-\t\t\t\tcompatible = \"fsl,sec-v4.0\";\n-\t\t\t\t#address-cells = <1>;\n-\t\t\t\t#size-cells = <1>;\n-\t\t\t\treg = <0x30900000 0x40000>;\n-\t\t\t\tranges = <0 0x30900000 0x40000>;\n-\t\t\t\tinterrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\tclocks = <&clk IMX8MQ_CLK_AHB>,\n-\t\t\t\t\t <&clk IMX8MQ_CLK_IPG_ROOT>;\n-\t\t\t\tclock-names = \"aclk\", \"ipg\";\n-\n-\t\t\t\tsec_jr0: jr@1000 {\n-\t\t\t\t\tcompatible = \"fsl,sec-v4.0-job-ring\";\n-\t\t\t\t\treg = <0x1000 0x1000>;\n-\t\t\t\t\tinterrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\t\tstatus = \"disabled\";\n-\t\t\t\t};\n-\n-\t\t\t\tsec_jr1: jr@2000 {\n-\t\t\t\t\tcompatible = \"fsl,sec-v4.0-job-ring\";\n-\t\t\t\t\treg = <0x2000 0x1000>;\n-\t\t\t\t\tinterrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\t};\n-\n-\t\t\t\tsec_jr2: jr@3000 {\n-\t\t\t\t\tcompatible = \"fsl,sec-v4.0-job-ring\";\n-\t\t\t\t\treg = <0x3000 0x1000>;\n-\t\t\t\t\tinterrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\t};\n-\t\t\t};\n-\n-\t\t\tmipi_dsi: mipi-dsi@30a00000 {\n-\t\t\t\tcompatible = \"fsl,imx8mq-nwl-dsi\";\n-\t\t\t\treg = <0x30a00000 0x300>;\n-\t\t\t\tclocks = <&clk IMX8MQ_CLK_DSI_CORE>,\n-\t\t\t\t\t <&clk IMX8MQ_CLK_DSI_AHB>,\n-\t\t\t\t\t <&clk IMX8MQ_CLK_DSI_IPG_DIV>,\n-\t\t\t\t\t <&clk IMX8MQ_CLK_DSI_PHY_REF>,\n-\t\t\t\t\t <&clk IMX8MQ_CLK_LCDIF_PIXEL>;\n-\t\t\t\tclock-names = \"core\", \"rx_esc\", \"tx_esc\", \"phy_ref\", \"lcdif\";\n-\t\t\t\tassigned-clocks = <&clk IMX8MQ_CLK_DSI_AHB>,\n-\t\t\t\t\t\t  <&clk IMX8MQ_CLK_DSI_CORE>,\n-\t\t\t\t\t\t  <&clk IMX8MQ_CLK_DSI_IPG_DIV>;\n-\t\t\t\tassigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>,\n-\t\t\t\t\t\t\t <&clk IMX8MQ_SYS1_PLL_266M>;\n-\t\t\t\tassigned-clock-rates = <80000000>, <266000000>, <20000000>;\n-\t\t\t\tinterrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\tmux-controls = <&mux 0>;\n-\t\t\t\tpower-domains = <&pgc_mipi>;\n-\t\t\t\tphys = <&dphy>;\n-\t\t\t\tphy-names = \"dphy\";\n-\t\t\t\tresets = <&src IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N>,\n-\t\t\t\t\t <&src IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N>,\n-\t\t\t\t\t <&src IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N>,\n-\t\t\t\t\t <&src IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N>;\n-\t\t\t\treset-names = \"byte\", \"dpi\", \"esc\", \"pclk\";\n-\t\t\t\tstatus = \"disabled\";\n-\n-\t\t\t\tports {\n-\t\t\t\t\t#address-cells = <1>;\n-\t\t\t\t\t#size-cells = <0>;\n-\n-\t\t\t\t\tport@0 {\n-\t\t\t\t\t\treg = <0>;\n-\t\t\t\t\t\t#address-cells = <1>;\n-\t\t\t\t\t\t#size-cells = <0>;\n-\t\t\t\t\t\tmipi_dsi_lcdif_in: endpoint@0 {\n-\t\t\t\t\t\t\treg = <0>;\n-\t\t\t\t\t\t\tremote-endpoint = <&lcdif_mipi_dsi>;\n-\t\t\t\t\t\t};\n-\t\t\t\t\t};\n-\t\t\t\t};\n-\t\t\t};\n-\n-\t\t\tdphy: dphy@30a00300 {\n-\t\t\t\tcompatible = \"fsl,imx8mq-mipi-dphy\";\n-\t\t\t\treg = <0x30a00300 0x100>;\n-\t\t\t\tclocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;\n-\t\t\t\tclock-names = \"phy_ref\";\n-\t\t\t\tassigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,\n-\t\t\t\t\t\t  <&clk IMX8MQ_VIDEO_PLL1_BYPASS>,\n-\t\t\t\t\t\t  <&clk IMX8MQ_CLK_DSI_PHY_REF>,\n-\t\t\t\t\t\t  <&clk IMX8MQ_VIDEO_PLL1>;\n-\t\t\t\tassigned-clock-parents = <&clk IMX8MQ_CLK_25M>,\n-\t\t\t\t\t\t  <&clk IMX8MQ_VIDEO_PLL1>,\n-\t\t\t\t\t\t  <&clk IMX8MQ_VIDEO_PLL1_OUT>;\n-\t\t\t\tassigned-clock-rates = <0>, <0>, <24000000>, <594000000>;\n-\t\t\t\t#phy-cells = <0>;\n-\t\t\t\tpower-domains = <&pgc_mipi>;\n-\t\t\t\tstatus = \"disabled\";\n-\t\t\t};\n-\n-\t\t\ti2c1: i2c@30a20000 {\n-\t\t\t\tcompatible = \"fsl,imx8mq-i2c\", \"fsl,imx21-i2c\";\n-\t\t\t\treg = <0x30a20000 0x10000>;\n-\t\t\t\tinterrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\tclocks = <&clk IMX8MQ_CLK_I2C1_ROOT>;\n-\t\t\t\t#address-cells = <1>;\n-\t\t\t\t#size-cells = <0>;\n-\t\t\t\tstatus = \"disabled\";\n-\t\t\t};\n-\n-\t\t\ti2c2: i2c@30a30000 {\n-\t\t\t\tcompatible = \"fsl,imx8mq-i2c\", \"fsl,imx21-i2c\";\n-\t\t\t\treg = <0x30a30000 0x10000>;\n-\t\t\t\tinterrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\tclocks = <&clk IMX8MQ_CLK_I2C2_ROOT>;\n-\t\t\t\t#address-cells = <1>;\n-\t\t\t\t#size-cells = <0>;\n-\t\t\t\tstatus = \"disabled\";\n-\t\t\t};\n-\n-\t\t\ti2c3: i2c@30a40000 {\n-\t\t\t\tcompatible = \"fsl,imx8mq-i2c\", \"fsl,imx21-i2c\";\n-\t\t\t\treg = <0x30a40000 0x10000>;\n-\t\t\t\tinterrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\tclocks = <&clk IMX8MQ_CLK_I2C3_ROOT>;\n-\t\t\t\t#address-cells = <1>;\n-\t\t\t\t#size-cells = <0>;\n-\t\t\t\tstatus = \"disabled\";\n-\t\t\t};\n-\n-\t\t\ti2c4: i2c@30a50000 {\n-\t\t\t\tcompatible = \"fsl,imx8mq-i2c\", \"fsl,imx21-i2c\";\n-\t\t\t\treg = <0x30a50000 0x10000>;\n-\t\t\t\tinterrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\tclocks = <&clk IMX8MQ_CLK_I2C4_ROOT>;\n-\t\t\t\t#address-cells = <1>;\n-\t\t\t\t#size-cells = <0>;\n-\t\t\t\tstatus = \"disabled\";\n-\t\t\t};\n-\n-\t\t\tuart4: serial@30a60000 {\n-\t\t\t\tcompatible = \"fsl,imx8mq-uart\",\n-\t\t\t\t             \"fsl,imx6q-uart\";\n-\t\t\t\treg = <0x30a60000 0x10000>;\n-\t\t\t\tinterrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\tclocks = <&clk IMX8MQ_CLK_UART4_ROOT>,\n-\t\t\t\t         <&clk IMX8MQ_CLK_UART4_ROOT>;\n-\t\t\t\tclock-names = \"ipg\", \"per\";\n-\t\t\t\tstatus = \"disabled\";\n-\t\t\t};\n-\n-\t\t\tmipi_csi1: csi@30a70000 {\n-\t\t\t\tcompatible = \"fsl,imx8mq-mipi-csi2\";\n-\t\t\t\treg = <0x30a70000 0x1000>;\n-\t\t\t\tclocks = <&clk IMX8MQ_CLK_CSI1_CORE>,\n-\t\t\t\t   <&clk IMX8MQ_CLK_CSI1_ESC>,\n-\t\t\t\t   <&clk IMX8MQ_CLK_CSI1_PHY_REF>;\n-\t\t\t\tclock-names = \"core\", \"esc\", \"ui\";\n-\t\t\t\tassigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE>,\n-\t\t\t\t    <&clk IMX8MQ_CLK_CSI1_PHY_REF>,\n-\t\t\t\t    <&clk IMX8MQ_CLK_CSI1_ESC>;\n-\t\t\t\tassigned-clock-rates = <266000000>, <333000000>, <66000000>;\n-\t\t\t\tassigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,\n-\t\t\t\t\t<&clk IMX8MQ_SYS2_PLL_1000M>,\n-\t\t\t\t\t<&clk IMX8MQ_SYS1_PLL_800M>;\n-\t\t\t\tpower-domains = <&pgc_mipi_csi1>;\n-\t\t\t\tresets = <&src IMX8MQ_RESET_MIPI_CSI1_CORE_RESET>,\n-\t\t\t\t\t <&src IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET>,\n-\t\t\t\t\t <&src IMX8MQ_RESET_MIPI_CSI1_ESC_RESET>;\n-\t\t\t\tfsl,mipi-phy-gpr = <&iomuxc_gpr 0x88>;\n-\t\t\t\tinterconnects = <&noc IMX8MQ_ICM_CSI1 &noc IMX8MQ_ICS_DRAM>;\n-\t\t\t\tinterconnect-names = \"dram\";\n-\t\t\t\tstatus = \"disabled\";\n-\n-\t\t\t\tports {\n-\t\t\t\t\t#address-cells = <1>;\n-\t\t\t\t\t#size-cells = <0>;\n-\n-\t\t\t\t\tport@1 {\n-\t\t\t\t\t\treg = <1>;\n-\n-\t\t\t\t\t\tcsi1_mipi_ep: endpoint {\n-\t\t\t\t\t\t\tremote-endpoint = <&csi1_ep>;\n-\t\t\t\t\t\t};\n-\t\t\t\t\t};\n-\t\t\t\t};\n-\t\t\t};\n-\n-\t\t\tcsi1: csi@30a90000 {\n-\t\t\t\tcompatible = \"fsl,imx8mq-csi\", \"fsl,imx7-csi\";\n-\t\t\t\treg = <0x30a90000 0x10000>;\n-\t\t\t\tinterrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\tclocks = <&clk IMX8MQ_CLK_CSI1_ROOT>;\n-\t\t\t\tclock-names = \"mclk\";\n-\t\t\t\tstatus = \"disabled\";\n-\n-\t\t\t\tport {\n-\t\t\t\t\tcsi1_ep: endpoint {\n-\t\t\t\t\t\tremote-endpoint = <&csi1_mipi_ep>;\n-\t\t\t\t\t};\n-\t\t\t\t};\n-\t\t\t};\n-\n-\t\t\tmipi_csi2: csi@30b60000 {\n-\t\t\t\tcompatible = \"fsl,imx8mq-mipi-csi2\";\n-\t\t\t\treg = <0x30b60000 0x1000>;\n-\t\t\t\tclocks = <&clk IMX8MQ_CLK_CSI2_CORE>,\n-\t\t\t\t   <&clk IMX8MQ_CLK_CSI2_ESC>,\n-\t\t\t\t   <&clk IMX8MQ_CLK_CSI2_PHY_REF>;\n-\t\t\t\tclock-names = \"core\", \"esc\", \"ui\";\n-\t\t\t\tassigned-clocks = <&clk IMX8MQ_CLK_CSI2_CORE>,\n-\t\t\t\t    <&clk IMX8MQ_CLK_CSI2_PHY_REF>,\n-\t\t\t\t    <&clk IMX8MQ_CLK_CSI2_ESC>;\n-\t\t\t\tassigned-clock-rates = <266000000>, <333000000>, <66000000>;\n-\t\t\t\tassigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,\n-\t\t\t\t\t<&clk IMX8MQ_SYS2_PLL_1000M>,\n-\t\t\t\t\t<&clk IMX8MQ_SYS1_PLL_800M>;\n-\t\t\t\tpower-domains = <&pgc_mipi_csi2>;\n-\t\t\t\tresets = <&src IMX8MQ_RESET_MIPI_CSI2_CORE_RESET>,\n-\t\t\t\t\t <&src IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET>,\n-\t\t\t\t\t <&src IMX8MQ_RESET_MIPI_CSI2_ESC_RESET>;\n-\t\t\t\tfsl,mipi-phy-gpr = <&iomuxc_gpr 0xa4>;\n-\t\t\t\tinterconnects = <&noc IMX8MQ_ICM_CSI2 &noc IMX8MQ_ICS_DRAM>;\n-\t\t\t\tinterconnect-names = \"dram\";\n-\t\t\t\tstatus = \"disabled\";\n-\n-\t\t\t\tports {\n-\t\t\t\t\t#address-cells = <1>;\n-\t\t\t\t\t#size-cells = <0>;\n-\n-\t\t\t\t\tport@1 {\n-\t\t\t\t\t\treg = <1>;\n-\n-\t\t\t\t\t\tcsi2_mipi_ep: endpoint {\n-\t\t\t\t\t\t\tremote-endpoint = <&csi2_ep>;\n-\t\t\t\t\t\t};\n-\t\t\t\t\t};\n-\t\t\t\t};\n-\t\t\t};\n-\n-\t\t\tcsi2: csi@30b80000 {\n-\t\t\t\tcompatible = \"fsl,imx8mq-csi\", \"fsl,imx7-csi\";\n-\t\t\t\treg = <0x30b80000 0x10000>;\n-\t\t\t\tinterrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\tclocks = <&clk IMX8MQ_CLK_CSI2_ROOT>;\n-\t\t\t\tclock-names = \"mclk\";\n-\t\t\t\tstatus = \"disabled\";\n-\n-\t\t\t\tport {\n-\t\t\t\t\tcsi2_ep: endpoint {\n-\t\t\t\t\t\tremote-endpoint = <&csi2_mipi_ep>;\n-\t\t\t\t\t};\n-\t\t\t\t};\n-\t\t\t};\n-\n-\t\t\tmu: mailbox@30aa0000 {\n-\t\t\t\tcompatible = \"fsl,imx8mq-mu\", \"fsl,imx6sx-mu\";\n-\t\t\t\treg = <0x30aa0000 0x10000>;\n-\t\t\t\tinterrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\tclocks = <&clk IMX8MQ_CLK_MU_ROOT>;\n-\t\t\t\t#mbox-cells = <2>;\n-\t\t\t};\n-\n-\t\t\tusdhc1: mmc@30b40000 {\n-\t\t\t\tcompatible = \"fsl,imx8mq-usdhc\",\n-\t\t\t\t             \"fsl,imx7d-usdhc\";\n-\t\t\t\treg = <0x30b40000 0x10000>;\n-\t\t\t\tinterrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\tclocks = <&clk IMX8MQ_CLK_IPG_ROOT>,\n-\t\t\t\t         <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,\n-\t\t\t\t         <&clk IMX8MQ_CLK_USDHC1_ROOT>;\n-\t\t\t\tclock-names = \"ipg\", \"ahb\", \"per\";\n-\t\t\t\tfsl,tuning-start-tap = <20>;\n-\t\t\t\tfsl,tuning-step = <2>;\n-\t\t\t\tbus-width = <4>;\n-\t\t\t\tstatus = \"disabled\";\n-\t\t\t};\n-\n-\t\t\tusdhc2: mmc@30b50000 {\n-\t\t\t\tcompatible = \"fsl,imx8mq-usdhc\",\n-\t\t\t\t             \"fsl,imx7d-usdhc\";\n-\t\t\t\treg = <0x30b50000 0x10000>;\n-\t\t\t\tinterrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\tclocks = <&clk IMX8MQ_CLK_IPG_ROOT>,\n-\t\t\t\t         <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,\n-\t\t\t\t         <&clk IMX8MQ_CLK_USDHC2_ROOT>;\n-\t\t\t\tclock-names = \"ipg\", \"ahb\", \"per\";\n-\t\t\t\tfsl,tuning-start-tap = <20>;\n-\t\t\t\tfsl,tuning-step = <2>;\n-\t\t\t\tbus-width = <4>;\n-\t\t\t\tstatus = \"disabled\";\n-\t\t\t};\n-\n-\t\t\tqspi0: spi@30bb0000 {\n-\t\t\t\t#address-cells = <1>;\n-\t\t\t\t#size-cells = <0>;\n-\t\t\t\tcompatible = \"fsl,imx8mq-qspi\", \"fsl,imx7d-qspi\";\n-\t\t\t\treg = <0x30bb0000 0x10000>,\n-\t\t\t\t      <0x08000000 0x10000000>;\n-\t\t\t\treg-names = \"QuadSPI\", \"QuadSPI-memory\";\n-\t\t\t\tinterrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\tclocks = <&clk IMX8MQ_CLK_QSPI_ROOT>,\n-\t\t\t\t\t <&clk IMX8MQ_CLK_QSPI_ROOT>;\n-\t\t\t\tclock-names = \"qspi_en\", \"qspi\";\n-\t\t\t\tstatus = \"disabled\";\n-\t\t\t};\n-\n-\t\t\tsdma1: dma-controller@30bd0000 {\n-\t\t\t\tcompatible = \"fsl,imx8mq-sdma\",\"fsl,imx7d-sdma\";\n-\t\t\t\treg = <0x30bd0000 0x10000>;\n-\t\t\t\tinterrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\tclocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>,\n-\t\t\t\t\t <&clk IMX8MQ_CLK_AHB>;\n-\t\t\t\tclock-names = \"ipg\", \"ahb\";\n-\t\t\t\t#dma-cells = <3>;\n-\t\t\t\tfsl,sdma-ram-script-name = \"imx/sdma/sdma-imx7d.bin\";\n-\t\t\t};\n-\n-\t\t\tfec1: ethernet@30be0000 {\n-\t\t\t\tcompatible = \"fsl,imx8mq-fec\", \"fsl,imx6sx-fec\";\n-\t\t\t\treg = <0x30be0000 0x10000>;\n-\t\t\t\tinterrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t\t             <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t\t\t     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t\t\t     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\tclocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,\n-\t\t\t\t         <&clk IMX8MQ_CLK_ENET1_ROOT>,\n-\t\t\t\t         <&clk IMX8MQ_CLK_ENET_TIMER>,\n-\t\t\t\t         <&clk IMX8MQ_CLK_ENET_REF>,\n-\t\t\t\t         <&clk IMX8MQ_CLK_ENET_PHY_REF>;\n-\t\t\t\tclock-names = \"ipg\", \"ahb\", \"ptp\",\n-\t\t\t\t              \"enet_clk_ref\", \"enet_out\";\n-\t\t\t\tassigned-clocks = <&clk IMX8MQ_CLK_ENET_AXI>,\n-\t\t\t\t\t\t  <&clk IMX8MQ_CLK_ENET_TIMER>,\n-\t\t\t\t\t\t  <&clk IMX8MQ_CLK_ENET_REF>,\n-\t\t\t\t\t\t  <&clk IMX8MQ_CLK_ENET_PHY_REF>;\n-\t\t\t\tassigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,\n-\t\t\t\t\t\t\t <&clk IMX8MQ_SYS2_PLL_100M>,\n-\t\t\t\t\t\t\t <&clk IMX8MQ_SYS2_PLL_125M>,\n-\t\t\t\t\t\t\t <&clk IMX8MQ_SYS2_PLL_50M>;\n-\t\t\t\tassigned-clock-rates = <0>, <100000000>, <125000000>, <0>;\n-\t\t\t\tfsl,num-tx-queues = <3>;\n-\t\t\t\tfsl,num-rx-queues = <3>;\n-\t\t\t\tnvmem-cells = <&fec_mac_address>;\n-\t\t\t\tnvmem-cell-names = \"mac-address\";\n-\t\t\t\tfsl,stop-mode = <&iomuxc_gpr 0x10 3>;\n-\t\t\t\tstatus = \"disabled\";\n-\t\t\t};\n-\t\t};\n-\n-\t\tnoc: interconnect@32700000 {\n-\t\t\tcompatible = \"fsl,imx8mq-noc\", \"fsl,imx8m-noc\";\n-\t\t\treg = <0x32700000 0x100000>;\n-\t\t\tclocks = <&clk IMX8MQ_CLK_NOC>;\n-\t\t\tfsl,ddrc = <&ddrc>;\n-\t\t\t#interconnect-cells = <1>;\n-\t\t\toperating-points-v2 = <&noc_opp_table>;\n-\n-\t\t\tnoc_opp_table: opp-table {\n-\t\t\t\tcompatible = \"operating-points-v2\";\n-\n-\t\t\t\topp-133M {\n-\t\t\t\t\topp-hz = /bits/ 64 <133333333>;\n-\t\t\t\t};\n-\n-\t\t\t\topp-400M {\n-\t\t\t\t\topp-hz = /bits/ 64 <400000000>;\n-\t\t\t\t};\n-\n-\t\t\t\topp-800M {\n-\t\t\t\t\topp-hz = /bits/ 64 <800000000>;\n-\t\t\t\t};\n-\t\t\t};\n-\t\t};\n-\n-\t\taips4: bus@32c00000 { /* AIPS4 */\n-\t\t\tcompatible = \"fsl,aips-bus\", \"simple-bus\";\n-\t\t\treg = <0x32c00000 0x400000>;\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <1>;\n-\t\t\tranges = <0x32c00000 0x32c00000 0x400000>;\n-\n-\t\t\tirqsteer: interrupt-controller@32e2d000 {\n-\t\t\t\tcompatible = \"fsl,imx8m-irqsteer\", \"fsl,imx-irqsteer\";\n-\t\t\t\treg = <0x32e2d000 0x1000>;\n-\t\t\t\tinterrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\tclocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>;\n-\t\t\t\tclock-names = \"ipg\";\n-\t\t\t\tfsl,channel = <0>;\n-\t\t\t\tfsl,num-irqs = <64>;\n-\t\t\t\tinterrupt-controller;\n-\t\t\t\t#interrupt-cells = <1>;\n-\t\t\t};\n-\t\t};\n-\n-\t\tgpu: gpu@38000000 {\n-\t\t\tcompatible = \"vivante,gc\";\n-\t\t\treg = <0x38000000 0x40000>;\n-\t\t\tinterrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\tclocks = <&clk IMX8MQ_CLK_GPU_ROOT>,\n-\t\t\t         <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,\n-\t\t\t         <&clk IMX8MQ_CLK_GPU_AXI>,\n-\t\t\t         <&clk IMX8MQ_CLK_GPU_AHB>;\n-\t\t\tclock-names = \"core\", \"shader\", \"bus\", \"reg\";\n-\t\t\t#cooling-cells = <2>;\n-\t\t\tassigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>,\n-\t\t\t                  <&clk IMX8MQ_CLK_GPU_SHADER_SRC>,\n-\t\t\t                  <&clk IMX8MQ_CLK_GPU_AXI>,\n-\t\t\t                  <&clk IMX8MQ_CLK_GPU_AHB>,\n-\t\t\t                  <&clk IMX8MQ_GPU_PLL_BYPASS>;\n-\t\t\tassigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>,\n-\t\t\t                         <&clk IMX8MQ_GPU_PLL_OUT>,\n-\t\t\t                         <&clk IMX8MQ_GPU_PLL_OUT>,\n-\t\t\t                         <&clk IMX8MQ_GPU_PLL_OUT>,\n-\t\t\t                         <&clk IMX8MQ_GPU_PLL>;\n-\t\t\tassigned-clock-rates = <800000000>, <800000000>,\n-\t\t\t                       <800000000>, <800000000>, <0>;\n-\t\t\tpower-domains = <&pgc_gpu>;\n-\t\t};\n-\n-\t\tusb_dwc3_0: usb@38100000 {\n-\t\t\tcompatible = \"fsl,imx8mq-dwc3\", \"snps,dwc3\";\n-\t\t\treg = <0x38100000 0x10000>;\n-\t\t\tclocks = <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>,\n-\t\t\t         <&clk IMX8MQ_CLK_USB_CORE_REF>,\n-\t\t\t\t <&clk IMX8MQ_CLK_32K>;\n-\t\t\tclock-names = \"bus_early\", \"ref\", \"suspend\";\n-\t\t\tassigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,\n-\t\t\t                  <&clk IMX8MQ_CLK_USB_CORE_REF>;\n-\t\t\tassigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,\n-\t\t\t                         <&clk IMX8MQ_SYS1_PLL_100M>;\n-\t\t\tassigned-clock-rates = <500000000>, <100000000>;\n-\t\t\tinterrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\tphys = <&usb3_phy0>, <&usb3_phy0>;\n-\t\t\tphy-names = \"usb2-phy\", \"usb3-phy\";\n-\t\t\tpower-domains = <&pgc_otg1>;\n-\t\t\tusb3-resume-missing-cas;\n-\t\t\tstatus = \"disabled\";\n-\t\t};\n-\n-\t\tusb3_phy0: usb-phy@381f0040 {\n-\t\t\tcompatible = \"fsl,imx8mq-usb-phy\";\n-\t\t\treg = <0x381f0040 0x40>;\n-\t\t\tclocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>;\n-\t\t\tclock-names = \"phy\";\n-\t\t\tassigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;\n-\t\t\tassigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;\n-\t\t\tassigned-clock-rates = <100000000>;\n-\t\t\t#phy-cells = <0>;\n-\t\t\tstatus = \"disabled\";\n-\t\t};\n-\n-\t\tusb_dwc3_1: usb@38200000 {\n-\t\t\tcompatible = \"fsl,imx8mq-dwc3\", \"snps,dwc3\";\n-\t\t\treg = <0x38200000 0x10000>;\n-\t\t\tclocks = <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>,\n-\t\t\t         <&clk IMX8MQ_CLK_USB_CORE_REF>,\n-\t\t\t\t <&clk IMX8MQ_CLK_32K>;\n-\t\t\tclock-names = \"bus_early\", \"ref\", \"suspend\";\n-\t\t\tassigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,\n-\t\t\t                  <&clk IMX8MQ_CLK_USB_CORE_REF>;\n-\t\t\tassigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,\n-\t\t\t                         <&clk IMX8MQ_SYS1_PLL_100M>;\n-\t\t\tassigned-clock-rates = <500000000>, <100000000>;\n-\t\t\tinterrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\tphys = <&usb3_phy1>, <&usb3_phy1>;\n-\t\t\tphy-names = \"usb2-phy\", \"usb3-phy\";\n-\t\t\tpower-domains = <&pgc_otg2>;\n-\t\t\tusb3-resume-missing-cas;\n-\t\t\tstatus = \"disabled\";\n-\t\t};\n-\n-\t\tusb3_phy1: usb-phy@382f0040 {\n-\t\t\tcompatible = \"fsl,imx8mq-usb-phy\";\n-\t\t\treg = <0x382f0040 0x40>;\n-\t\t\tclocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>;\n-\t\t\tclock-names = \"phy\";\n-\t\t\tassigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;\n-\t\t\tassigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;\n-\t\t\tassigned-clock-rates = <100000000>;\n-\t\t\t#phy-cells = <0>;\n-\t\t\tstatus = \"disabled\";\n-\t\t};\n-\n-\t\tvpu_g1: video-codec@38300000 {\n-\t\t\tcompatible = \"nxp,imx8mq-vpu-g1\";\n-\t\t\treg = <0x38300000 0x10000>;\n-\t\t\tinterrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\tclocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>;\n-\t\t\tpower-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>;\n-\t\t};\n-\n-\t\tvpu_g2: video-codec@38310000 {\n-\t\t\tcompatible = \"nxp,imx8mq-vpu-g2\";\n-\t\t\treg = <0x38310000 0x10000>;\n-\t\t\tinterrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\tclocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>;\n-\t\t\tpower-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>;\n-\t\t};\n-\n-\t\tvpu_blk_ctrl: blk-ctrl@38320000 {\n-\t\t\tcompatible = \"fsl,imx8mq-vpu-blk-ctrl\";\n-\t\t\treg = <0x38320000 0x100>;\n-\t\t\tpower-domains = <&pgc_vpu>, <&pgc_vpu>, <&pgc_vpu>;\n-\t\t\tpower-domain-names = \"bus\", \"g1\", \"g2\";\n-\t\t\tclocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,\n-\t\t\t\t <&clk IMX8MQ_CLK_VPU_G2_ROOT>;\n-\t\t\tclock-names = \"g1\", \"g2\";\n-\t\t\t#power-domain-cells = <1>;\n-\t\t};\n-\n-\t\tpcie0: pcie@33800000 {\n-\t\t\tcompatible = \"fsl,imx8mq-pcie\";\n-\t\t\treg = <0x33800000 0x400000>,\n-\t\t\t      <0x1ff00000 0x80000>;\n-\t\t\treg-names = \"dbi\", \"config\";\n-\t\t\t#address-cells = <3>;\n-\t\t\t#size-cells = <2>;\n-\t\t\tdevice_type = \"pci\";\n-\t\t\tbus-range = <0x00 0xff>;\n-\t\t\tranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */\n-\t\t\t\t <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */\n-\t\t\tnum-lanes = <1>;\n-\t\t\tinterrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\tinterrupt-names = \"msi\";\n-\t\t\t#interrupt-cells = <1>;\n-\t\t\tinterrupt-map-mask = <0 0 0 0x7>;\n-\t\t\tinterrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t                <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t                <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t                <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\tfsl,max-link-speed = <2>;\n-\t\t\tlinux,pci-domain = <0>;\n-\t\t\tpower-domains = <&pgc_pcie>;\n-\t\t\tresets = <&src IMX8MQ_RESET_PCIEPHY>,\n-\t\t\t         <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,\n-\t\t\t         <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;\n-\t\t\treset-names = \"pciephy\", \"apps\", \"turnoff\";\n-\t\t\tassigned-clocks = <&clk IMX8MQ_CLK_PCIE1_CTRL>,\n-\t\t\t                  <&clk IMX8MQ_CLK_PCIE1_PHY>,\n-\t\t\t                  <&clk IMX8MQ_CLK_PCIE1_AUX>;\n-\t\t\tassigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>,\n-\t\t\t                         <&clk IMX8MQ_SYS2_PLL_100M>,\n-\t\t\t                         <&clk IMX8MQ_SYS1_PLL_80M>;\n-\t\t\tassigned-clock-rates = <250000000>, <100000000>,\n-\t\t\t                       <10000000>;\n-\t\t\tstatus = \"disabled\";\n-\t\t};\n-\n-\t\tpcie1: pcie@33c00000 {\n-\t\t\tcompatible = \"fsl,imx8mq-pcie\";\n-\t\t\treg = <0x33c00000 0x400000>,\n-\t\t\t      <0x27f00000 0x80000>;\n-\t\t\treg-names = \"dbi\", \"config\";\n-\t\t\t#address-cells = <3>;\n-\t\t\t#size-cells = <2>;\n-\t\t\tdevice_type = \"pci\";\n-\t\t\tranges =  <0x81000000 0 0x00000000 0x27f80000 0 0x00010000>, /* downstream I/O 64KB */\n-\t\t\t\t  <0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */\n-\t\t\tnum-lanes = <1>;\n-\t\t\tinterrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\tinterrupt-names = \"msi\";\n-\t\t\t#interrupt-cells = <1>;\n-\t\t\tinterrupt-map-mask = <0 0 0 0x7>;\n-\t\t\tinterrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t\t\t<0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t\t\t<0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t\t\t<0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\tfsl,max-link-speed = <2>;\n-\t\t\tlinux,pci-domain = <1>;\n-\t\t\tpower-domains = <&pgc_pcie>;\n-\t\t\tresets = <&src IMX8MQ_RESET_PCIEPHY2>,\n-\t\t\t         <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>,\n-\t\t\t         <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>;\n-\t\t\treset-names = \"pciephy\", \"apps\", \"turnoff\";\n-\t\t\tassigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>,\n-\t\t\t                  <&clk IMX8MQ_CLK_PCIE2_PHY>,\n-\t\t\t                  <&clk IMX8MQ_CLK_PCIE2_AUX>;\n-\t\t\tassigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>,\n-\t\t\t                         <&clk IMX8MQ_SYS2_PLL_100M>,\n-\t\t\t                         <&clk IMX8MQ_SYS1_PLL_80M>;\n-\t\t\tassigned-clock-rates = <250000000>, <100000000>,\n-\t\t\t                       <10000000>;\n-\t\t\tstatus = \"disabled\";\n-\t\t};\n-\n-\t\tgic: interrupt-controller@38800000 {\n-\t\t\tcompatible = \"arm,gic-v3\";\n-\t\t\treg = <0x38800000 0x10000>,\t/* GIC Dist */\n-\t\t\t      <0x38880000 0xc0000>,\t/* GICR */\n-\t\t\t      <0x31000000 0x2000>,\t/* GICC */\n-\t\t\t      <0x31010000 0x2000>,\t/* GICV */\n-\t\t\t      <0x31020000 0x2000>;\t/* GICH */\n-\t\t\t#interrupt-cells = <3>;\n-\t\t\tinterrupt-controller;\n-\t\t\tinterrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\tinterrupt-parent = <&gic>;\n-\t\t};\n-\n-\t\tddrc: memory-controller@3d400000 {\n-\t\t\tcompatible = \"fsl,imx8mq-ddrc\", \"fsl,imx8m-ddrc\";\n-\t\t\treg = <0x3d400000 0x400000>;\n-\t\t\tclock-names = \"core\", \"pll\", \"alt\", \"apb\";\n-\t\t\tclocks = <&clk IMX8MQ_CLK_DRAM_CORE>,\n-\t\t\t\t <&clk IMX8MQ_DRAM_PLL_OUT>,\n-\t\t\t\t <&clk IMX8MQ_CLK_DRAM_ALT>,\n-\t\t\t\t <&clk IMX8MQ_CLK_DRAM_APB>;\n-\t\t\tstatus = \"disabled\";\n-\t\t};\n-\n-\t\tddr-pmu@3d800000 {\n-\t\t\tcompatible = \"fsl,imx8mq-ddr-pmu\", \"fsl,imx8m-ddr-pmu\";\n-\t\t\treg = <0x3d800000 0x400000>;\n-\t\t\tinterrupt-parent = <&gic>;\n-\t\t\tinterrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t};\n-\t};\n-};\n","prefixes":["06/13"]}