{"id":2228187,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2228187/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20260425-imx8m-of-upstream-v1-7-07527be92e5d@nxp.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.1/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260425-imx8m-of-upstream-v1-7-07527be92e5d@nxp.com>","date":"2026-04-25T00:36:59","name":"[07/13] imx8mm: mx8menlo: Switch OF_UPSTREAM","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"aeb0dc742900314f029a92ac64fab782322d09b5","submitter":{"id":80723,"url":"http://patchwork.ozlabs.org/api/1.1/people/80723/?format=json","name":"Peng Fan (OSS)","email":"peng.fan@oss.nxp.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20260425-imx8m-of-upstream-v1-7-07527be92e5d@nxp.com/mbox/","series":[{"id":501451,"url":"http://patchwork.ozlabs.org/api/1.1/series/501451/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=501451","date":"2026-04-25T00:37:04","name":"iMX8M: Covert to OF_UPSTREAM","version":1,"mbox":"http://patchwork.ozlabs.org/series/501451/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2228187/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2228187/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com\n header.a=rsa-sha256 header.s=selector1-NXP1-onmicrosoft-com\n header.b=PkjFHu4o;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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phobos.denx.de","X-Virus-Status":"Clean"},"content":"From: Peng Fan \n\narch/arm/dts/imx8mm-mx8menlo.dts is almost same as upstream Linux dts,\nso switch to OF_UPSTREAM by dropping the U-Boot copy of the dts,\nenabling OF_UPSTREAM and updating CONFIG_DEFAULT_DEVICE_TREE.\n\nSigned-off-by: Peng Fan \n---\n arch/arm/dts/Makefile | 1 -\n arch/arm/dts/imx8mm-mx8menlo.dts | 335 --------------------------------------\n arch/arm/mach-imx/imx8m/Kconfig | 1 +\n configs/imx8mm-mx8menlo_defconfig | 2 +-\n 4 files changed, 2 insertions(+), 337 deletions(-)","diff":"diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile\nindex c4360390984..dff05dd5888 100644\n--- a/arch/arm/dts/Makefile\n+++ b/arch/arm/dts/Makefile\n@@ -876,7 +876,6 @@ dtb-$(CONFIG_ARCH_IMX8M) += \\\n \timx8mm-data-modul-edm-sbc.dtb \\\n \timx8mm-icore-mx8mm-ctouch2.dtb \\\n \timx8mm-icore-mx8mm-edimm2.2.dtb \\\n-\timx8mm-mx8menlo.dtb \\\n \timx8mm-phg.dtb \\\n \timx8mq-cm.dtb \\\n \timx8mp-data-modul-edm-sbc.dtb \\\ndiff --git a/arch/arm/dts/imx8mm-mx8menlo.dts b/arch/arm/dts/imx8mm-mx8menlo.dts\ndeleted file mode 100644\nindex 0b123a84018..00000000000\n--- a/arch/arm/dts/imx8mm-mx8menlo.dts\n+++ /dev/null\n@@ -1,335 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0+ OR MIT\n-/*\n- * Copyright 2021-2022 Marek Vasut \n- */\n-\n-/dts-v1/;\n-\n-#include \"imx8mm-verdin.dtsi\"\n-\n-/ {\n-\tmodel = \"MENLO MX8MM EMBEDDED DEVICE\";\n-\tcompatible = \"menlo,mx8menlo\",\n-\t\t \"toradex,verdin-imx8mm-nonwifi\",\n-\t\t \"toradex,verdin-imx8mm\",\n-\t\t \"fsl,imx8mm\";\n-\n-\t/delete-node/ gpio-keys;\n-\n-\tleds {\n-\t\tcompatible = \"gpio-leds\";\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pinctrl_led>;\n-\n-\t\tled-1 {\n-\t\t\tlabel = \"TestLed601\";\n-\t\t\tgpios = <&gpio4 18 GPIO_ACTIVE_HIGH>;\n-\t\t\tlinux,default-trigger = \"mmc0\";\n-\t\t};\n-\n-\t\tled-2 {\n-\t\t\tlabel = \"TestLed602\";\n-\t\t\tgpios = <&gpio4 10 GPIO_ACTIVE_HIGH>;\n-\t\t\tlinux,default-trigger = \"heartbeat\";\n-\t\t};\n-\t};\n-\n-\tbeeper {\n-\t\tcompatible = \"gpio-beeper\";\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pinctrl_beeper>;\n-\t\tgpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;\n-\t};\n-\n-\t/* Fixed clock dedicated to SPI CAN on carrier board */\n-\tclk_xtal20: clk-xtal20 {\n-\t\tcompatible = \"fixed-clock\";\n-\t\t#clock-cells = <0>;\n-\t\tclock-frequency = <20000000>;\n-\t};\n-};\n-\n-&ecspi1 {\n-\t#address-cells = <1>;\n-\t#size-cells = <0>;\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_ecspi1>;\n-\tcs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;\n-\tstatus = \"okay\";\n-\n-\t/* CAN controller on the baseboard */\n-\tcanfd: can@0 {\n-\t\tcompatible = \"microchip,mcp2518fd\";\n-\t\tclocks = <&clk_xtal20>;\n-\t\tinterrupt-parent = <&gpio1>;\n-\t\tinterrupts = <8 IRQ_TYPE_EDGE_FALLING>;\n-\t\treg = <0>;\n-\t\tspi-max-frequency = <2000000>;\n-\t};\n-\n-};\n-\n-&ecspi2 {\n-\tpinctrl-0 = <&pinctrl_ecspi2 &pinctrl_gpio1>;\n-\tcs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, <&gpio3 4 GPIO_ACTIVE_LOW>;\n-\tstatus = \"okay\";\n-\n-\tspidev@0 {\n-\t\tcompatible = \"menlo,m53cpld\";\n-\t\treg = <0>;\n-\t\tspi-max-frequency = <25000000>;\n-\t};\n-\n-\tspidev@1 {\n-\t\tcompatible = \"menlo,m53cpld\";\n-\t\treg = <1>;\n-\t\tspi-max-frequency = <25000000>;\n-\t};\n-\n-};\n-\n-ðphy0 {\n-\tmax-speed = <100>;\n-};\n-\n-&fec1 {\n-\tstatus = \"okay\";\n-};\n-\n-&flexspi {\n-\tstatus = \"okay\";\n-\n-\tflash@0 {\n-\t\treg = <0>;\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <1>;\n-\t\tcompatible = \"jedec,spi-nor\";\n-\t\tspi-max-frequency = <66000000>;\n-\t\tspi-rx-bus-width = <4>;\n-\t\tspi-tx-bus-width = <4>;\n-\t};\n-};\n-\n-&gpio1 {\n-\tgpio-line-names =\n-\t\t\"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\";\n-};\n-\n-&gpio2 {\n-\tgpio-line-names =\n-\t\t\"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\";\n-};\n-\n-&gpio3 {\n-\tgpio-line-names =\n-\t\t\"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"DISP_reset\", \"KBD_intI\",\n-\t\t\"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\";\n-};\n-\n-&gpio4 {\n-\t/*\n-\t * CPLD_D[n] is ARM_CPLD[n] in schematic\n-\t * CPLD_int is SA_INTERRUPT in schematic\n-\t * CPLD_reset is RESET_SOFT in schematic\n-\t */\n-\tgpio-line-names =\n-\t\t\"CPLD_D[6]\", \"CPLD_int\", \"CPLD_reset\", \"\",\n-\t\t\"\", \"CPLD_D[7]\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"CPLD_D[5]\",\n-\t\t\"CPLD_D[4]\", \"CPLD_D[3]\", \"CPLD_D[2]\", \"CPLD_D[1]\",\n-\t\t\"CPLD_D[0]\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"KBD_intK\",\n-\t\t\"\", \"\", \"\", \"\";\n-};\n-\n-&gpio5 {\n-\tgpio-line-names =\n-\t\t\"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\";\n-};\n-\n-&gpio_expander_21 {\n-\tstatus = \"okay\";\n-};\n-\n-&hwmon {\n-\tstatus = \"okay\";\n-};\n-\n-&i2c3 {\n-\tstatus = \"okay\";\n-};\n-\n-&i2c4 {\n-\t/* None of this is present on the SoM. */\n-\t/delete-node/ bridge@2c;\n-\t/delete-node/ hdmi@48;\n-\t/delete-node/ touch@4a;\n-\t/delete-node/ sensor@4f;\n-\t/delete-node/ eeprom@50;\n-\t/delete-node/ eeprom@57;\n-};\n-\n-&iomuxc {\n-\tpinctrl-0 = <&pinctrl_gpio7>, <&pinctrl_gpio_hog1>,\n-\t\t <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>;\n-\n-\tpinctrl_beeper: beepergrp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3\t\t\t0x1c4\n-\t\t>;\n-\t};\n-\n-\tpinctrl_ecspi1: ecspi1grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK\t\t0x4\n-\t\t\tMX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI\t\t0x4\n-\t\t\tMX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO\t\t0x1c4\n-\t\t\tMX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9\t\t0x1c4\n-\t\t>;\n-\t};\n-\n-\tpinctrl_led: ledgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18\t\t0x1c4\n-\t\t\tMX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10\t\t0x1c4\n-\t\t>;\n-\t};\n-\n-\tpinctrl_uart4_rts: uart4rtsgrp {\n-\t\tfsl,pins = <\n-\t\t\t/* SODIMM 222 */\n-\t\t\tMX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9\t\t0x184\n-\t\t>;\n-\t};\n-};\n-\n-&pinctrl_gpio1 {\n-\tfsl,pins = <\n-\t\t/* SODIMM 206 */\n-\t\tMX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4\t\t\t0x1c4\n-\t>;\n-};\n-\n-&pinctrl_gpio_hog1 {\n-\tfsl,pins = <\n-\t\t/* SODIMM 88 */\n-\t\tMX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20\t\t\t0x1c4\n-\t\t/* CPLD_int */\n-\t\tMX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1\t\t\t\t0x1c4\n-\t\t/* CPLD_reset */\n-\t\tMX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2\t\t\t0x1c4\n-\t\t/* SODIMM 94 */\n-\t\tMX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3\t\t\t0x1c4\n-\t\t/* SODIMM 96 */\n-\t\tMX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4\t\t\t0x1c4\n-\t\t/* CPLD_D[7] */\n-\t\tMX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5\t\t\t0x184\n-\t\t/* CPLD_D[6] */\n-\t\tMX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0\t\t\t0x184\n-\t\t/* CPLD_D[5] */\n-\t\tMX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11\t\t\t0x184\n-\t\t/* CPLD_D[4] */\n-\t\tMX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12\t\t\t0x184\n-\t\t/* CPLD_D[3] */\n-\t\tMX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13\t\t\t0x184\n-\t\t/* CPLD_D[2] */\n-\t\tMX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14\t\t\t0x184\n-\t\t/* CPLD_D[1] */\n-\t\tMX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15\t\t\t0x184\n-\t\t/* CPLD_D[0] */\n-\t\tMX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16\t\t\t0x184\n-\t\t/* KBD_intK */\n-\t\tMX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27\t\t\t0x1c4\n-\t\t/* DISP_reset */\n-\t\tMX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22\t\t\t0x1c4\n-\t\t/* KBD_intI */\n-\t\tMX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23\t\t\t0x1c4\n-\t\t/* SODIMM 46 */\n-\t\tMX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24\t\t\t0x1c4\n-\t>;\n-};\n-\n-&pinctrl_uart1 {\n-\tfsl,pins = <\n-\t\t/* SODIMM 149 */\n-\t\tMX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX\t\t\t0x1c4\n-\t\t/* SODIMM 147 */\n-\t\tMX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX\t\t\t0x1c4\n-\t\t/* SODIMM 210 */\n-\t\tMX8MM_IOMUXC_UART3_RXD_UART1_DTE_RTS_B\t\t\t0x1c4\n-\t\t/* SODIMM 212 */\n-\t\tMX8MM_IOMUXC_UART3_TXD_UART1_DTE_CTS_B\t\t\t0x1c4\n-\t>;\n-};\n-\n-®_usb_otg1_vbus {\n-\t/delete-property/ enable-active-high;\n-\tgpio = <&gpio1 12 GPIO_ACTIVE_LOW>;\n-};\n-\n-®_usb_otg2_vbus {\n-\t/delete-property/ enable-active-high;\n-\tgpio = <&gpio1 14 GPIO_ACTIVE_LOW>;\n-};\n-\n-&sai2 {\n-\tstatus = \"disabled\";\n-};\n-\n-&uart1 {\n-\tuart-has-rtscts;\n-\tstatus = \"okay\";\n-};\n-\n-&uart2 {\n-\tstatus = \"okay\";\n-};\n-\n-&uart4 {\n-\tpinctrl-0 = <&pinctrl_uart4 &pinctrl_uart4_rts>;\n-\tlinux,rs485-enabled-at-boot-time;\n-\trts-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;\n-\tstatus = \"okay\";\n-};\n-\n-&usbotg1 {\n-\tdr_mode = \"peripheral\";\n-\tstatus = \"okay\";\n-};\n-\n-&usbotg2 {\n-\tdr_mode = \"host\";\n-\tstatus = \"okay\";\n-};\n-\n-&usdhc2 {\n-\tstatus = \"okay\";\n-};\ndiff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig\nindex 0e885f97e63..fbabd17288f 100644\n--- a/arch/arm/mach-imx/imx8m/Kconfig\n+++ b/arch/arm/mach-imx/imx8m/Kconfig\n@@ -132,6 +132,7 @@ config TARGET_IMX8MM_MX8MENLO\n \tselect IMX8MM\n \tselect SUPPORT_SPL\n \tselect IMX8M_LPDDR4\n+\timply OF_UPSTREAM\n \n config TARGET_IMX8MM_PHG\n \tbool \"i.MX8MM PHG board\"\ndiff --git a/configs/imx8mm-mx8menlo_defconfig b/configs/imx8mm-mx8menlo_defconfig\nindex 097425399b3..55614bd946e 100644\n--- a/configs/imx8mm-mx8menlo_defconfig\n+++ b/configs/imx8mm-mx8menlo_defconfig\n@@ -8,7 +8,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y\n CONFIG_ENV_SIZE=0x2000\n CONFIG_ENV_OFFSET=0xFFFFDE00\n CONFIG_DM_GPIO=y\n-CONFIG_DEFAULT_DEVICE_TREE=\"imx8mm-mx8menlo\"\n+CONFIG_DEFAULT_DEVICE_TREE=\"freescale/imx8mm-mx8menlo\"\n CONFIG_TARGET_IMX8MM_MX8MENLO=y\n CONFIG_OF_LIBFDT_OVERLAY=y\n CONFIG_SYS_MONITOR_LEN=524288\n","prefixes":["07/13"]}