{"id":2228158,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2228158/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/patch/3cfc5fbc-1a7b-4260-bef6-877248bf61f4@oss.qualcomm.com/","project":{"id":17,"url":"http://patchwork.ozlabs.org/api/1.1/projects/17/?format=json","name":"GNU Compiler Collection","link_name":"gcc","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<3cfc5fbc-1a7b-4260-bef6-877248bf61f4@oss.qualcomm.com>","date":"2026-04-25T14:33:23","name":"[to-be-committed,RISC-V,PR,target/123838] Improve code generated for shifts with counts 31-N or 63-N","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"dcfffce5a00a6e8f6fe78af103bdb45d6464b447","submitter":{"id":92310,"url":"http://patchwork.ozlabs.org/api/1.1/people/92310/?format=json","name":"Jeffrey Law","email":"jeffrey.law@oss.qualcomm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/gcc/patch/3cfc5fbc-1a7b-4260-bef6-877248bf61f4@oss.qualcomm.com/mbox/","series":[{"id":501441,"url":"http://patchwork.ozlabs.org/api/1.1/series/501441/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/list/?series=501441","date":"2026-04-25T14:33:23","name":"[to-be-committed,RISC-V,PR,target/123838] Improve code generated for shifts with counts 31-N or 63-N","version":1,"mbox":"http://patchwork.ozlabs.org/series/501441/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2228158/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2228158/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=AESHfFeZ;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=UBiWi0vY;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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boundary=\"------------5ABv7JNsLBab0pQWJ0TPUH2S\"","Message-ID":"<3cfc5fbc-1a7b-4260-bef6-877248bf61f4@oss.qualcomm.com>","Date":"Sat, 25 Apr 2026 08:33:23 -0600","MIME-Version":"1.0","User-Agent":"Mozilla Thunderbird","Content-Language":"en-US","From":"Jeffrey Law ","Subject":"[to-be-committed][RISC-V][PR target/123838] Improve code generated\n for shifts with counts 31-N or 63-N","To":"'GCC Patches' ","X-Authority-Analysis":"v=2.4 cv=QNxYgALL c=1 sm=1 tr=0 ts=69ecd0b6 cx=c_pps\n a=JYo30EpNSr/tUYqK9jHPoA==:117 a=asGLMfRmzhnGNxaIYohjRg==:17\n a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=r77TgQKjGQsHNAKrUKIA:9\n a=X-s9Emf64VNPKdGg-DgA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10\n a=06Iw0JyqPAGL7hmUEMMA:9 a=B2y7HmGcmWMA:10 a=Fk4IpSoW4aLDllm1B1p-:22","X-Proofpoint-GUID":"r2tVXaz7Tt3_WZeXO55aXuILndz4Oib1","X-Proofpoint-ORIG-GUID":"r2tVXaz7Tt3_WZeXO55aXuILndz4Oib1","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNDI1MDE0OCBTYWx0ZWRfX02CNEgpzgy4p\n b3GSYaaacmoLXhztLXIPD0Qw6haOrMzLybmiMpesx9BH0/uAGNNuv+HLOVBPftc/slIA3H/it31\n kZ7785tpksN/RxBh01nUiuPJus6tZ4g3+x8CYcEcXvtmB+qCGyiTD/NMb2oljoCz92g9aUySTQD\n cbqD2RGu7cDiheSZwmTapt2EuMKs2et5/E+XqxdBCNbtTtyS0sDfa6pO3WcSievkd2tv9oiWWuh\n aN/adsO06dOfmKNUSgrBnelxAz6RdjAtDmoMQeWqyQYzZsQe4dq3n69BBVXzBJUWFTMbTLuY6JD\n 6JC8T14X2C8FT+0AlZT2OaO3ru76WZxTF7qKxNN034Fz7JjI7t/w6rpKX3GRQ0XJsDJ1CtILez/\n 0+LZX3+AoYIJp0yf1Vsf6Odh2hx4JhhZsRuWmP8JcJ3CH+wI0hGIzwvqnYgoM5n+44eXcRb81MQ\n IWh30L9U0UjYpD0EH8w==","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-25_03,2026-04-21_02,2025-10-01_01","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n impostorscore=0 suspectscore=0 bulkscore=0 phishscore=0 spamscore=0\n adultscore=0 priorityscore=1501 lowpriorityscore=0 malwarescore=0\n clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc=\n route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000\n definitions=main-2604250148","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org"},"content":"A shift count expressed at 31 - n ends up generating code like this:\n\n         li      a5,31\n         subw    a5,a5,a1\n         sllw    a0,a0,a5\n         ret\n\nNote how we had to load 31 into a constant for the subtraction. But \ninstead of using 31 - n we can use a bit-not as it'll do precisely what \nwe need in the bits that the shift instruction actually uses.  This \nresults in:\n\n         not     a1, a1\n         sllw    a0, a0, a1\n         ret\n\n\nThe core idea we're exploiting here is the processor implements \nSHIFT_COUNT_TRUNCATED semantics.  so a SI shift only cares about the low \n5 bits and DI the low 6 bits of the shift count.  And if we think about \nwhat bit pattern -1 would be in those cases we get 31 and 63.  We then \nexploit the identity\n\n-x = ~x + 1  // identity\n-1 - x = ~x  // a tiny bit of algebra\n\nSo in these limited cases we can place the the -1 - x with ~x.\n\nI didn't implement this in simplify-rtx.  It wasn't actually going to \nhelp because while the RISC-V chip implements SHIFT_COUNT_TRUNCATED \nsemantics, it doesn't define SHIFT_COUNT_TRUNCATED for \"reasons\".\n\nSo there's two patterns.  One for an X mode destination, naturally the \nshift count is 31/63 - n for SI/DI respectively.  It's a bit odd that \nthe subtraction is always SImode, but that's probably narrowing \nhappening somewhere.\n\nThe second pattern covers the \"w\" forms for rv64.\n\nThis trick probably works for the zbs instructions as well. That's going \nto be a whole lot more patterns and I haven't seen this idiom show up \nanywhere in practice, so it doesn't seem like a good cost/benefit analysis.\n\nThis spun overnight on riscv32-elf and riscv64-elf and on the Pioneer \nwithout regressions.  I'll wait for pre-commit CI to do its thing before \npushing.\n\njeff\nPR target/123838\ngcc/\n\t* config/riscv/riscv.md: Use splitters to simplify shifts where\n\tthe shift count is 31-N or 63-N.\n\ngcc/testsuite\n\t* gcc.target/riscv/pr123838.c: New test.","diff":"diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md\nindex 7e9205fb24bf..3aa7d5f343b2 100644\n--- a/gcc/config/riscv/riscv.md\n+++ b/gcc/config/riscv/riscv.md\n@@ -4995,6 +4995,48 @@ (define_split\n { operands[3] = GEN_INT (BITS_PER_WORD\n \t\t\t - exact_log2 (INTVAL (operands[3]) + 1)); })\n \n+;; If a shift count is BITS_PER_WORD - 1 - N, then we can exploit the identity\n+;; that -x = ~x + 1 which is equivalent to (-1 - x) = ~x. When shifting only\n+;; low bits of X matter (5 for SI, 6 for DI). So 31/63 are equivalent to -1\n+;; for SI/DI shifts.\n+;;\n+;; Strangely, even for rv64, the shift computation is done in SI, presumably\n+;; something narrowed the arithmetic prior to gimple->rtl expansion.\n+;; Ultimately it gets wrapped with a SUBREG narrowing to QI.\n+(define_split\n+ [(set (match_operand:X 0 \"register_operand\")\n+\t(any_shift_rotate:X\n+\t (match_operand:X 1 \"register_operand\")\n+\t (subreg:QI (minus:SI (match_operand 2 \"bitpos_mask_operand\")\n+\t\t\t (match_operand:SI 3 \"register_operand\")) 0)))\n+ (clobber (match_operand:X 4 \"register_operand\"))]\n+ \"\"\n+ [(set (match_dup 4) (not:X (match_dup 6)))\n+ (set (match_dup 0) (any_shift_rotate:X (match_dup 1) (match_dup 5)))]\n+ { \n+ operands[5] = gen_lowpart (QImode, operands[4]);\n+ operands[6] = gen_lowpart (word_mode, operands[3]);\n+ })\n+\n+;; This is the same thing as the prior pattern, but for 32 bit shifts on rv64.\n+(define_split\n+ [(set (match_operand:DI 0 \"register_operand\")\n+\t(sign_extend:DI\n+\t (any_shift_rotate:SI\n+\t (match_operand:SI 1 \"register_operand\")\n+\t (subreg:QI (minus:SI (const_int 31)\n+\t\t\t (match_operand:SI 2 \"register_operand\") ) 0))))\n+ (clobber (match_operand:DI 3 \"register_operand\"))]\n+ \"TARGET_64BIT\"\n+ [(set (match_dup 3) (not:DI (match_dup 2)))\n+ (set (match_dup 0)\n+\t(sign_extend:DI (any_shift_rotate:SI (match_dup 1)\n+\t\t\t\t\t (match_dup 4))))]\n+ {\n+ operands[2] = gen_lowpart (DImode, operands[2]);\n+ operands[4] = gen_lowpart (QImode, operands[3]);\n+ })\n+\n ;; Standard extensions and pattern for optimization\n (include \"bitmanip.md\")\n (include \"crypto.md\")\ndiff --git a/gcc/testsuite/gcc.target/riscv/pr123838.c b/gcc/testsuite/gcc.target/riscv/pr123838.c\nnew file mode 100644\nindex 000000000000..58a8ea6ea0bb\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/pr123838.c\n@@ -0,0 +1,15 @@\n+/* { dg-do compile } */\n+/* { dg-skip-if \"\" { *-*-* } { \"-O0\" \"-Og\"} } */\n+\n+#define F(NAME, OP, TYPE) TYPE f##NAME##TYPE (TYPE x, TYPE n) { return x OP (sizeof (TYPE) * 8 - 1 - n); }\n+\n+F(RSHIFT, >>, int)\n+F(LSHIFT, <<, int)\n+F(RSHIFT, >>, long)\n+F(LSHIFT, <<, long)\n+\n+/* { dg-final { scan-assembler-times \"not\\t\" 4 } } */\n+/* { dg-final { scan-assembler-not \"li\\t\" } } */\n+/* { dg-final { scan-assembler-not \"sub\\t\" } } */\n+/* { dg-final { scan-assembler-not \"subw\\t\" } } */\n+\n","prefixes":["to-be-committed","RISC-V","PR","target/123838"]}