{"id":2228145,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2228145/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260425131721.932250-13-joel@jms.id.au/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260425131721.932250-13-joel@jms.id.au>","date":"2026-04-25T13:17:18","name":"[v4,12/13] hw/riscv/atlantis: Integrate i2c buses","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"66ba3e6874f10ba0ade85cf22f77ac55ac42b4c3","submitter":{"id":48628,"url":"http://patchwork.ozlabs.org/api/1.1/people/48628/?format=json","name":"Joel Stanley","email":"joel@jms.id.au"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260425131721.932250-13-joel@jms.id.au/mbox/","series":[{"id":501439,"url":"http://patchwork.ozlabs.org/api/1.1/series/501439/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501439","date":"2026-04-25T13:17:08","name":"hw/riscv: Add the Tenstorrent Atlantis machine","version":4,"mbox":"http://patchwork.ozlabs.org/series/501439/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2228145/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2228145/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=nzX0mzp/;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g2r6F0FNwz1xvV\n\tfor ; Sat, 25 Apr 2026 23:20:05 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wGcuy-0007v4-6t; Sat, 25 Apr 2026 09:19:34 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wGcue-0007bt-S8\n for qemu-devel@nongnu.org; Sat, 25 Apr 2026 09:19:16 -0400","from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wGcud-0000MO-3w\n for qemu-devel@nongnu.org; Sat, 25 Apr 2026 09:19:12 -0400","by mail-pf1-x432.google.com with SMTP id\n d2e1a72fcca58-82735a41920so3560381b3a.2\n for ; Sat, 25 Apr 2026 06:19:10 -0700 (PDT)","from donnager-debian.. ([45.124.203.19])\n by smtp.gmail.com with ESMTPSA id\n d2e1a72fcca58-82f8e9f7735sm26898866b3a.21.2026.04.25.06.19.03\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Sat, 25 Apr 2026 06:19:09 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=gmail.com; s=20251104; t=1777123150; x=1777727950; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:sender:from:to:cc:subject:date\n :message-id:reply-to;\n bh=yoGuy7Y7mcp7aomRMsnsXeq4e2FJ2nZOLuRGsrIDzxY=;\n b=nzX0mzp/Ar2rwwhnA/ZlqIL3q/sjD46N/rZg6T/ZyUI8QkRSsuoaTHXQKbx6GUsso7\n TOduHPohC3byo9beY6Lt7G+DUqT4URjev1QYdu41Yb/8XnAOwvhlqMPMeolRPShcKhlA\n MjHeuOvR8Z4/Qpj5j37qwPWpSepqaTVi9wGycs5ZiX+LdrLFUOcZggHKYRRGi7rmCSMT\n byjaJ54gJnTASObF+hHu/EYKwWCT+lXdGiQ4ontthvyEojrcdnk2G26OK8ghA+CiGX3J\n tUYdg3mkEJIifxib06zS19OBnMKynhuBuADr+ICmZzCu9l1byBR+QUBSJROFwoMctpdD\n +Grg==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1777123150; x=1777727950;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:sender:x-gm-gg\n :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to;\n bh=yoGuy7Y7mcp7aomRMsnsXeq4e2FJ2nZOLuRGsrIDzxY=;\n b=igzO+BJRu3gQXzIv226gyq03gqYkYq5n/vaqZA7lLz7VA6FGizfAuJufHuOcPOJcFk\n 1cORh2CELKx2uBn9V2Y8kYqiYIB9v8WOjhBwzTsO2o+CZ21pQY1EbKqEXcSO82VEycM6\n 8kq0sDNND2VlJLYP/tafsnVtfVYOQAP8bvNrqNiGqZuG/84Klm1VHkq5651xITtNhkzG\n m7uaa16Fq94s2HSh4WsLaAbydBXs2vu9I1zgw+o90nP9q0tCa+/ArToeKprSu5Q8yoK8\n yEJ961zxLYFOub+/s4VqVJJnKryNkRlM9ZP2BGdg0iS+m8n55UkRD4INUyki4bj5JSp/\n zEdg==","X-Forwarded-Encrypted":"i=1;\n AFNElJ+IRbBN5LgVh+o42xIXHafjmsA/8aaGAN9bLJcN+XuNcn82TLwrRn2DjLAcudOqw9rR2UNJqvOLOKpz@nongnu.org","X-Gm-Message-State":"AOJu0YxK3OoHTcKrZyYy64Yy+ihDIbxWR1bojA7TPNbs6PXUm0G+hB73\n kL+viY4In1suZeRsSH98a1+6hivKAWvgalWQKMZE+yiqYJ3/fhgE9y3H","X-Gm-Gg":"AeBDietG4tBCFXRyhmkPKNtjMDE2hzcqBmrp5M2/bzesupWouhaPZLQvvtvSIpRNOvJ\n wT2IkZ93fd300geAr6Gqx1kM702Ib+gp+V+gSPck38ZuDsWEvlgv2sF6uPjjCMM/mi0ebwlAeFd\n yYFeRzEdoDFQGcHmep76yDqo5e44QQNQ1NWybSxNUo3Qhz0LqfCZhiRL3h+ASERIDDkgd0I65Gg\n zvg3j+xTimgjvwnRZatiVb3rtjqCAp8wCeIBWhQFf2/9Cqx+sl16ROvaCyJ9+wpvAc0EEvAgzJz\n PhUWZCrZHJQArXB4lCMFrecd65MflZBvZvNcr9RSrClNLlMhB+qBezBwT7CEfy2k5w+OtxZL3ME\n 06SpjajdOl30cQLbODLDsEAGSVY7gMhye0iDdF4vsLhHqMiprIgL/JsOPdOX1xDTCGi2nHwxwZx\n 5d4FoaM2lVzCzc43uDBm1CR7M3fjnHsDzj6P/sJPdxT4p2GilPDUejuw7UkWKBkjKJ+C2ZPLj55\n mdf5vQ4pFjlG5Vy2emCpDI+xBXQpGbR","X-Received":"by 2002:a05:6a00:4b01:b0:82f:390a:69df with SMTP id\n d2e1a72fcca58-82f8c8d616emr38415084b3a.35.1777123149725;\n Sat, 25 Apr 2026 06:19:09 -0700 (PDT)","From":"Joel Stanley ","To":"Alistair Francis ,\n Daniel Henrique Barboza ","Cc":"Chao Liu , Michael Ellerman ,\n Nicholas Piggin , Joel Stanley ,\n Anirudh Srinivasan ,\n Portia Stephens , qemu-riscv@nongnu.org,\n qemu-devel@nongnu.org,\n =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= ","Subject":"[PATCH v4 12/13] hw/riscv/atlantis: Integrate i2c buses","Date":"Sat, 25 Apr 2026 23:17:18 +1000","Message-ID":"<20260425131721.932250-13-joel@jms.id.au>","X-Mailer":"git-send-email 2.47.3","In-Reply-To":"<20260425131721.932250-1-joel@jms.id.au>","References":"<20260425131721.932250-1-joel@jms.id.au>","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2607:f8b0:4864:20::432;\n envelope-from=joel.stan@gmail.com; helo=mail-pf1-x432.google.com","X-Spam_score_int":"-16","X-Spam_score":"-1.7","X-Spam_bar":"-","X-Spam_report":"(-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.001,\n FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=no autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Now that we have the DesignWare model we can add buses to the\ntt-atlantis machine.\n\nProvide a fixed clock in the device tree so that the Linux driver probes\nwithout WARNing.\n\nReviewed-by: Philippe Mathieu-Daudé \nSigned-off-by: Joel Stanley \n---\nv3:\n - Add device tree clock\nv2:\n - Correct count from 4 to 5\n - Fix headers location\n - Use HWADDR_PRIX to be consistent\n---\n include/hw/riscv/tt_atlantis.h | 13 +++++++++\n hw/riscv/tt_atlantis.c | 53 ++++++++++++++++++++++++++++++++++\n hw/riscv/Kconfig | 1 +\n 3 files changed, 67 insertions(+)","diff":"diff --git a/include/hw/riscv/tt_atlantis.h b/include/hw/riscv/tt_atlantis.h\nindex 070f53eeb450..a19a8cc0773f 100644\n--- a/include/hw/riscv/tt_atlantis.h\n+++ b/include/hw/riscv/tt_atlantis.h\n@@ -11,12 +11,15 @@\n \n #include \"hw/core/boards.h\"\n #include \"hw/core/sysbus.h\"\n+#include \"hw/i2c/designware_i2c.h\"\n #include \"hw/intc/riscv_imsic.h\"\n #include \"hw/riscv/riscv_hart.h\"\n \n #define TYPE_TT_ATLANTIS_MACHINE MACHINE_TYPE_NAME(\"tt-atlantis\")\n OBJECT_DECLARE_SIMPLE_TYPE(TTAtlantisState, TT_ATLANTIS_MACHINE)\n \n+#define TT_ATL_NUM_I2C 5\n+\n typedef struct {\n hwaddr pcie_addr; /* Device side address */\n hwaddr window_offset; /* Host side offset */\n@@ -37,12 +40,18 @@ struct TTAtlantisState {\n RISCVHartArrayState soc;\n DeviceState *irqchip;\n GPEXHost gpex_host;\n+ DesignWareI2CState i2c[TT_ATL_NUM_I2C];\n \n int fdt_size;\n };\n \n enum {\n TT_ATL_SYSCON_IRQ = 10,\n+ TT_ATL_I2C0_IRQ = 33,\n+ TT_ATL_I2C1_IRQ = 34,\n+ TT_ATL_I2C2_IRQ = 35,\n+ TT_ATL_I2C3_IRQ = 36,\n+ TT_ATL_I2C4_IRQ = 37,\n TT_ATL_UART0_IRQ = 38,\n TT_ATL_UART1_IRQ = 39,\n TT_ATL_UART2_IRQ = 40,\n@@ -58,6 +67,10 @@ enum {\n TT_ATL_DDR_HI,\n TT_ATL_FW_CFG,\n TT_ATL_I2C0,\n+ TT_ATL_I2C1,\n+ TT_ATL_I2C2,\n+ TT_ATL_I2C3,\n+ TT_ATL_I2C4,\n TT_ATL_MAPLIC,\n TT_ATL_MIMSIC,\n TT_ATL_PCIE_ECAM0,\ndiff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c\nindex 1eb473907ad7..d517d0aee2d1 100644\n--- a/hw/riscv/tt_atlantis.c\n+++ b/hw/riscv/tt_atlantis.c\n@@ -71,6 +71,11 @@ static const MemMapEntry tt_atlantis_memmap[] = {\n [TT_ATL_TIMER] = { 0xa8020000, 0x10000 },\n [TT_ATL_WDT0] = { 0xa8030000, 0x10000 },\n [TT_ATL_UART0] = { 0xb0100000, 0x10000 },\n+ [TT_ATL_I2C0] = { 0xb0400000, 0x10000 },\n+ [TT_ATL_I2C1] = { 0xb0500000, 0x10000 },\n+ [TT_ATL_I2C2] = { 0xb0600000, 0x10000 },\n+ [TT_ATL_I2C3] = { 0xb0700000, 0x10000 },\n+ [TT_ATL_I2C4] = { 0xb0800000, 0x10000 },\n [TT_ATL_MAPLIC] = { 0xcc000000, 0x4000000 },\n [TT_ATL_SAPLIC] = { 0xe8000000, 0x4000000 },\n [TT_ATL_DDR_HI] = { 0x100000000, 0x1000000000 },\n@@ -484,10 +489,36 @@ static void create_fdt_fw_cfg(void *fdt, const MemMapEntry *mem)\n qemu_fdt_setprop(fdt, name, \"dma-coherent\", NULL, 0);\n }\n \n+static void create_fdt_clk(void *fdt, const char *name, uint32_t clk_phandle)\n+{\n+ qemu_fdt_add_subnode(fdt, name);\n+ qemu_fdt_setprop_string(fdt, name, \"compatible\", \"fixed-clock\");\n+ qemu_fdt_setprop_cell(fdt, name, \"#clock-cells\", 0);\n+ qemu_fdt_setprop_cell(fdt, name, \"clock-frequency\", 100000000);\n+ qemu_fdt_setprop_cell(fdt, name, \"phandle\", clk_phandle);\n+}\n+\n+static void create_fdt_i2c(void *fdt, const MemMapEntry *mem, uint32_t irq,\n+ uint32_t irqchip_phandle, uint32_t clk_phandle)\n+{\n+ g_autofree char *name = g_strdup_printf(\"/soc/i2c@%\"HWADDR_PRIX, mem->base);\n+\n+ qemu_fdt_add_subnode(fdt, name);\n+ qemu_fdt_setprop_string(fdt, name, \"compatible\", \"snps,designware-i2c\");\n+ qemu_fdt_setprop_sized_cells(fdt, name, \"reg\", 2, mem->base, 2, mem->size);\n+ qemu_fdt_setprop_cell(fdt, name, \"interrupt-parent\", irqchip_phandle);\n+ qemu_fdt_setprop_cells(fdt, name, \"interrupts\", irq, 0x4);\n+ qemu_fdt_setprop_cell(fdt, name, \"clocks\", clk_phandle);\n+ qemu_fdt_setprop_cell(fdt, name, \"clock-frequency\", 100000);\n+ qemu_fdt_setprop_cell(fdt, name, \"#address-cells\", 1);\n+ qemu_fdt_setprop_cell(fdt, name, \"#size-cells\", 0);\n+}\n+\n static void finalize_fdt(TTAtlantisState *s)\n {\n uint32_t aplic_s_phandle = next_phandle();\n uint32_t imsic_s_phandle = next_phandle();\n+ uint32_t periph_clk_phandle = next_phandle();\n void *fdt = MACHINE(s)->fdt;\n \n create_fdt_cpu(s, s->memmap, aplic_s_phandle, imsic_s_phandle);\n@@ -512,6 +543,15 @@ static void finalize_fdt(TTAtlantisState *s)\n \n create_fdt_uart(fdt, &s->memmap[TT_ATL_UART0], TT_ATL_UART0_IRQ,\n aplic_s_phandle);\n+\n+ create_fdt_clk(fdt, \"/periph-clk\", periph_clk_phandle);\n+\n+ for (int i = 0; i < TT_ATL_NUM_I2C; i++) {\n+ create_fdt_i2c(fdt,\n+ &s->memmap[TT_ATL_I2C0 + i],\n+ TT_ATL_I2C0_IRQ + i,\n+ aplic_s_phandle, periph_clk_phandle);\n+ }\n }\n \n static void create_fdt(TTAtlantisState *s)\n@@ -821,6 +861,19 @@ static void tt_atlantis_machine_init(MachineState *machine)\n qdev_get_gpio_in(s->irqchip, TT_ATL_UART0_IRQ),\n 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN);\n \n+ /* I2C */\n+ for (int i = 0; i < TT_ATL_NUM_I2C; i++) {\n+ object_initialize_child(OBJECT(s), \"i2c[*]\", &s->i2c[i],\n+ TYPE_DESIGNWARE_I2C);\n+ sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), &error_fatal);\n+ SysBusDevice *sbd = SYS_BUS_DEVICE(&s->i2c[i]);\n+ memory_region_add_subregion(system_memory,\n+ s->memmap[TT_ATL_I2C0 + i].base,\n+ sysbus_mmio_get_region(sbd, 0));\n+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,\n+ qdev_get_gpio_in(s->irqchip, TT_ATL_I2C0_IRQ + i));\n+ }\n+\n /* Load or create device tree */\n if (machine->dtb) {\n machine->fdt = load_device_tree(machine->dtb, &s->fdt_size);\ndiff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig\nindex f13a05c7b1d1..2db8f409b926 100644\n--- a/hw/riscv/Kconfig\n+++ b/hw/riscv/Kconfig\n@@ -135,6 +135,7 @@ config TENSTORRENT\n select RISCV_APLIC\n select RISCV_IMSIC\n select FW_CFG_DMA\n+ select DESIGNWARE_I2C\n \n config XIANGSHAN_KUNMINGHU\n bool\n","prefixes":["v4","12/13"]}