{"id":2227864,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2227864/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20260424111330.702272-18-changhuang.liang@starfivetech.com/","project":{"id":42,"url":"http://patchwork.ozlabs.org/api/1.1/projects/42/?format=json","name":"Linux GPIO development","link_name":"linux-gpio","list_id":"linux-gpio.vger.kernel.org","list_email":"linux-gpio@vger.kernel.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260424111330.702272-18-changhuang.liang@starfivetech.com>","date":"2026-04-24T11:13:27","name":"[v1,17/20] dt-bindings: pinctrl: Add starfive,jhb100-per3-pinctrl","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"121931874df03c3941adfc81814ad595a776d1f1","submitter":{"id":85771,"url":"http://patchwork.ozlabs.org/api/1.1/people/85771/?format=json","name":"Changhuang Liang","email":"changhuang.liang@starfivetech.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20260424111330.702272-18-changhuang.liang@starfivetech.com/mbox/","series":[{"id":501347,"url":"http://patchwork.ozlabs.org/api/1.1/series/501347/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/list/?series=501347","date":"2026-04-24T11:13:16","name":"Add basic pinctrl drivers for JHB100 SoC","version":1,"mbox":"http://patchwork.ozlabs.org/series/501347/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2227864/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2227864/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-gpio@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n 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33bba334-af17-49da-3c11-08dea1f2967f","X-MS-Exchange-CrossTenant-AuthSource":"\n ZQ4PR01MB1202.CHNPR01.prod.partner.outlook.cn","X-MS-Exchange-CrossTenant-AuthAs":"Internal","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"24 Apr 2026 11:14:01.3286\n (UTC)","X-MS-Exchange-CrossTenant-FromEntityHeader":"Hosted","X-MS-Exchange-CrossTenant-Id":"06fe3fa3-1221-43d3-861b-5a4ee687a85c","X-MS-Exchange-CrossTenant-MailboxType":"HOSTED","X-MS-Exchange-CrossTenant-UserPrincipalName":"\n P7g2lea13EHSsXTBgnBhCqTofhcw/lgEvEkQ3I+qSv4uathHYB3xQnx9X25MrL0mxpa2ije1WB2J/iRY8tss+OcVtR1yla5w18piDN9CCIz4zk37HA9AiWBvQGAVNff3","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"ZQ4PR01MB1156"},"content":"Add pinctrl bindings for StarFive JHB100 SoC Peripheral-3(per3) pinctrl\ncontroller.\n\nSigned-off-by: Changhuang Liang \n---\n .../pinctrl/starfive,jhb100-per3-pinctrl.yaml | 177 ++++++++++++++++++\n 1 file changed, 177 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per3-pinctrl.yaml","diff":"diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per3-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per3-pinctrl.yaml\nnew file mode 100644\nindex 000000000000..263392a5774c\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per3-pinctrl.yaml\n@@ -0,0 +1,177 @@\n+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/pinctrl/starfive,jhb100-per3-pinctrl.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: StarFive JHB100 Peripheral-3 Pin Controller\n+\n+description: |\n+ Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd.\n+\n+ The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1,\n+ per2, per2pok, per3, adc0, adc1, emmc, and vga.\n+ This document provides an overview of the \"per3\" pinctrl domain.\n+\n+ The \"per3\" domain has a pin controller which provides\n+ - function selection for GPIO pads.\n+ - GPIO interrupt handling.\n+\n+ In the Peripheral-3 Pin Controller, there are 11 multi-function GPIO_PADs. Each of them\n+ can be multiplexed to several peripherals through function selection. Each iopad has a\n+ maximum of up to 2 functions - 0 and 1. Function 0 is the default function which is\n+ generally the GPIO function. Function 1 is the alternate function or peripheral signal\n+ that can be routed to an iopad. The function selection can be carried out by writing\n+ the function number to the iopad function select register.\n+ Each iopad is configurable with parameters such as input-enable, internal pull-up/pull-down\n+ bias, drive strength, schmitt trigger, slew rate, and debounce width.\n+\n+ This domain contains an IO group which support voltage levels 1.8V, 2.5V, and 3.3V\n+ 1. gpios - comprises PAD_GPIO_E0 through PAD_GPIO_E10.\n+\n+ Each of the above IO groups must be configured with a voltage setting that matches the external\n+ voltage level provided to the IO group.\n+\n+maintainers:\n+ - Alex Soo \n+\n+properties:\n+ compatible:\n+ items:\n+ - const: starfive,jhb100-per3-pinctrl\n+\n+ reg:\n+ maxItems: 1\n+\n+ clocks:\n+ maxItems: 1\n+\n+ resets:\n+ maxItems: 1\n+\n+ interrupts:\n+ maxItems: 1\n+\n+ interrupt-controller: true\n+\n+ '#interrupt-cells':\n+ const: 2\n+\n+ gpio-controller: true\n+\n+ '#gpio-cells':\n+ const: 2\n+\n+ gpio-ranges:\n+ maxItems: 1\n+\n+ gpio-line-names: true\n+\n+ gpios-vref:\n+ default: 0\n+ description: |\n+ Voltage reference value for the IO group \"gpios\"\n+ 0: voltage reference value for 3.3V\n+ 1: voltage reference value for 2.5V\n+ 2: voltage reference value for 1.8V\n+ $ref: /schemas/types.yaml#/definitions/uint32\n+ enum: [0, 1, 2]\n+\n+patternProperties:\n+ '-grp$':\n+ type: object\n+ additionalProperties: false\n+ patternProperties:\n+ '-pins$':\n+ type: object\n+ description: |\n+ A pinctrl node should contain at least one subnode representing the\n+ pinctrl groups available in the domain. Each subnode will list the\n+ pins it needs, and how they should be configured, with regard to\n+ function selection, bias, input enable/disable, input schmitt\n+ trigger enable/disable, slew-rate and drive strength.\n+ allOf:\n+ - $ref: /schemas/pinctrl/pincfg-node.yaml\n+ - $ref: /schemas/pinctrl/pinmux-node.yaml\n+ unevaluatedProperties: false\n+\n+ properties:\n+ pinmux:\n+ description: |\n+ The list of GPIOs and their function select.\n+ The PINMUX macros are used to configure the\n+ function selection.\n+\n+ bias-disable: true\n+\n+ bias-pull-up:\n+ type: boolean\n+\n+ bias-pull-down:\n+ type: boolean\n+\n+ drive-strength:\n+ enum: [ 2, 4, 8, 12 ]\n+\n+ drive-strength-microamp:\n+ enum: [ 2000, 4000, 8000, 12000 ]\n+\n+ input-enable: true\n+\n+ input-disable: true\n+\n+ input-schmitt-enable: true\n+\n+ input-schmitt-disable: true\n+\n+ slew-rate:\n+ enum: [ 0, 1 ]\n+ default: 0\n+ description: |\n+ 0: slow (half frequency)\n+ 1: fast\n+\n+ starfive,gmac-vsel:\n+ $ref: /schemas/types.yaml#/definitions/uint32\n+ default: 0\n+ description:\n+ RGMII mode voltage select 0 = 1.8V/3.3V, 1 = 2.5V\n+ enum: [0, 1]\n+\n+ starfive,debounce-width:\n+ $ref: /schemas/types.yaml#/definitions/uint32\n+ default: 0\n+ description:\n+ Debounce width 0 = Disabled, Others = 80ns*N stages\n+\n+required:\n+ - compatible\n+ - reg\n+ - resets\n+ - interrupts\n+ - interrupt-controller\n+ - '#interrupt-cells'\n+ - gpio-controller\n+ - '#gpio-cells'\n+ - gpio-ranges\n+\n+additionalProperties: false\n+\n+examples:\n+ - |\n+ soc {\n+ #address-cells = <2>;\n+ #size-cells = <2>;\n+\n+ pinctrl_per3: pinctrl@11c42000 {\n+ compatible = \"starfive,jhb100-per3-pinctrl\";\n+ reg = <0x0 0x11c42000 0x0 0x1000>;\n+ resets = <&per3crg 6>;\n+ interrupts = <64>;\n+ interrupt-controller;\n+ #interrupt-cells = <2>;\n+ gpio-controller;\n+ #gpio-cells = <2>;\n+ gpio-ranges = <&pinctrl_per3 0 0 11>;\n+ };\n+ };\n","prefixes":["v1","17/20"]}