{"id":2227773,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2227773/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424083837.214947-6-adityag@linux.ibm.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260424083837.214947-6-adityag@linux.ibm.com>","date":"2026-04-24T08:38:32","name":"[v6,05/10] pnv/mpipl: Preserve CPU registers after crash","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"08919d90a1ccc17aaa306ff53170e4adb6744a29","submitter":{"id":86610,"url":"http://patchwork.ozlabs.org/api/1.1/people/86610/?format=json","name":"Aditya Gupta","email":"adityag@linux.ibm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424083837.214947-6-adityag@linux.ibm.com/mbox/","series":[{"id":501318,"url":"http://patchwork.ozlabs.org/api/1.1/series/501318/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501318","date":"2026-04-24T08:38:28","name":"Implement MPIPL for PowerNV","version":6,"mbox":"http://patchwork.ozlabs.org/series/501318/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2227773/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2227773/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256\n header.s=pp1 header.b=O6JOYQzH;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n 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b=O6JOYQzHXJTHU/aQMJ+IVONIeVJujVjPx\n +v4gUYOYqrLGSU9gjCDwSjoJO8rX/4R1DUtnPYtY79EQScgXJjLjFlvugJKQ7E+9\n gEysdU7INN3t2W5LD2UPoOHJOXMSehEZDk4PQTJl6f7hFV5kVLLZ1P9ODwDxum+Z\n XaqrfyApu38POseoXksjcxj7dlU4AADTlM9hX/h3RK2/yX69IcgO6mG6y4uICfID\n oSa1RkbmILL9M+KluD0HONRP04BUbHPOYexO7sWyt5/6B2xs7JuDD7MjXhfoGdvP\n PgJV59I38yT/LdTaMKqlIXKOv82OsxexysQ5+92ZCJO9zb++KJG+A==","From":"Aditya Gupta ","To":"","Cc":", Hari Bathini ,\n Sourabh Jain ,\n Harsh Prateek Bora ,\n Nicholas Piggin ,\n Miles Glenn , Chinmay Rath ,\n Shivang Upadhyay ","Subject":"[PATCH v6 05/10] pnv/mpipl: Preserve CPU registers after crash","Date":"Fri, 24 Apr 2026 14:08:32 +0530","Message-ID":"<20260424083837.214947-6-adityag@linux.ibm.com>","X-Mailer":"git-send-email 2.53.0","In-Reply-To":"<20260424083837.214947-1-adityag@linux.ibm.com>","References":"<20260424083837.214947-1-adityag@linux.ibm.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-TM-AS-GCONF":"00","X-Proofpoint-Reinject":"loops=2 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autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Kernel expects the platform to provide CPU registers after pausing\nexecution of the CPUs.\n\nCurrently only exporting the registers, used by Linux, for generating\nthe /proc/vmcore\n\nReviewed-by: Hari Bathini \nReviewed-by: Sourabh Jain \nSigned-off-by: Aditya Gupta \n---\n hw/ppc/pnv_mpipl.c | 154 +++++++++++++++++++++++++++++++++++++\n include/hw/ppc/pnv_mpipl.h | 60 +++++++++++++++\n 2 files changed, 214 insertions(+)","diff":"diff --git a/hw/ppc/pnv_mpipl.c b/hw/ppc/pnv_mpipl.c\nindex cef1fe2c4056..308948b829cd 100644\n--- a/hw/ppc/pnv_mpipl.c\n+++ b/hw/ppc/pnv_mpipl.c\n@@ -8,6 +8,9 @@\n #include \"qemu/log.h\"\n #include \"qemu/units.h\"\n #include \"system/address-spaces.h\"\n+#include \"system/cpus.h\"\n+#include \"system/hw_accel.h\"\n+#include \"system/memory.h\"\n #include \"system/runstate.h\"\n #include \"hw/ppc/pnv.h\"\n #include \"hw/ppc/pnv_mpipl.h\"\n@@ -17,6 +20,8 @@\n (pnv->mpipl_state.skiboot_base + MDST_TABLE_OFF)\n #define MDDT_TABLE_RELOCATED \\\n (pnv->mpipl_state.skiboot_base + MDDT_TABLE_OFF)\n+#define PROC_DUMP_RELOCATED \\\n+ (pnv->mpipl_state.skiboot_base + PROC_DUMP_AREA_OFF)\n \n /*\n * Preserve the memory regions as pointed by MDST table\n@@ -169,9 +174,158 @@ static bool pnv_mpipl_preserve_mem(PnvMachineState *pnv)\n return true;\n }\n \n+static void do_store_cpu_regs(CPUState *cpu, MpiplPreservedCPUState *state)\n+{\n+ CPUPPCState *env = cpu_env(cpu);\n+ MpiplRegDataHdr *regs_hdr = &state->hdr;\n+ MpiplRegEntry *reg_entries = state->reg_entries;\n+ MpiplRegEntry *curr_reg_entry;\n+ uint32_t num_saved_regs = 0;\n+\n+ cpu_synchronize_state(cpu);\n+\n+ regs_hdr->pir = cpu_to_be32(env->spr[SPR_PIR]);\n+\n+ /* QEMU CPUs are not in Power Saving Mode */\n+ regs_hdr->core_state = 0xff;\n+\n+ regs_hdr->off_regentries = 0;\n+ regs_hdr->num_regentries = cpu_to_be32(NUM_REGS_PER_CPU);\n+\n+ regs_hdr->alloc_size = cpu_to_be32(sizeof(MpiplRegEntry));\n+ regs_hdr->act_size = cpu_to_be32(sizeof(MpiplRegEntry));\n+\n+#define REG_TYPE_GPR 0x1\n+#define REG_TYPE_SPR 0x2\n+#define REG_TYPE_TIMA 0x3\n+\n+/*\n+ * ID numbers used by f/w while populating certain registers\n+ *\n+ * Copied these defines from the linux kernel\n+ */\n+#define REG_ID_NIP 0x7D0\n+#define REG_ID_MSR 0x7D1\n+#define REG_ID_CCR 0x7D2\n+\n+ curr_reg_entry = reg_entries;\n+\n+#define REG_ENTRY(type, num, val) \\\n+ do { \\\n+ curr_reg_entry->reg_type = cpu_to_be32(type); \\\n+ curr_reg_entry->reg_num = cpu_to_be32(num); \\\n+ curr_reg_entry->reg_val = cpu_to_be64(val); \\\n+ ++curr_reg_entry; \\\n+ ++num_saved_regs; \\\n+ } while (0)\n+\n+ /* Save the GPRs */\n+ for (int gpr_id = 0; gpr_id < 32; ++gpr_id) {\n+ REG_ENTRY(REG_TYPE_GPR, gpr_id, env->gpr[gpr_id]);\n+ }\n+\n+ REG_ENTRY(REG_TYPE_SPR, SPR_ACOP, env->spr[SPR_ACOP]);\n+ REG_ENTRY(REG_TYPE_SPR, SPR_AMR, env->spr[SPR_AMR]);\n+ REG_ENTRY(REG_TYPE_SPR, SPR_BESCR, env->spr[SPR_BESCR]);\n+ REG_ENTRY(REG_TYPE_SPR, SPR_CFAR, env->spr[SPR_CFAR]);\n+ REG_ENTRY(REG_TYPE_SPR, SPR_CIABR, env->spr[SPR_CIABR]);\n+\n+ REG_ENTRY(REG_TYPE_SPR, SPR_CTR, env->spr[SPR_CTR]);\n+ REG_ENTRY(REG_TYPE_SPR, SPR_CTRL, env->spr[SPR_CTRL]);\n+ REG_ENTRY(REG_TYPE_SPR, SPR_DABR, env->spr[SPR_DABR]);\n+ REG_ENTRY(REG_TYPE_SPR, SPR_DABRX, env->spr[SPR_DABRX]);\n+ REG_ENTRY(REG_TYPE_SPR, SPR_DAR, env->spr[SPR_DAR]);\n+ REG_ENTRY(REG_TYPE_SPR, SPR_DAWR0, env->spr[SPR_DAWR0]);\n+ REG_ENTRY(REG_TYPE_SPR, SPR_DAWR1, env->spr[SPR_DAWR1]);\n+ REG_ENTRY(REG_TYPE_SPR, SPR_DAWRX0, env->spr[SPR_DAWRX0]);\n+ REG_ENTRY(REG_TYPE_SPR, SPR_DAWRX1, env->spr[SPR_DAWRX1]);\n+ REG_ENTRY(REG_TYPE_SPR, SPR_DPDES, env->spr[SPR_DPDES]);\n+ REG_ENTRY(REG_TYPE_SPR, SPR_DSCR, env->spr[SPR_DSCR]);\n+ REG_ENTRY(REG_TYPE_SPR, SPR_DSISR, env->spr[SPR_DSISR]);\n+ REG_ENTRY(REG_TYPE_SPR, SPR_EBBHR, env->spr[SPR_EBBHR]);\n+ REG_ENTRY(REG_TYPE_SPR, SPR_EBBRR, env->spr[SPR_EBBRR]);\n+\n+ REG_ENTRY(REG_TYPE_SPR, SPR_FSCR, env->spr[SPR_FSCR]);\n+\n+ REG_ENTRY(REG_TYPE_SPR, SPR_CTR, env->ctr);\n+ REG_ENTRY(REG_TYPE_SPR, SPR_DAR, env->spr[SPR_DAR]);\n+ REG_ENTRY(REG_TYPE_SPR, SPR_DSISR, env->spr[SPR_DSISR]);\n+ REG_ENTRY(REG_TYPE_SPR, SPR_LR, env->lr);\n+ REG_ENTRY(REG_TYPE_SPR, REG_ID_MSR, env->msr);\n+ REG_ENTRY(REG_TYPE_SPR, REG_ID_NIP, env->nip);\n+ REG_ENTRY(REG_TYPE_SPR, SPR_XER, env->xer);\n+ REG_ENTRY(REG_TYPE_SPR, SPR_SRR0, env->spr[SPR_SRR0]);\n+ REG_ENTRY(REG_TYPE_SPR, SPR_SRR1, env->spr[SPR_SRR1]);\n+ REG_ENTRY(REG_TYPE_SPR, SPR_HSRR0, env->spr[SPR_HSRR0]);\n+ REG_ENTRY(REG_TYPE_SPR, SPR_HSRR1, env->spr[SPR_HSRR1]);\n+ REG_ENTRY(REG_TYPE_SPR, SPR_CFAR, env->spr[SPR_CFAR]);\n+ REG_ENTRY(REG_TYPE_SPR, SPR_HMER, env->spr[SPR_HMER]);\n+ REG_ENTRY(REG_TYPE_SPR, SPR_HMEER, env->spr[SPR_HMEER]);\n+\n+ /*\n+ * Ensure the number of registers saved match the number of\n+ * registers per cpu\n+ *\n+ * This will help catch an error if in future a new register entry\n+ * is added/removed while not modifying NUM_PER_CPU_REGS\n+ */\n+ assert(num_saved_regs == NUM_REGS_PER_CPU);\n+}\n+\n+static bool pnv_mpipl_preserve_cpu_state(PnvMachineState *pnv)\n+{\n+ MachineState *machine = MACHINE(pnv);\n+ uint32_t num_cpus = machine->smp.cpus;\n+ MpiplPreservedCPUState *state;\n+ CPUState *cpu;\n+ AddressSpace *default_as = &address_space_memory;\n+ MemTxResult io_result;\n+ MemTxAttrs attrs;\n+\n+ /* Mark the memory transactions as privileged memory access */\n+ attrs.user = 0;\n+ attrs.memory = 1;\n+\n+ if (pnv->mpipl_state.cpu_states) {\n+ /*\n+ * CPU States might have been allocated from some past crash, free the\n+ * memory to preven memory leak\n+ */\n+ g_free(pnv->mpipl_state.cpu_states);\n+ pnv->mpipl_state.num_cpu_states = 0;\n+ }\n+\n+ pnv->mpipl_state.cpu_states = g_malloc_n(num_cpus,\n+ sizeof(MpiplPreservedCPUState));\n+ pnv->mpipl_state.num_cpu_states = num_cpus;\n+\n+ state = pnv->mpipl_state.cpu_states;\n+\n+ /* Preserve the Processor Dump Area */\n+ io_result = address_space_read(default_as, PROC_DUMP_RELOCATED, attrs,\n+ &pnv->mpipl_state.proc_area, sizeof(MpiplProcDumpArea));\n+ if (io_result != MEMTX_OK) {\n+ qemu_log_mask(LOG_GUEST_ERROR,\n+ \"MPIPL: Failed to read Proc Dump Area at: 0x\" TARGET_FMT_lx \"\\n\",\n+ PROC_DUMP_RELOCATED);\n+\n+ return false;\n+ }\n+\n+ CPU_FOREACH(cpu) {\n+ do_store_cpu_regs(cpu, state);\n+ ++state;\n+ }\n+\n+ return true;\n+}\n+\n void do_mpipl_preserve(PnvMachineState *pnv)\n {\n+ pause_all_vcpus();\n+\n pnv_mpipl_preserve_mem(pnv);\n+ pnv_mpipl_preserve_cpu_state(pnv);\n \n /* Mark next boot as Memory-preserving boot */\n pnv->mpipl_state.is_next_boot_mpipl = true;\ndiff --git a/include/hw/ppc/pnv_mpipl.h b/include/hw/ppc/pnv_mpipl.h\nindex b3d980dfefb1..aa2936caa75c 100644\n--- a/include/hw/ppc/pnv_mpipl.h\n+++ b/include/hw/ppc/pnv_mpipl.h\n@@ -17,6 +17,10 @@\n typedef struct MdstTableEntry MdstTableEntry;\n typedef struct MdrtTableEntry MdrtTableEntry;\n typedef struct MpiplPreservedState MpiplPreservedState;\n+typedef struct MpiplRegDataHdr MpiplRegDataHdr;\n+typedef struct MpiplRegEntry MpiplRegEntry;\n+typedef struct MpiplProcDumpArea MpiplProcDumpArea;\n+typedef struct MpiplPreservedCPUState MpiplPreservedCPUState;\n \n /*\n * Following offsets are copied from skiboot source code.\n@@ -49,6 +53,8 @@ typedef struct MpiplPreservedState MpiplPreservedState;\n /* HRMOR_BIT copied from skiboot */\n #define HRMOR_BIT (1ull << 63)\n \n+#define NUM_REGS_PER_CPU 66 /*(32 GPRs, 34 SPRs)*/\n+\n /*\n * Memory Dump Source Table (MDST)\n *\n@@ -95,6 +101,55 @@ static_assert(MDST_MAX_ENTRIES == MDDT_MAX_ENTRIES,\n static_assert(MDRT_MAX_ENTRIES >= MDST_MAX_ENTRIES,\n \"MDRT should support atleast having number of entries as in MDST\");\n \n+/*\n+ * Processor Dump Area\n+ *\n+ * This contains the information needed for having processor\n+ * state captured during a platform dump.\n+ *\n+ * As mentioned in HDAT, following the P9 specific format\n+ */\n+struct MpiplProcDumpArea {\n+ uint32_t thread_size; /* Size of each thread register entry */\n+#define PROC_DUMP_AREA_VERSION_P9 0x1 /* P9 format */\n+ uint8_t version;\n+ uint8_t reserved[11];\n+ uint64_t alloc_addr; /* Destination memory to place register data */\n+ uint32_t reserved2;\n+ uint32_t alloc_size; /* Allocated size */\n+ uint64_t dest_addr; /* Destination address */\n+ uint32_t reserved3;\n+ uint32_t act_size; /* Actual data size */\n+} QEMU_PACKED;\n+\n+/*\n+ * \"Architected Register Data\" in the HDAT spec\n+ *\n+ * Acts as a header to the register entries for a particular thread\n+ */\n+struct MpiplRegDataHdr {\n+ uint32_t pir; /* PIR of thread */\n+ uint8_t core_state; /* Stop state of the overall core */\n+ uint8_t reserved[3];\n+ uint32_t off_regentries; /* Offset to Register Entries Array */\n+ uint32_t num_regentries; /* Number of Register Entries in Array */\n+ uint32_t alloc_size; /* Allocated size for each Register Entry */\n+ uint32_t act_size; /* Actual size for each Register Entry */\n+} QEMU_PACKED;\n+\n+struct MpiplRegEntry {\n+ uint32_t reg_type;\n+ uint32_t reg_num;\n+ uint64_t reg_val;\n+} QEMU_PACKED;\n+\n+struct MpiplPreservedCPUState {\n+ MpiplRegDataHdr hdr;\n+\n+ /* Length of 'reg_entries' is hdr.num_regentries */\n+ MpiplRegEntry reg_entries[NUM_REGS_PER_CPU];\n+};\n+\n /* Preserved state to be saved in PnvMachineState */\n struct MpiplPreservedState {\n /* skiboot_base will be valid only after OPAL sends relocated base to SBE */\n@@ -103,6 +158,11 @@ struct MpiplPreservedState {\n \n MdrtTableEntry *mdrt_table;\n uint32_t num_mdrt_entries;\n+\n+ MpiplProcDumpArea proc_area;\n+\n+ MpiplPreservedCPUState *cpu_states;\n+ uint32_t num_cpu_states;\n };\n \n #endif\n","prefixes":["v6","05/10"]}